===== 03 RLT F32 TIMER READ LOOPS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Timer 2 reset at target (mode 0008h, 0208h for sysclock/8) read 1000 times by a loop
from RAM: lhu, k NOPs, sb to the scratchpad; cycles on timer 1 (sysclock), counts.
Timer2 sysclock, target 1, k 0: 10067 cycles; 0:667 1:333 2:0 3:0 higher:0
Timer2 sysclock, target 1, k 1: 11067 cycles; 0:667 1:333 2:0 3:0 higher:0
Timer2 sysclock, target 1, k 2: 12070 cycles; 0:1000 1:0 2:0 3:0 higher:0
Timer2 sysclock, target 1, k 3: 12067 cycles; 0:0 1:1000 2:0 3:0 higher:0
Timer2 sysclock, target 1, k 4: 12067 cycles; 0:1000 1:0 2:0 3:0 higher:0
Timer2 sysclock, target 1, k 5: 13067 cycles; 0:667 1:333 2:0 3:0 higher:0
Timer2 sysclock, target 1, k 6: 14073 cycles; 0:666 1:334 2:0 3:0 higher:0
Timer2 sysclock, target 1, k 7: 15067 cycles; 0:1000 1:0 2:0 3:0 higher:0
Timer2 sysclock, target 2, k 0: 10067 cycles; 0:500 1:499 2:1 3:0 4:0 higher:0
Timer2 sysclock, target 2, k 1: 11067 cycles; 0:500 1:250 2:250 3:0 4:0 higher:0
Timer2 sysclock, target 2, k 2: 12067 cycles; 0:1000 1:0 2:0 3:0 4:0 higher:0
Timer2 sysclock, target 2, k 3: 12067 cycles; 0:0 1:1000 2:0 3:0 4:0 higher:0
Timer2 sysclock, target 2, k 4: 12067 cycles; 0:1000 1:0 2:0 3:0 4:0 higher:0
Timer2 sysclock, target 2, k 5: 13067 cycles; 0:500 1:250 2:250 3:0 4:0 higher:0
Timer2 sysclock, target 2, k 6: 14067 cycles; 0:500 1:0 2:500 3:0 4:0 higher:0
Timer2 sysclock, target 2, k 7: 15067 cycles; 0:500 1:250 2:250 3:0 4:0 higher:0
Timer2 sysclock, target 3, k 0: 10067 cycles; 0:1 1:0 2:0 3:999 4:0 5:0 higher:0
Timer2 sysclock, target 3, k 1: 11067 cycles; 0:400 1:200 2:200 3:200 4:0 5:0 higher:0
Timer2 sysclock, target 3, k 2: 12067 cycles; 0:400 1:200 2:200 3:200 4:0 5:0 higher:0
Timer2 sysclock, target 3, k 3: 12067 cycles; 0:400 1:200 2:200 3:200 4:0 5:0 higher:0
Timer2 sysclock, target 3, k 4: 12067 cycles; 0:400 1:200 2:200 3:200 4:0 5:0 higher:0
Timer2 sysclock, target 3, k 5: 13067 cycles; 0:400 1:200 2:200 3:200 4:0 5:0 higher:0
Timer2 sysclock, target 3, k 6: 14067 cycles; 0:400 1:200 2:200 3:200 4:0 5:0 higher:0
Timer2 sysclock, target 3, k 7: 15067 cycles; 0:0 1:1000 2:0 3:0 4:0 5:0 higher:0
Timer2 sysclock, target 10, k 0: 10069 cycles; 0:166 1:0 2:166 3:0 4:166 5:0 6:168 7:0 8:167 9:0 10:167 11:0 12:0 higher:0
Timer2 sysclock, target 10, k 1: 11067 cycles; 0:168 1:84 2:83 3:83 4:83 5:83 6:83 7:83 8:83 9:83 10:84 11:0 12:0 higher:0
Timer2 sysclock, target 10, k 2: 12067 cycles; 0:0 1:1000 2:0 3:0 4:0 5:0 6:0 7:0 8:0 9:0 10:0 11:0 12:0 higher:0
Timer2 sysclock, target 10, k 3: 12067 cycles; 0:1000 1:0 2:0 3:0 4:0 5:0 6:0 7:0 8:0 9:0 10:0 11:0 12:0 higher:0
Timer2 sysclock, target 10, k 4: 12072 cycles; 0:1000 1:0 2:0 3:0 4:0 5:0 6:0 7:0 8:0 9:0 10:0 11:0 12:0 higher:0
Timer2 sysclock, target 10, k 5: 13067 cycles; 0:166 1:83 2:83 3:83 4:83 5:83 6:84 7:84 8:84 9:84 10:83 11:0 12:0 higher:0
Timer2 sysclock, target 10, k 6: 14067 cycles; 0:167 1:0 2:167 3:0 4:167 5:0 6:167 7:0 8:166 9:0 10:166 11:0 12:0 higher:0
Timer2 sysclock, target 10, k 7: 15067 cycles; 0:250 1:0 2:250 3:0 4:0 5:250 6:0 7:0 8:250 9:0 10:0 11:0 12:0 higher:0
Timer2 sysclock/8, target 10, k 0: 10067 cycles; 0:125 1:125 2:0 3:125 4:125 5:125 6:125 7:0 8:125 9:125 10:0 11:0 12:0 higher:0
Timer2 sysclock/8, target 10, k 1: 11071 cycles; 0:88 1:100 2:99 3:101 4:100 5:100 6:100 7:101 8:99 9:100 10:12 11:0 12:0 higher:0
Timer2 sysclock/8, target 10, k 2: 12067 cycles; 0:100 1:100 2:100 3:100 4:100 5:100 6:100 7:100 8:100 9:100 10:0 11:0 12:0 higher:0
Timer2 sysclock/8, target 10, k 3: 12067 cycles; 0:50 1:100 2:100 3:100 4:100 5:100 6:100 7:100 8:100 9:100 10:50 11:0 12:0 higher:0
Timer2 sysclock/8, target 10, k 4: 12067 cycles; 0:100 1:100 2:100 3:100 4:100 5:100 6:100 7:100 8:100 9:100 10:0 11:0 12:0 higher:0
Timer2 sysclock/8, target 10, k 5: 13067 cycles; 0:88 1:99 2:100 3:100 4:100 5:100 6:101 7:100 8:100 9:100 10:12 11:0 12:0 higher:0
Timer2 sysclock/8, target 10, k 6: 14067 cycles; 0:100 1:100 2:100 3:100 4:100 5:100 6:100 7:100 8:100 9:100 10:0 11:0 12:0 higher:0
Timer2 sysclock/8, target 10, k 7: 15067 cycles; 0:62 1:125 2:124 3:63 4:125 5:63 6:125 7:126 8:62 9:125 10:0 11:0 12:0 higher:0
Timer 2 sysclock, the write to the first tick on timer 1 (RC7's), 16 tries each:
mode write, cold: 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27
mode write, warm: 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22
counter write, cold: 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27 27
counter write, warm: 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22
Done.