===== 00 SIO3 SIO1 TX start phase at x1: STAT bits 0 and 2 (as 1, 4, 5) at k NOPs after the DATA write | BIOS 19951204
k:bits@timer2 (bits: 1 TX ready, 4 TX idle); timer 2 from its reset before the BAUD write
  reload 1 j 0: 0:0@8 4:1@9 14:5@19 | idle from k 14
  reload 1 j 1: 0:0@8 3:1@9 13:5@19 | idle from k 13
  reload 1 j 2: 0:0@8 2:1@9 12:5@19 | idle from k 12
  reload 1 j 3: 0:0@9 2:1@10 12:5@20 | idle from k 12
  reload 2 j 0: 0:0@8 5:1@10 25:5@30 | idle from k 25
  reload 2 j 1: 0:0@8 4:1@10 24:5@30 | idle from k 24
  reload 2 j 2: 0:0@8 3:1@10 23:5@30 | idle from k 23
  reload 2 j 3: 0:0@9 2:1@10 22:5@30 | idle from k 22
  reload 3 j 0: 0:0@8 7:1@12 37:5@42 | idle from k 37
  reload 3 j 1: 0:0@8 6:1@12 36:5@42 | idle from k 36
  reload 3 j 2: 0:0@8 5:1@12 35:5@42 | idle from k 35
  reload 3 j 3: 0:0@9 4:1@12 34:5@42 | idle from k 34
  reload 4 j 0: 0:0@8 5:1@10 45:5@50 | idle from k 45
  reload 4 j 1: 0:0@8 4:1@10 44:5@50 | idle from k 44
  reload 4 j 2: 0:0@8 3:1@10 43:5@50 | idle from k 43
  reload 4 j 3: 0:0@9 6:1@14 46:5@54 | idle from k 46
  reload 5 j 0: 0:0@8 6:1@11 56:5@61 | idle from k 56
  reload 5 j 1: 0:0@8 5:1@11 55:5@61 | idle from k 55
  reload 5 j 2: 0:0@8 4:1@11 54:5@61 | idle from k 54
  reload 5 j 3: 0:0@9 8:1@16 58:5@66 | idle from k 58
  reload 6 j 0: 0:0@8 7:1@12 67:5@72 | idle from k 67
  reload 6 j 1: 0:0@8 6:1@12 66:5@72 | idle from k 66
  reload 6 j 2: 0:0@8 5:1@12 65:5@72 | idle from k 65
  reload 6 j 3: 0:0@9 4:1@12 64:5@72 | idle from k 64
  reload 7 j 0: 0:0@8 8:1@13 78:5@83 | idle from k 78
  reload 7 j 1: 0:0@8 7:1@13 77:5@83 | idle from k 77
  reload 7 j 2: 0:0@8 6:1@13 76:5@83 | idle from k 76
  reload 7 j 3: 0:0@9 5:1@13 75:5@83 | idle from k 75
  reload 8 j 0: 0:0@8 9:1@14 89:5@94 | idle from k 89
  reload 8 j 1: 0:0@8 8:1@14 88:5@94 | idle from k 88
  reload 8 j 2: 0:0@8 7:1@14 87:5@94 | idle from k 87
  reload 8 j 3: 0:0@9 6:1@14 86:5@94 | idle from k 86