Expansion Port (PIO): Difference between revisions
| Revision as of 02:45, 23 October 2026 RemmyLee (design-study: the lede rule no longer applies to wiki pages) | Revision as of 02:46, 23 October 2026 RemmyLee (GTE, MDEC, controllers, Memory Card, SIO and expansion port at register depth) | ||
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| + | --- | ||
| + | title: Expansion Port (PIO) | ||
| + | type: component | ||
| + | summary: Parallel expansion connector that exposes the CPU bus of early PlayStation boards. | ||
| + | category: Hardware | ||
| + | --- | ||
| + | |||
| + | ## Overview | ||
| + | |||
| + | The PlayStation provides two types of expansion port, serial and parallel. The parallel port is the PIO (extended parallel port) of the PlayStation block diagram.[^hw13] [^hw15] It brings the CPU bus out to a connector on the back of the unit, so expansion hardware can place ROM, RAM or I/O ports in the address space of the CPU.[^spxpio] [^spxpin] | ||
| + | |||
| + | The port exists only on older PlayStation boards. Later PlayStation boards and all PSone boards omit the connector, although psx-spx reports that the CPU still outputs the expansion signals and that the board keeps solder points for them.[^spxpio] Most uses of the port come from third parties: cheat cartridges, Video CD adapters and the PSIO optical drive emulator.[^spxpin] | ||
| + | |||
| + | ## Connector | ||
| + | |||
| + | The connector (CN103) has 68 pins in two rows:[^spxpin] | ||
| + | |||
| + | Table: Expansion port pins | ||
| + | |||
| + | | Pins | Signals | | ||
| + | | --- | --- | | ||
| + | | 1, 16, 19, 34, 35, 50, 53, 68 | GND | | ||
| + | | 2 | /RESET | | ||
| + | | 3 | DREQ5 | | ||
| + | | 4 | /CS0 (DEV0 chip select) | | ||
| + | | 5 | GND (SBEN on the PSIO switch board) | | ||
| + | | 6 to 13, 40 to 47 | D0 to D15 | | ||
| + | | 14, 15, 20 to 29, 48, 49, 54 to 63 | A0 to A23 | | ||
| + | | 17, 51 | +3.5V | | ||
| + | | 18, 52 | +7.5V | | ||
| + | | 30 | /RD | | ||
| + | | 31 | Not connected (/IRQ2 on the PSIO switch board) | | ||
| + | | 32 | SYSCK | | ||
| + | | 33 | BCLK | | ||
| + | | 36 | DACK5 | | ||
| + | | 37 | /IRQ10 | | ||
| + | | 38 | /WR1 | | ||
| + | | 39 | GND (/CS2 on the PSIO switch board) | | ||
| + | | 64 | /WR0 | | ||
| + | | 65 | Not connected (/CS5 on the PSIO switch board) | | ||
| + | | 66 | LRCK | | ||
| + | | 67 | SDIN | | ||
| + | |||
| + | The data lines alternate between the rows: D0 is pin 6 and D1 pin 40, and so on to D15 on pin 47. The address lines alternate in the same way from A0 on pin 14.[^spxpin] | ||
| + | |||
| + | The PSIO switch board repurposes three pins. When pin 5 is high it disconnects /CS5 and /IRQ2 of the CPU from the CD-ROM drive and routes them to pins 65 and 31, so the PSIO can take the place of the drive. Pin 39 can override /CS2 and with it the BIOS ROM in the same way.[^spxpin] | ||
| + | |||
| + | A0 to A23 are latched outputs. While the CPU bus is not used for other devices they can serve as 24 general purpose outputs, because main RAM, the GPU and the internal I/O ports do not change them.[^spxpio] | ||
| + | |||
| + | ## Address Regions | ||
| + | |||
| + | The expansion hardware is reached through three regions:[^spxpio] [^spxmap] | ||
| + | |||
| + | Table: Expansion regions | ||
| + | |||
| + | | Region | Address (KUSEG) | Size | Intended use | | ||
| + | | --- | --- | --- | --- | | ||
| + | | DEV0 | 1F000000h | 8192K | ROM, with chip select /CS0 | | ||
| + | | DEV8 | 1F802000h | 8K | I/O ports, without a chip select | | ||
| + | | DEV1 | 1FA00000h | 2048K | RAM | | ||
| + | |||
| + | The BIOS sets DEV0 to 512 Kbytes with an 8-bit bus and DEV8 to 128 bytes with an 8-bit bus. The memory control registers at 1F801000h to 1F80101Ch can change the size and the bus width.[^spxpio] [^spxmc] DEV0 accepts 32-bit reads in 8-bit mode by splitting them into four 8-bit reads, so code can run directly from an expansion ROM. DEV8 appears to accept only 8-bit access.[^spxpio] | ||
| + | |||
| + | DEV8 has no chip select of its own. psx-spx therefore suggests that an address decoder treat any read or write with A13 and A23 high and A22 low as a DEV8 access.[^spxpio] DEV1 is used neither by the BIOS nor by games, and it seems to hold 1 Mbyte of 16-bit RAM on the DTL-H2000.[^spxpio] | ||
| + | |||
| + | The BIOS reads the ROM header at 1F000000h to 1F0000FFh and writes the POST register at 1F802041h. Other expansion hardware must therefore tolerate those accesses.[^spxpio] | ||
| + | |||
| + | ## Expansion ROM Header | ||
| + | |||
| + | An expansion ROM in DEV0 starts with a 256-byte header, which the BIOS reads with the 8-bit bus setting:[^spxrom] | ||
| + | |||
| + | Table: Expansion ROM header | ||
| + | |||
| + | | Address | Size | Content | | ||
| + | | --- | --- | --- | | ||
| + | | 1F000000h | 4 | Post-boot entry point (1F000100h and up) | | ||
| + | | 1F000004h | 2Ch | Post-boot ID ("Licensed by Sony Computer Entertainment Inc.") | | ||
| + | | 1F000030h | 50h | Post-boot TTY message (must contain at least one 00h byte) | | ||
| + | | 1F000080h | 4 | Pre-boot entry point (1F000100h and up) | | ||
| + | | 1F000084h | 2Ch | Pre-boot ID ("Licensed by Sony Computer Entertainment Inc.") | | ||
| + | | 1F0000B0h | 50h | Not used | | ||
| + | | 1F000100h | | Code, data and I/O ports | | ||
| + | |||
| + | The BIOS calls each entry point only when its ID string is present. The return address is passed in R31, so the expansion code may return to the BIOS. Before it calls the post-boot entry point the BIOS also prints the post-boot ID and message on the TTY.[^spxrom] | ||
| + | |||
| + | The pre-boot function runs almost immediately after reset, when only some memory control registers are set and the BIOS function tables at A0h, B0h and C0h are not yet installed. The post-boot function runs while the PS logo is shown and before the executable is loaded, when the function tables are available. Because it runs only while the PS logo is shown, it is not called when the drive is empty or holds an audio CD.[^spxrom] | ||
| + | |||
| + | psx-spx reports that cheat devices from Action Replay 2.0 on hook the kernel between the two. The pre-boot function sets a COP0 breakpoint on instruction fetch at 80030000h, and the kernel stops there after it has built its function tables.[^spxrom] | ||
| + | |||
| + | ## POST Register | ||
| + | |||
| + | During boot the BIOS writes increasing values from 00h to 0Fh to the POST register at 1F802041h. An external 7-segment display on the port can therefore show the boot status, in the way that port 80h is used on a PC.[^spxpost] | ||
| + | |||
| + | ## Serial Debug Port | ||
| + | |||
| + | The retail BIOS contains TTY debug terminal code for an SCN2681 dual UART connected to the expansion port at 1F802020h to 1F80202Fh. psx-spx reports that no known console, development board or expansion contains this chip.[^spxduart] The DTL-H2000 development board instead uses its own ATCONS channel in DEV8 for TTY output.[^spxduart] | ||
| + | |||
| + | ## References | ||
| + | |||
| + | [^hw13]: Sony Computer Entertainment Inc. PlayStation Hardware. August 1998. Page 1-3, Figure 1-1. | ||
| + | [^hw15]: Sony Computer Entertainment Inc. PlayStation Hardware. August 1998. Page 1-5. | ||
| + | [^spxpio]: psx-spx. Expansion Port (PIO). https://psx-spx.consoledev.net/expansionportpio/ | ||
| + | [^spxrom]: psx-spx. Expansion Port (PIO), DEV0 Expansion ROM Header. https://psx-spx.consoledev.net/expansionportpio/ | ||
| + | [^spxpost]: psx-spx. Expansion Port (PIO), DEV8 Post Registers. https://psx-spx.consoledev.net/expansionportpio/ | ||
| + | [^spxduart]: psx-spx. Expansion Port (PIO), DEV8 Dual Serial Port (for TTY Debug Terminal). https://psx-spx.consoledev.net/expansionportpio/ | ||
| + | [^spxpin]: psx-spx. Pinouts, Parallel Port (PIO) (Expansion Port) (CN103). https://psx-spx.consoledev.net/pinouts/ | ||
| + | [^spxmap]: psx-spx. Memory Map. https://psx-spx.consoledev.net/memorymap/ | ||
| + | [^spxmc]: psx-spx. Memory Control. https://psx-spx.consoledev.net/memorycontrol/ | ||