Hardware tests

BIOS Logo Race and Uncached Calls

Measures the BIOS shell's own instruction path through the logo race window, and calls from cached code into uncached routines, alone and during a DMA2 list.

Bus Access and Device Register Timing

Measures COM0 recovery on BIOS ROM loads, loads and stores around RAM writes, word stores to SPU registers, DMA start, MDEC control writes after a reset, root counter 0 after an hblank reset and KSEG1 stores to the scratchpad.

Bus Auto Increment

Measures what bit 13 of the delay and size registers does to 32-bit accesses to 8-bit and 16-bit devices.

Cache Control Register Bits

Measures the effect of BCC bits 11 to 17 on bus, cache and DMA timing, and what narrow reads of BCC return.

CD-ROM Audio and Data Commands

Measures how the CD-ROM drive answers Test, GetQ, seek, read, play and Init commands, and how long each takes, with no disc and with a disc of 12 tracks.

CD-ROM Commands With No Disc

Records the CD-ROM controller's answer and response time for every command with the lid open and no disc.

CD-ROM Controller Commands and Reads

Measures how the CD-ROM controller answers commands with and without a disc, and what the GTE registers hold after the undocumented opcodes.

CD-ROM Controller With a Disc

Times reads, seeks, speed changes, Stop, MotorOn and Init on the CD-ROM controller with a disc in the drive.

CD-ROM Controller With No Disc

Measures the CD-ROM controller's answers, reply times, FIFOs and registers with the lid open and no disc.

CD-ROM Position After a Hold

Compares GetlocL with GetlocP during a read that follows a 20 second pause and during a read with no pause.

CD-ROM Read After a Pause

Replays a game's two-part read sequence and records which sectors arrive and when.

CD-ROM Seek Timing

Times seeks, speed changes, Init, Pause and ReadTOC on the CD-ROM drive with a game disc in it.

Coprocessor Usable Bits

Checks which coprocessor instructions raise an exception when the coprocessor is disabled in SR.

CPU Access Time

Measures the CPU cycles that one load takes in each region of the memory map.

CPU Access Types During a DMA2 List

Measures each kind of CPU access the BIOS shell makes while a DMA2 list of empty nodes runs.

CPU Bus Gaps and Cache Isolation

Measures which unused addresses raise a bus error and how loads and stores behave with the data cache isolated.

CPU Core and Bus

Measures CPU exceptions, arithmetic results, load delays, bus errors, mirrors, cache and instruction timing.

CPU Load and Store Timing

Measures how loads, stores, uncached code, cache fills and GTE commands overlap with the instructions around them.

CPU Load Pairs and GTE Input Timing

Measures back-to-back loads, stores after loads, LWC2 and the point in each GTE command where it reads its inputs.

CPU Loads and BIOS ROM Reads

Measures back-to-back loads, timed loads in a cold cache line, a store during a DMA2 list, COP0 r6, BIOS ROM reads at read delays 0 and 1, cache line fills from the ROM and bus error loads.

CPU Loop During DMA2 and Timer Reads

Measures how much a cached CPU loop slows during DMA2 lists of different shapes, a RAM store followed by a load, and timer 2 read in a loop with reset at target and after a mode or counter write.

CPU Pipeline Timing and Cache Isolation

Measures CPU store and load sequences, uncached instruction fetch, I/O register upper halves, an interrupt taken on a GTE command, and isolated cache reads.

CPU Speed During a DMA2 List

Measures CPU loops during a DMA2 list, the BIOS shell loops that race the list at the logo, and the end of the MDEC busy bit after a table.

CPU Stores and Device Delays

Measures RAM store bursts, loads that land on a following instruction and uncached code alone and during a DMA2 list, with timer 1 toggle mode, SIO1 CTRL bit 7 and the COM0 and COM3 delay fields.

CPU Timing on BIOS DMA2 List Shapes

Measures CPU loads, stores, line fills, SPU accesses and the BIOS shell's code path while DMA2 walks lists laid out like the ones the BIOS sends during its logo.

Display Timing and GPUSTAT

Measures frame and scanline length, blanking and GPUSTAT bits 13 and 31 against the GP1 display settings.

DMA Channel 6 Ordering Table Clear

Checks how DMA channel 6 clears an ordering table and which of its control bits are fixed.

DMA Chopping

Times an 8192-byte DMA2 transfer to VRAM by block size and by chopping window.

DMA Interrupt Latency and MDEC Reset

Measures DICR interrupt latency, the upper half of I_MASK, timer 1 resets, GTE register effects, MDEC resets and FIFOs, and SPU DMA cost.

DMA List Loops

Times CPU work while DMA channel 2 walks a finished list, a list that points at itself and two entries that point at each other.

DMA Master Enable

Checks that an SPU DMA transfer runs only when its enable bit in DPCR is set.

DMA Priority Against the CPU and Between Channels

Measures whether the DPCR priority fields change how the CPU and two DMA channels share the bus.

DMA Registers and Interrupt Latency

Measures every DMA register bit, OTC lengths, DICR flags on five kinds of transfer and three-channel priority.

DMA Registers and Timer Pulse Mode

Measures OTC transfer times, the DMA registers at 1F8010F8h and 1F8010FCh, the timer reached-target bit in pulse mode, SPU register 1DA0h, the first samples after key on and the MDEC status after a reset.

DMA Start Stall and Delay Slot Fetch

Measures when the CPU waits for an OTC transfer started by a CHCR store, and the time of a call whose delay slot begins a new cache line.

DMA Timing

Measures DMA register behavior, transfer times, chopping, priorities and DICR interrupts.

DMA2 Progress and Cache Line Fills

Measures how far a DMA2 list gets while the BIOS logo race path runs, what a load, store or branch adds to a cache line fill, accesses after a load's use, and how long a held timer write waits during a list.

EXP2 Delay Register Read-back

Writes the expansion region 2 delay/size register with four values and reads each back.

Expansion Region 2 Access Width

Reads and writes expansion region 2 at every width under two bus width settings.

Generated Program Timing by Code Segment

Measures the time of 53 generated CPU programs and their smaller variants, each run from KSEG0, KSEG1 and KUSEG and at each word of a cache line.

GP0 Command FIFO Occupancy

Measures which GP0 command words take space in the GPU command FIFO.

GP0(E1h) Draw Mode

Checks which bits of GP0(E1h) reach GPUSTAT and how textured polygons change them.

GPU Bandwidth

Counts the horizontal blanks that 400 full-screen transfers and draws of 320 by 240 pixels take.

GPU Command Timing

Measures how long the GPU takes to execute fills, rectangles, triangles and VRAM copies.

GPU Draw Queue and IRQ1

Measures the IRQ1 that GP0(1Fh) raises at the end of a DMA list and the recovery of a stalled GPU.

GPU Drawing Time and Status Bits

Measures GPU drawing times for rectangles, lines, textured primitives, fills and copies, and the GPUSTAT and GPUREAD values around GP1 writes and transfers.

GPU Flat Quad Fill Time

Measures the cycles from the first command word to the GPU idle for flat quads of each size and setting and for the BIOS's shaded quad and triangles.

GPU Info Index 08h

Reads GP1(10h) index 08h and the other unused info indices on a v2 GPU.

GPU Polyline Over DMA

Sends polylines with missing or misplaced end words through DMA2 in list mode and records what the GPU draws and where DMA stops.

GPU Primitives at Game Scale

Records the pixels the GPU writes for whole triangles, quads, meshes, textured polygons and texture windows of the sizes games use.

GPU Rasterization Rules

Records which pixels the GPU writes for small triangles, quads, lines, rectangles, fills and copies.

GPU Read and Draw Behavior

Measures GPUREAD after GP0(C0h), draw times by GP0(03h) and rectangle width, timer 0 on the dot clock, texel steps, closed meshes, polyline joints and the SPU write FIFO cut by a stop.

GPU State

Measures what GPUSTAT and the GP1(10h) info indices report after each GP0 and GP1 setting and after a GP1(00h) reset.

GPU Timing at Game Scale

Measures GPU drawing time for screen-sized fills and draws and the time the display fetch takes from drawing in each video mode.

GPUSTAT Bit 13 Across Interlace Changes

Measures what GPUSTAT bit 13 reads when GP1(08h) switches into and out of 480-line interlace.

GPUSTAT DMA Bits

Reads the DMA request and ready bits of GPUSTAT around a draw in each DMA direction.

GTE Command Timing

Measures how long each GTE command keeps the CPU waiting for its result.

GTE Control Inputs and Store Widths

Measures when GTE commands read their control register inputs, and the cost of stores of each width after a load.

GTE Input Timing and CD-ROM Queries

Measures how many instructions after a GTE command its inputs can still be written, and how the CD-ROM controller answers Test 19h, GetTN, GetTD and GetQ.

GTE Input Timing and I/O Load Pairs

Measures when each GTE command reads each input, and the cost of paired loads, stores after loads and uncached loads.

GTE Lighting Input Latency

Measures how long NCT, NCCT and NCDT keep reading each input register after they start.

GTE LZCS Write Delay

Measures how soon LZCR shows the leading-bit count after a write to LZCS.

GTE Register Write Delay

Measures how many instructions pass before a written GTE register is seen by a command or a read.

GTE Register Writes and Expansion Reads

Measures which value a GTE command uses when its input is written a few instructions after it, by instruction cache state, the end of a DMA2 list of empty nodes by poll rate, and timed expansion port reads by cache line.

GTE Registers and Results

Measures how each GTE register reads back after a write and what every GTE command writes for a wide set of inputs.

GTE Timing during CPU Stalls

Measures whether a GTE command keeps running while the CPU stalls, and the cost of loads and stores from KSEG1 code by device.

GTE Undocumented Opcodes

Records which GTE data registers each undocumented command changes when it follows NCS.

GTE Write-to-Use Delay

Measures how many instructions must separate a GTE register write from the command that reads it.

Hardware Behavior Checks

Measures twelve separate points of timer, DMA, GTE, MDEC, SPU, controller port, GPU and CD-ROM behavior.

I/O Access Width

Writes 12345678h to memory and I/O registers as a byte, halfword and word and reads back what arrived.

I/O Load and Store Spacing

Measures how far apart back-to-back I/O register loads go, how an I/O or RAM store between two loads delays the second, and how long an I/O register read holds the RAM access after it.

Instruction Fetch During DMA2

Measures CPU instruction fetch while a DMA2 list runs and how long the MDEC status shows busy after a table.

Interrupt Controller and Serial Ports

Measures I_STAT and I_MASK, interrupt edges and latency, the SIO0 and SIO1 registers, byte timing and the pad protocol.

KSEG0 and KSEG1 Code Fetch

Measures how long the same short code bodies take when called through KSEG0 with the instruction cache and through KSEG1 without it.

Load and Use During a DMA2 List

Measures how a RAM load, the use of its value and the accesses around them share time with a DMA2 list.

Load Delay Slot Collisions

Measures the time a counted loop takes when the instruction in a load's delay slot, or the one after it, writes, reads or loads the load's destination register, by load width, data region and code segment.

Load Landing and Device Loads

Measures the cost of an instruction that runs as a RAM load completes, loads from each device and width, and code run from KSEG1.

MDEC Block Counter

Records each change of the MDEC status register while a stream is written and read by the CPU.

MDEC Block Timing

Measures when the MDEC status register changes during a decode, by output depth, by what came before the decode and by how the output is read, and what the MDEC outputs after an AC run past entry 63.

MDEC Hand-Made Streams

Measures the MDEC with hand-made streams that change one input at a time, the command bits, the status sequence and decode time by DMA.

MDEC Output

Measures the MDEC status register, table loads, decode output by CPU and by DMA, DMA block sizes and reset.

MDEC Reset and Store Timing

Measures whether the MDEC accepts a command written soon after a reset, and how long stores to RAM and I/O registers take.

MDEC Start and Interrupt Entry Timing

Measures when the MDEC starts after a full input FIFO, what GPUREAD returns after a VRAM read, CPU work during a DMA2 list, and how soon an enabled interrupt is taken.

MDEC Status and Decode Timing

Measures MDEC output after short decodes, the status block field during a decode, commands written while the MDEC is busy, reset in a stuck decode, DMA0 table and decode times, and a whole frame read by the CPU.

Memory Card After a Write

Measures how long the Memory Card in slot 1 stays silent after a frame write and times each byte of a frame read.

Memory Control and Bus Timing

Measures the memory control registers, bus access times by delay setting, window sizes, RAM_SIZE and cache control.

Multiply and Divide Timing

Measures how long MULT, MULTU, DIV and DIVU take for each kind of operand.

Partial Writes to I/O Registers

Measures what byte, halfword and unaligned stores do to 32-bit on-chip registers and to 16-bit SPU registers.

Peripheral Registers and Bus Delays

Measures SIO1 and SIO0 status timing, root counter target and hblank behavior, register 1F8010F8h, DMA2 chopping, DMA4 block sizes, the COM and write delays and the BIOS read delay.

RAM Access During a DMA2 List

Measures how RAM loads and stores a few cycles apart are delayed while DMA2 walks a list of empty nodes.

RAM Refresh

Measures the period and length of the RAM refresh window and which accesses wait for it.

Root Counter Behavior

Measures root counter mode bits, counter writes, flags, interrupts, periods, clock sources and sync modes.

Root Counter Clocks and Sync Modes

Measures what each root counter counts over fixed delays and frames for each clock source and sync mode.

Root Counter Mode Combinations

Runs the root counters in every combination of mode bits and records interrupts, flags and bit 10.

SIO1 Transmit Start Timing

Measures when SIO1 reports TX ready and TX idle after a byte is written at baud reload values 1 to 8.

SPU 32-bit Stores

Checks whether a 32-bit store to an SPU register loses one of its halves at any store timing.

SPU Envelope Grid and GPU Fill Timing

Measures the SPU registers as a program finds them, GPU fill times by shape, Gouraud shading steps, the shared SPU envelope step grid, 32-bit SPU stores, MDEC output left unread and the SPU DMA read with a zero delay field.

SPU Loads and Cold Calls During a DMA2 List

Measures SPU loads, calls into cold cache lines, multiply and divide reads, and RAM loads and stores, alone and while DMA2 walks a list.

SPU Memory Transfer

Checks sound RAM access through the data port and DMA channel 4.

SPU Noise Flags and Reverb

Reads the SPU registers, the voice 1 capture buffer and the reverb area to measure noise, ADPCM flag bits, key on by voice, the capture level and the reverb engine's writes.

SPU Read Timing

Times one load from the SPU and two loads in a row against the SPU delay register and COM_DELAY.

SPU Registers and Envelope

Reads the SPU's registers while it runs to measure key on and off, the ADSR envelope, volume sweeps, ENDX, IRQ9, capture and transfers.

SPU Voice After End and Mute

Uses IRQ9 to find which sound RAM blocks a voice reads after an End+Mute block sends it to its repeat address.

SPU Voice Flags and Interrupts

Measures SPU ENDX writes and clearing at key on, volume sweep limits, IRQ address timing, start addresses on an odd unit, reverb area use and sound RAM transfers.

SPU Voice Onset and Pitch

Measures the first output samples of an SPU voice after key on when its first ADPCM block is a ramp or one constant value at pitches 0400h to 2000h.

SPU Voice Start and MDEC Reset

Measures SPU voice behavior at key on, the noise generator state, the ENDX refill and the repeat address, and whether an MDEC command stored straight after a reset is taken.

SPU Wide Writes

Counts how often a 32-bit store to an SPU register pair loses a half for each tested value of the SPU delay register.

Store and Load Sequences

Measures stores and loads in sequence and the GTE inputs that commands read after they start.

Timer Sync and SIO0 Timing

Measures timer 0 and timer 1 in their blanking sync modes, single accesses from KSEG1 and the cache, the SIO0 receive interrupt and /ACK timing, and a KSEG1 loop by placement.

Timer Write and Cache Line Fills

Measures when an I/O store lands against the instruction cache fills that a following jump causes, and what each cold cache line costs.

Undrained SPU Write FIFO

Measures which halfwords of a block in the SPU write FIFO reach sound RAM when the transfer mode is set to Stop a given time after the block is sent, and what the halfwords not yet written keep.

Write Queue and GTE Interrupts

Measures runs of RAM stores, CD-ROM drive reply times, interrupts arriving on a GTE command and the spread of repeated timings.