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GTE Registers: Difference between revisions

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RemmyLee
(design-study: the lede rule no longer applies to wiki pages)		Revision as of 02:46, 23 October 2026
RemmyLee
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+---
+title: GTE Registers
+type: register
+summary: Control and data registers of the Geometry Transformation Engine.
+category: Hardware
+---
+
+## Summary
+
+The [GTE](/hardware/gte/) has 32 control registers and 32 data registers, each 32 bits wide. The CPU reads and writes the control registers with cfc2 and ctc2, and the data registers with mfc2, mtc2, lwc2 and swc2; lwc2 and swc2 transfer directly between a data register and memory.[^ipr43] The header gtereg.h names each register with the prefix C2_. FLAG is therefore C2_FLAG.[^ipr44] psx-spx numbers the same registers as one block, cop2r0 to cop2r31 for the data registers and cop2r32 to cop2r63 for the control registers.[^spxsum]
+
+Each field is given in Sony's fixed-point notation (sign.integer.fraction), counted in bits, so (1.3.12) is a signed value with 3 integer bits and 12 fraction bits.[^ipr64]
+
+## Control Registers
+
+The control registers are as follows:
+
+Table: GTE control register group
+
+| No. | Name | Access | Content | Format |
+| --- | --- | --- | --- | --- |
+| 0 | R11R12 | R/W | Rotation matrix | (1.3.12) x 2 |
+| 1 | R13R21 | R/W | Rotation matrix | (1.3.12) x 2 |
+| 2 | R22R23 | R/W | Rotation matrix | (1.3.12) x 2 |
+| 3 | R31R32 | R/W | Rotation matrix | (1.3.12) x 2 |
+| 4 | R33 | R/W | Rotation matrix | (1.3.12) |
+| 5 | TRX | R/W | Translation vector (X) | (1.31.0) |
+| 6 | TRY | R/W | Translation vector (Y) | (1.31.0) |
+| 7 | TRZ | R/W | Translation vector (Z) | (1.31.0) |
+| 8 | L11L12 | R/W | Light source direction vector X 3 | (1.3.12) x 2 |
+| 9 | L13L21 | R/W | Light source direction vector X 3 | (1.3.12) x 2 |
+| 10 | L22L23 | R/W | Light source direction vector X 3 | (1.3.12) x 2 |
+| 11 | L31L32 | R/W | Light source direction vector X 3 | (1.3.12) x 2 |
+| 12 | L33 | R/W | Light source direction vector X 3 | (1.3.12) |
+| 13 | RBK | R/W | Peripheral color (background color) (R) | (1.19.12) |
+| 14 | GBK | R/W | Peripheral color (background color) (G) | (1.19.12) |
+| 15 | BBK | R/W | Peripheral color (background color) (B) | (1.19.12) |
+| 16 | LR1LR2 | R/W | Light source color X 3 | (1.3.12) x 2 |
+| 17 | LR3LG1 | R/W | Light source color X 3 | (1.3.12) x 2 |
+| 18 | LG2LG3 | R/W | Light source color X 3 | (1.3.12) x 2 |
+| 19 | LB1LB2 | R/W | Light source color X 3 | (1.3.12) x 2 |
+| 20 | LB3 | R/W | Light source color X 3 | (1.3.12) |
+| 21 | RFC | R/W | Far color (R) | (1.27.4) |
+| 22 | GFC | R/W | Far color (G) | (1.27.4) |
+| 23 | BFC | R/W | Far color (B) | (1.27.4) |
+| 24 | OFX | R/W | Screen offset (X) | (1.15.16) |
+| 25 | OFY | R/W | Screen offset (Y) | (1.15.16) |
+| 26 | H | R/W | Screen position | (0.16.0) |
+| 27 | DQA | R/W | Depth parameter A (coefficient) | (1.7.8) |
+| 28 | DQB | R/W | Depth parameter B (offset) | (1.7.24) |
+| 29 | ZSF3 | R/W | Z-averaging scale factor | (1.3.12) |
+| 30 | ZSF4 | R/W | Z-averaging scale factor | (1.3.12) |
+| 31 | FLAG | R | Flag | See FLAG |
+
+The Content column is from the register table on page 5-3. The Format column is from the register pages that follow it.[^ipr53] [^ipr5c]
+
+### Matrix Registers
+
+The rotation matrix, the light matrix and the light color matrix each have 3 x 3 elements of 16 bits, packed two to a register. Nine elements therefore take five registers: the first element of each pair is in bits 0 to 15 and the second in bits 16 to 31, and the fifth register holds the ninth element in bits 0 to 15 with bits 16 to 31 not used.[^ipr5c]
+
+Table: Matrix element layout
+
+| Register | Bits 0 to 15 | Bits 16 to 31 |
+| --- | --- | --- |
+| R11R12 | R11 | R12 |
+| R13R21 | R13 | R21 |
+| R22R23 | R22 | R23 |
+| R31R32 | R31 | R32 |
+| R33 | R33 | Not used |
+
+The light matrix L uses the same layout. Sony describes it as three light source direction vectors combined into one matrix, with row n holding the X, Y and Z components of light n. The light color matrix combines the colors of the same three lights; its columns are the lights and its rows are the R, G and B components.[^ipr5c] psx-spx reports that reading R33, L33 or LB3 returns the 16-bit element sign-extended to 32 bits.[^spxmat]
+
+### Screen Registers
+
+OFX and OFY are the screen offset in (1.15.16) and H is the screen position in (0.16.0).[^ipr5c] psx-spx calls H the projection plane distance and reports a read bug: a read returns H sign-extended. Values 8000h to FFFFh therefore come back as FFFF8000h to FFFFFFFFh. The bug affects only the register read, and RTPS and RTPT use the correct value.[^spxofs]
+
+DQA (1.7.8) and DQB (1.7.24) are the depth cueing coefficient and offset. RTPS and RTPT compute P = DQB + DQA*(H/SZ) and store the result in IR0 after limiter E.[^ipr5c] [^ipr66] ZSF3 and ZSF4 are the Z-averaging scale factors used by AVSZ3 and AVSZ4. They are normally set to 1/3 and 1/4.[^ipr5c] psx-spx gives typical values of ZSF3 = N/30h and ZSF4 = N/40h for an ordering table of N entries.[^spxavsz]
+
+## Data Registers
+
+The data registers are as follows:
+
+Table: GTE data register group
+
+| No. | Name | Access | Content | Format |
+| --- | --- | --- | --- | --- |
+| 0 | VXY0 | R/W | Vector #0 (X/Y) | (1.15.0) or (1.3.12) x 2 |
+| 1 | VZ0 | R/W | Vector #0 (Z) | (1.15.0) or (1.3.12) |
+| 2 | VXY1 | R/W | Vector #1 (X/Y) | (1.15.0) or (1.3.12) x 2 |
+| 3 | VZ1 | R/W | Vector #1 (Z) | (1.15.0) or (1.3.12) |
+| 4 | VXY2 | R/W | Vector #2 (X/Y) | (1.15.0) or (1.3.12) x 2 |
+| 5 | VZ2 | R/W | Vector #2 (Z) | (1.15.0) or (1.3.12) |
+| 6 | RGB | R/W | Color data + GTE instruction | (0.8.0) x 3 and CODE |
+| 7 | OTZ | R | Z-component average value | (0.15.0) |
+| 8 | IR0 | R/W | Intermediate value #0 | (1.3.12) |
+| 9 | IR1 | R/W | Intermediate value #1 | (1.3.12) or other |
+| 10 | IR2 | R/W | Intermediate value #2 | (1.3.12) or other |
+| 11 | IR3 | R/W | Intermediate value #3 | (1.3.12) or other |
+| 12 | SXY0 | R/W | Calculation result record (XY) | (1.15.0) x 2 |
+| 13 | SXY1 | R/W | Calculation result record (XY) | (1.15.0) x 2 |
+| 14 | SXY2 | R/W | Calculation result record (XY) | (1.15.0) x 2 |
+| 15 | SXYP | W | Calculation result setting register | (1.15.0) x 2 |
+| 16 | SZ0 | R/W | Calculation result record (Z) | (0.16.0) |
+| 17 | SZ1 | R/W | Calculation result record (Z) | (0.16.0) |
+| 18 | SZ2 | R/W | Calculation result record (Z) | (0.16.0) |
+| 19 | SZ3 | R/W | Calculation result record (Z) | (0.16.0) |
+| 20 | RGB0 | R/W | Calculation result record (color data) | (0.8.0) x 3 and CD0 |
+| 21 | RGB1 | R/W | Calculation result record (color data) | (0.8.0) x 3 and CD1 |
+| 22 | RGB2 | R/W | Calculation result record (color data) | (0.8.0) x 3 and CD2 |
+| 23 | RES1 | n/a | Reserved by system (access prohibited) | |
+| 24 | MAC0 | R | Sum of products #0 | (1.31.0) |
+| 25 | MAC1 | R/W | Sum of products #1 | (1.31.0) |
+| 26 | MAC2 | R/W | Sum of products #2 | (1.31.0) |
+| 27 | MAC3 | R/W | Sum of products #3 | (1.31.0) |
+| 28 | IRGB | W | Color data input register | (-.5.-) x 3 |
+| 29 | ORGB | R | Color data output register | (-.5.-) x 3 |
+| 30 | LZCS | W | Leading zero/one count source data | (1.31.0) |
+| 31 | LZCR | R | Leading zero/one count processing result | (0.6.0) |
+
+The Access column is from the register table on page 5-4. The register pages for MAC0 give R/W.[^ipr54] [^ipr5d]
+
+### Vectors
+
+VXY0, VXY1 and VXY2 hold X in bits 0 to 15 and Y in bits 16 to 31, and VZ0, VZ1 and VZ2 hold Z in bits 0 to 15. Each element is (1.15.0) for a coordinate or (1.3.12) for a normal vector.[^ipr5d] psx-spx reports that reading VZn or IRn returns the 16-bit value sign-extended to 32 bits.[^spxvec]
+
+### Color Register
+
+RGB holds R in bits 0 to 7, G in bits 8 to 15, B in bits 16 to 23 and CODE in bits 24 to 31. CODE is arbitrary 8-bit data and is normally specified by the GPU draw command.[^ipr5d] The color commands copy CODE into the color FIFO with each result, so the result is a ready GPU command word.[^spxnotes]
+
+### FIFOs
+
+SXY0 to SXY2 record the last three screen XY results and SZ0 to SZ3 the last four screen Z results. SXY2 and SZ3 are the newest entries. The Z record is one stage deeper because AVSZ4 averages four Z values. RGB0 to RGB2 record the last three color results in the same way, each with R, G, B and a CODE byte CD0 to CD2.[^ipr5d] [^spxfifo]
+
+SXYP exists to load the XY record. A write to SXYP moves SXY1 to SXY0 and SXY2 to SXY1 and then stores the written value in SXY2.[^ipr5d] psx-spx reports that a write to any other SXYn or SZn register changes only that register, and that RES1 can be read and written but has no FIFO function.[^spxfifo]
+
+### Color Conversion
+
+IRGB and ORGB convert between 15-bit color and the intermediate values without a command. A write to IRGB takes IR from bits 0 to 4, IG from bits 5 to 9 and IB from bits 10 to 14, converts each to (1.11.4) format and stores them in IR1, IR2 and IR3.[^ipr544] A read of ORGB converts IR1 to IR3 back to 5-bit values:[^ipr545]
+
+```
+OR = (IR1>>7)&0x1f;
+OG = (IR2>>7)&0x1f;
+OB = (IR3>>7)&0x1f;
+```
+
+psx-spx reports that ORGB saturates instead of masking, so a negative IR value reads as 0 and a value of 1000h or more as 1Fh, and no FLAG bit is set.[^spxorgb] Because these registers work without a command, the CPU is not stalled while the conversion takes place, and a program must wait for the result itself.[^spxadd] psx-spx therefore reports that after a write to IRGB, IR3 is valid after two nops and IR1 and IR2 after three.[^spxirgb]
+
+### Leading Zero Count
+
+A read of LZCR returns the number of leading zeros in LZCS when LZCS is positive and the number of leading ones when LZCS is negative. The count is a 6-bit value in bits 0 to 5.[^ipr547] psx-spx gives the result range as 1 to 32.[^spxlzc]
+
+## FLAG
+
+FLAG (control register 31) records the overflows and out-of-range values of the last calculation in bits 12 to 31; bits 0 to 11 are not used. Bit 31 is the logical sum of bits 30 to 23 and 18 to 13, so a program can test one bit for any of the errors it covers.[^ipr527]
+
+Table: FLAG bits
+
+| Bit | Content |
+| --- | --- |
+| 31 | Logical sum of bits 30 to 23 and bits 18 to 13 |
+| 30 | Calculation test result #1 overflow (2^43 or more) |
+| 29 | Calculation test result #2 overflow (2^43 or more) |
+| 28 | Calculation test result #3 overflow (2^43 or more) |
+| 27 | Calculation test result #1 underflow (less than -2^43) |
+| 26 | Calculation test result #2 underflow (less than -2^43) |
+| 25 | Calculation test result #3 underflow (less than -2^43) |
+| 24 | Limiter A1 out of range |
+| 23 | Limiter A2 out of range |
+| 22 | Limiter A3 out of range |
+| 21 | Limiter B1 out of range (less than 0, or 2^8 or more) |
+| 20 | Limiter B2 out of range (less than 0, or 2^8 or more) |
+| 19 | Limiter B3 out of range (less than 0, or 2^8 or more) |
+| 18 | Limiter C out of range (less than 0, or 2^16 or more) |
+| 17 | Divide overflow (quotient of 2.0 or more) |
+| 16 | Calculation test result #4 overflow (2^31 or more) |
+| 15 | Calculation test result #4 underflow (less than -2^31) |
+| 14 | Limiter D1 out of range (less than -2^10, or 2^10 or more) |
+| 13 | Limiter D2 out of range (less than -2^10, or 2^10 or more) |
+| 12 | Limiter E out of range (less than 0, or 2^12 or more) |
+
+The register table on page 5-3 gives FLAG as read only. The FLAG register page gives R/W.[^ipr53] [^ipr527]
+
+psx-spx reports that bits 12 to 30 can be written by software, although this is not normally needed because every GTE command clears them when it starts. It also reports that writing a 32-bit value to a 16-bit register sets no FLAG bit and does not saturate.[^spxflag]
+
+### Limiters
+
+A limiter clips a value to its lower and upper limits and sets its out-of-bounds bit in FLAG when it clips. The command reference names a limiter by its code in the form limA1S or limC.[^ipr63] [^ipr64]
+
+Table: GTE limiters
+
+| Code | Limiter | FLAG bit | Lower limit | Upper limit |
+| --- | --- | --- | --- | --- |
+| A1S | A1 | 24 | -2^15 | 2^15-1 |
+| A2S | A2 | 23 | -2^15 | 2^15-1 |
+| A3S | A3 | 22 | -2^15 | 2^15-1 |
+| A1U | A1 | 24 | 0 | 2^15-1 |
+| A2U | A2 | 23 | 0 | 2^15-1 |
+| A3U | A3 | 22 | 0 | 2^15-1 |
+| A1C | A1 | 24 | 0 or -2^15 | 2^15-1 |
+| A2C | A2 | 23 | 0 or -2^15 | 2^15-1 |
+| A3C | A3 | 22 | 0 or -2^15 | 2^15-1 |
+| B1 | B1 | 21 | 0 | 2^8-1 |
+| B2 | B2 | 20 | 0 | 2^8-1 |
+| B3 | B3 | 19 | 0 | 2^8-1 |
+| C | C | 18 | 0 | 2^16-1 |
+| D1 | D1 | 14 | -2^10 | 2^10-1 |
+| D2 | D2 | 13 | -2^10 | 2^10-1 |
+| E | E | 12 | 0 | 2^12-1 |
+
+For A1C, A2C and A3C the lm argument of the command selects the lower limit.[^ipr63] The A limiters clip IR1 to IR3, the B limiters the color FIFO components, C the values SZ3 and OTZ, D the screen coordinates SX2 and SY2, and E the value IR0.[^spxflag] The MAC registers themselves are not clipped.[^spxsat]
+
+Overflow and underflow tests are performed only for certain calculations. The [command reference](/hardware/gte/commands/) marks each tested calculation with the number of its test result in angle brackets, and that number selects the FLAG bits it sets.[^ipr63]
+
+## References
+
+[^ipr43]: Sony Computer Entertainment Inc. Inline Programming Reference. November 1998. Page 4-3.
+[^ipr44]: Sony Computer Entertainment Inc. Inline Programming Reference. November 1998. Page 4-4.
+[^ipr53]: Sony Computer Entertainment Inc. Inline Programming Reference. November 1998. Page 5-3.
+[^ipr54]: Sony Computer Entertainment Inc. Inline Programming Reference. November 1998. Page 5-4.
+[^ipr5c]: Sony Computer Entertainment Inc. Inline Programming Reference. November 1998. Pages 5-5 to 5-27, control registers #0 to #30.
+[^ipr5d]: Sony Computer Entertainment Inc. Inline Programming Reference. November 1998. Pages 5-28 to 5-44, data registers #0 to #27.
+[^ipr527]: Sony Computer Entertainment Inc. Inline Programming Reference. November 1998. Page 5-27, control register #31.
+[^ipr544]: Sony Computer Entertainment Inc. Inline Programming Reference. November 1998. Page 5-44, data register #28.
+[^ipr545]: Sony Computer Entertainment Inc. Inline Programming Reference. November 1998. Page 5-45, data register #29.
+[^ipr547]: Sony Computer Entertainment Inc. Inline Programming Reference. November 1998. Pages 5-46 and 5-47, data registers #30 and #31.
+[^ipr63]: Sony Computer Entertainment Inc. Inline Programming Reference. November 1998. Page 6-3.
+[^ipr64]: Sony Computer Entertainment Inc. Inline Programming Reference. November 1998. Page 6-4.
+[^ipr66]: Sony Computer Entertainment Inc. Inline Programming Reference. November 1998. Page 6-6.
+[^spxsum]: psx-spx. Geometry Transformation Engine (GTE), GTE Data Register Summary (cop2r0-31). https://psx-spx.consoledev.net/geometrytransformationenginegte/
+[^spxmat]: psx-spx. Geometry Transformation Engine (GTE), Matrix Registers. https://psx-spx.consoledev.net/geometrytransformationenginegte/
+[^spxofs]: psx-spx. Geometry Transformation Engine (GTE), Screen Offset and Distance. https://psx-spx.consoledev.net/geometrytransformationenginegte/
+[^spxavsz]: psx-spx. Geometry Transformation Engine (GTE), AVSZ3 and AVSZ4. https://psx-spx.consoledev.net/geometrytransformationenginegte/
+[^spxvec]: psx-spx. Geometry Transformation Engine (GTE), 16bit Vectors. https://psx-spx.consoledev.net/geometrytransformationenginegte/
+[^spxfifo]: psx-spx. Geometry Transformation Engine (GTE), Screen XYZ Coordinate FIFOs and Color Register and Color FIFO. https://psx-spx.consoledev.net/geometrytransformationenginegte/
+[^spxnotes]: psx-spx. Geometry Transformation Engine (GTE), GTE Color Calculation Commands, Notes. https://psx-spx.consoledev.net/geometrytransformationenginegte/
+[^spxirgb]: psx-spx. Geometry Transformation Engine (GTE), cop2r28 - IRGB - Color conversion Input. https://psx-spx.consoledev.net/geometrytransformationenginegte/
+[^spxorgb]: psx-spx. Geometry Transformation Engine (GTE), cop2r29 - ORGB - Color conversion Output. https://psx-spx.consoledev.net/geometrytransformationenginegte/
+[^spxlzc]: psx-spx. Geometry Transformation Engine (GTE), cop2r30 - LZCS and cop2r31 - LZCR. https://psx-spx.consoledev.net/geometrytransformationenginegte/
+[^spxflag]: psx-spx. Geometry Transformation Engine (GTE), cop2r63 - FLAG. https://psx-spx.consoledev.net/geometrytransformationenginegte/
+[^spxadd]: psx-spx. Geometry Transformation Engine (GTE), Additional Functions. https://psx-spx.consoledev.net/geometrytransformationenginegte/
+[^spxsat]: psx-spx. Geometry Transformation Engine (GTE), GTE Saturation. https://psx-spx.consoledev.net/geometrytransformationenginegte/