BIOS Logo Race and Uncached Calls: Difference between revisions
| Revision as of 05:40, 23 October 2026 RemmyLee (Hardware tests: 15 more test pages (CPU, DMA, SPU, GPU, MDEC, CD-ROM, bus), each with See also links to the pages that measure the same parts) | Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | ||
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| UCL runs a cached loop of 100 turns that calls a routine of NOPs with JALR. The routine holds 1 NOP in the first rows and then 4 and 8. The routine sits in KSEG1 or in the cache. Root counter 2 times every row, and the program reads it with loads only.[^run] | UCL runs a cached loop of 100 turns that calls a routine of NOPs with JALR. The routine holds 1 NOP in the first rows and then 4 and 8. The routine sits in KSEG1 or in the cache. Root counter 2 times every row, and the program reads it with loads only.[^run] | ||
| + | See also: | ||
| + | |||
| + | - [DMA2 Progress and Cache Line Fills](/tests/dma2-progress-line-fills/) | ||
| + | - [CPU Timing on BIOS DMA2 List Shapes](/tests/dma2-list-shapes/) | ||
| + | |||
| ## Results | ## Results | ||