CPU Bus Gaps and Cache Isolation: Difference between revisions
| Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | Revision as of 05:18, 23 October 2026 RemmyLee (Hardware tests: nine DMA, MDEC and BIOS test pages with part names for titles; join one-sentence paragraphs per voice.md) | ||
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| The program loads a word, a halfword and a byte from addresses in the first 512MB where the [memory map](/hardware/memory-map/) names no device. It covers the region past the 8MB RAM window, expansion 1 with no cartridge, a gap in the I/O ports, expansion 3, the region past the 512KB BIOS ROM, the same RAM-window gap in KSEG1, and KSEG2 away from its cache control port.[^runh] | The program loads a word, a halfword and a byte from addresses in the first 512MB where the [memory map](/hardware/memory-map/) names no device. It covers the region past the 8MB RAM window, expansion 1 with no cartridge, a gap in the I/O ports, expansion 3, the region past the 512KB BIOS ROM, the same RAM-window gap in KSEG1, and KSEG2 away from its cache control port.[^runh] | ||
| − | Each load first fills its target register with 5A5A5A5Ah, so a load that the exception handler skipped leaves that value. The program then repeats each access followed by 16 ADDIU instructions that count by one, to find where the bus error is taken.[^runh] | + | Each load first fills its target register with 5A5A5A5Ah, so a load that the exception handler skipped leaves that value. The program then repeats each access followed by 16 ADDIU instructions that count by one, to find where the bus error is taken.[^runh] A second group sets SR bit 16, which isolates the cache, and reads and writes a RAM word holding 11111111h from uncached code.[^runh] |
| − | A second group sets SR bit 16, which isolates the cache, and reads and writes a RAM word holding 11111111h from uncached code.[^runh] | ||
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| ## Results | ## Results | ||
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| ### Cache Isolation | ### Cache Isolation | ||
| − | With the cache isolated, a load reads the cache and not memory, and a store writes the cache and not memory. An isolated store of 22222222h followed by an isolated load read 22222222h back, while the RAM word still held 11111111h afterwards.[^runh] | + | With the cache isolated, a load reads the cache and not memory, and a store writes the cache and not memory. An isolated store of 22222222h followed by an isolated load read 22222222h back, while the RAM word still held 11111111h afterwards.[^runh] An isolated load before any isolated store returned whatever the cache line held, a value that differed between runs (00002021h, 10400026h, 8FA40254h).[^runs] The same steps run from cached code hung the console, so the program leaves them out.[^runh] |
| − | An isolated load before any isolated store returned whatever the cache line held, a value that differed between runs (00002021h, 10400026h, 8FA40254h).[^runs] | ||
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| − | The same steps run from cached code hung the console, so the program leaves them out.[^runh] | ||
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| ## Runs | ## Runs | ||