CPU Bus Gaps and Cache Isolation: Difference between revisions
| Revision as of 05:40, 23 October 2026 RemmyLee (Hardware tests: 15 more test pages (CPU, DMA, SPU, GPU, MDEC, CD-ROM, bus), each with See also links to the pages that measure the same parts) | Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | ||
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| Each load first fills its target register with 5A5A5A5Ah, so a load that the exception handler skipped leaves that value. The program then repeats each access followed by 16 ADDIU instructions that count by one, to find where the bus error is taken.[^runh] A second group sets SR bit 16, which isolates the cache, and reads and writes a RAM word holding 11111111h from uncached code.[^runh] | Each load first fills its target register with 5A5A5A5Ah, so a load that the exception handler skipped leaves that value. The program then repeats each access followed by 16 ADDIU instructions that count by one, to find where the bus error is taken.[^runh] A second group sets SR bit 16, which isolates the cache, and reads and writes a RAM word holding 11111111h from uncached code.[^runh] | ||
| + | See also: | ||
| + | |||
| + | - [CPU Pipeline Timing and Cache Isolation](/tests/cpu-pipeline-cache-isolation/) | ||
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| ## Results | ## Results | ||