CPU Load and Store Timing: Difference between revisions

Revision as of 05:11, 23 October 2026
RemmyLee
(Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published)

Revision as of 05:49, 23 October 2026
RemmyLee
(Hardware tests: the last 15 test pages (timers, SPU, CPU, GPU, DMA, CD-ROM, GTE), See also links both ways; uncited clock claim removed)

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## Overview

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The program times short loop bodies on the [CPU](/hardware/cpu/) and the [GTE](/hardware/gte/). Every figure is the root counter 2 count in system clock cycles for 100 turns of a loop. Each turn adds the loop's own ADDIU, BNEZ and NOP to the body, so the differences between rows carry the meaning and a difference divided by 100 is cycles per turn.[^runh]

+

The program times short loop bodies on the [CPU](/hardware/cpu/) and the [GTE](/hardware/gte/). Every figure is the root counter 2 count in system clock cycles for 100 turns of a loop. Each turn adds the loop's own ADDIU, BNEZ and NOP to the body, so the differences between rows carry the meaning and a difference divided by 100 is cycles per turn.[^runh] The groups place NOPs after RAM, I/O and BIOS loads, store to devices of each bus width, follow a store with a load elsewhere, run code from KSEG1, time instruction cache fills, write GTE inputs just before or after a command, time each GTE command and read back GTE moves.[^runh]

−

The groups place NOPs after RAM, I/O and BIOS loads, store to devices of each bus width, follow a store with a load elsewhere, run code from KSEG1, time instruction cache fills, write GTE inputs just before or after a command, time each GTE command and read back GTE moves.[^runh]

−

The GTE rows run twice. The first run fetches its code from RAM and the second takes it from the instruction cache. The output lists the two as "cold" and "cached".[^runh]

+

Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published)		Revision as of 05:49, 23 October 2026 RemmyLee (Hardware tests: the last 15 test pages (timers, SPU, CPU, GPU, DMA, CD-ROM, GTE), See also links both ways; uncited clock claim removed)
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	## Overview		## Overview

−	The program times short loop bodies on the [CPU](/hardware/cpu/) and the [GTE](/hardware/gte/). Every figure is the root counter 2 count in system clock cycles for 100 turns of a loop. Each turn adds the loop's own ADDIU, BNEZ and NOP to the body, so the differences between rows carry the meaning and a difference divided by 100 is cycles per turn.[^runh]	+	The program times short loop bodies on the [CPU](/hardware/cpu/) and the [GTE](/hardware/gte/). Every figure is the root counter 2 count in system clock cycles for 100 turns of a loop. Each turn adds the loop's own ADDIU, BNEZ and NOP to the body, so the differences between rows carry the meaning and a difference divided by 100 is cycles per turn.[^runh] The groups place NOPs after RAM, I/O and BIOS loads, store to devices of each bus width, follow a store with a load elsewhere, run code from KSEG1, time instruction cache fills, write GTE inputs just before or after a command, time each GTE command and read back GTE moves.[^runh]

−	The groups place NOPs after RAM, I/O and BIOS loads, store to devices of each bus width, follow a store with a load elsewhere, run code from KSEG1, time instruction cache fills, write GTE inputs just before or after a command, time each GTE command and read back GTE moves.[^runh]
−
	The GTE rows run twice. The first run fetches its code from RAM and the second takes it from the instruction cache. The output lists the two as "cold" and "cached".[^runh]		The GTE rows run twice. The first run fetches its code from RAM and the second takes it from the instruction cache. The output lists the two as "cold" and "cached".[^runh]

		+	See also:
		+
		+	- [CPU Pipeline Timing and Cache Isolation](/tests/cpu-pipeline-cache-isolation/)
		+	- [CPU Loads and BIOS ROM Reads](/tests/cpu-loads-bios-rom-reads/)
		+
	## Results		## Results

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	### Stores to Devices		### Stores to Devices

−	A store wider than a device's bus is split into narrower accesses. One 32-bit store to an SPU voice register took 1463 cycles for 100 turns against 806 for a halfword store, and four took 5963 against 3220. On the 8-bit CD-ROM bus, four halfword stores took 4383 against 4842 for eight byte stores.[^runh]	+	A store wider than a device's bus is split into narrower accesses. One 32-bit store to an SPU voice register took 1463 cycles for 100 turns against 806 for a halfword store, and four took 5963 against 3220. On the 8-bit CD-ROM bus, four halfword stores took 4383 against 4842 for eight byte stores.[^runh] Stores to the timers and to DMA registers cost about the same as stores to RAM: one store a turn took 426 cycles against 455 for RAM.[^runh]

−	Stores to the timers and to DMA registers cost about the same as stores to RAM: one store a turn took 426 cycles against 455 for RAM.[^runh]
−
	A store followed by a load waits when the load goes to RAM. A RAM store then a RAM load took 1465 cycles, and a RAM load then a RAM store took 1276. A store to the scratchpad does not delay a following RAM load, which took 954 cycles as it does alone.[^runh]		A store followed by a load waits when the load goes to RAM. A RAM store then a RAM load took 1465 cycles, and a RAM load then a RAM store took 1276. A store to the scratchpad does not delay a following RAM load, which took 954 cycles as it does alone.[^runh]

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	DPCS issued at once after an MTC2 of RGBC used the old RGBC: MAC1 read 20h, which is the old red value 2 times 16. With one NOP between, it used the new one and read 40h. CC, NCDS and NCS used the new value even at once.[^runh]		DPCS issued at once after an MTC2 of RGBC used the old RGBC: MAC1 read 20h, which is the old red value 2 times 16. With one NOP between, it used the new one and read 40h. CC, NCDS and NCS used the new value even at once.[^runh]

−	A write to an input after the command has started does not reach the command. SQR followed at once by an MTC2 of IR1 or IR3, and RTPS followed by an MTC2 of VZ0, gave results from the old values.[^runh]	+	A write to an input after the command has started does not reach the command. SQR followed at once by an MTC2 of IR1 or IR3, and RTPS followed by an MTC2 of VZ0, gave results from the old values.[^runh] GPF and OP with IR0 or IR3 written at once gave results that differed between the cold and the cached run, so these rows do not settle which value the command read.[^runh]

−	GPF and OP with IR0 or IR3 written at once gave results that differed between the cold and the cached run, so these rows do not settle which value the command read.[^runh]
−
	## Runs		## Runs