CPU Load and Store Timing: Difference between revisions
| Revision as of 05:18, 23 October 2026 RemmyLee (Hardware tests: nine DMA, MDEC and BIOS test pages with part names for titles; join one-sentence paragraphs per voice.md) | Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | ||
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| The GTE rows run twice. The first run fetches its code from RAM and the second takes it from the instruction cache. The output lists the two as "cold" and "cached".[^runh] | The GTE rows run twice. The first run fetches its code from RAM and the second takes it from the instruction cache. The output lists the two as "cold" and "cached".[^runh] | ||
| + | See also: | ||
| + | |||
| + | - [CPU Pipeline Timing and Cache Isolation](/tests/cpu-pipeline-cache-isolation/) | ||
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| ## Results | ## Results | ||