DMA Chopping: Difference between revisions
| Revision as of 05:18, 23 October 2026 RemmyLee (Hardware tests: nine DMA, MDEC and BIOS test pages with part names for titles; join one-sentence paragraphs per voice.md) | Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | ||
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| The program sends 8192 bytes of random data to VRAM through [DMA](/hardware/dma/) channel 2 after a GP0(A0h) copy command, and times each transfer in CPU cycles from the CHCR write until the channel goes idle. It first uses sync mode 1 with block sizes from 1 to 64 words and 128 words. It then uses sync mode 0 without chopping. Last it uses sync mode 0 with chopping at every pair of DMA window (1 to 128 words) and CPU window (1 to 128 clocks).[^src] After each transfer the program reads GPUSTAT bit 26 and prints "(GPU busy)" when the GPU was not yet ready for a command.[^src] | The program sends 8192 bytes of random data to VRAM through [DMA](/hardware/dma/) channel 2 after a GP0(A0h) copy command, and times each transfer in CPU cycles from the CHCR write until the channel goes idle. It first uses sync mode 1 with block sizes from 1 to 64 words and 128 words. It then uses sync mode 0 without chopping. Last it uses sync mode 0 with chopping at every pair of DMA window (1 to 128 words) and CPU window (1 to 128 clocks).[^src] After each transfer the program reads GPUSTAT bit 26 and prints "(GPU busy)" when the GPU was not yet ready for a command.[^src] | ||
| + | See also: | ||
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| + | - [Peripheral Registers and Bus Delays](/tests/peripheral-bus-delays/) | ||
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| ## Results | ## Results | ||