DMA Interrupt Latency and MDEC Reset: Difference between revisions
| Revision as of 05:18, 23 October 2026 RemmyLee (Hardware tests: nine DMA, MDEC and BIOS test pages with part names for titles; join one-sentence paragraphs per voice.md) | Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | ||
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| | SDS | DMA4 to the SPU by block size, and in sync mode 0 | | | SDS | DMA4 to the SPU by block size, and in sync mode 0 | | ||
| + | See also: | ||
| + | |||
| + | - [Undrained SPU Write FIFO](/tests/spu-write-fifo-undrained/) | ||
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| ## Results | ## Results | ||