DMA Priority Against the CPU and Between Channels: Difference between revisions
| Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | Revision as of 05:49, 23 October 2026 RemmyLee (Hardware tests: the last 15 test pages (timers, SPU, CPU, GPU, DMA, CD-ROM, GTE), See also links both ways; uncited clock claim removed) | ||
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| Part 2 programs DMA2 and DMA6 with their master enables clear and starts both with one DPCR write. DMA2 reads a filled VRAM rectangle into a RAM buffer in ascending order, and DMA6 writes the OT clear pattern into the same buffer in descending order. The last writer of each word shows the order. Part 3 starts DMA6 and reads the counter after 0 to 12 NOPs. It takes eight samples of each, and the first sample runs from a cold instruction cache. Rows of parts 1 and 2 run twice and are marked UNSTABLE when the two runs differ.[^src] | Part 2 programs DMA2 and DMA6 with their master enables clear and starts both with one DPCR write. DMA2 reads a filled VRAM rectangle into a RAM buffer in ascending order, and DMA6 writes the OT clear pattern into the same buffer in descending order. The last writer of each word shows the order. Part 3 starts DMA6 and reads the counter after 0 to 12 NOPs. It takes eight samples of each, and the first sample runs from a cold instruction cache. Rows of parts 1 and 2 run twice and are marked UNSTABLE when the two runs differ.[^src] | ||
| + | See also: | ||
| + | |||
| + | - [DMA Start Stall and Delay Slot Fetch](/tests/dma-start-stall-delay-slot/) | ||
| + | |||
| ## Results | ## Results | ||