DMA Start Stall and Delay Slot Fetch: Difference between revisions

Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones)	Revision as of 05:49, 23 October 2026 RemmyLee (Hardware tests: the last 15 test pages (timers, SPU, CPU, GPU, DMA, CD-ROM, GTE), See also links both ways; uncited clock claim removed)
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	+	---
	+	title: DMA Start Stall and Delay Slot Fetch
	+	type: test
	+	summary: Measures when the CPU waits for an OTC transfer started by a CHCR store, and the time of a call whose delay slot begins a new cache line.
	+	category: Hardware tests
	+	info: Machine = SCPH-5501
	+	info: Program = followup35
	+	---
	+
	+	## Overview
	+
	+	The program runs two groups.[^run] DSK stores to the CHCR of DMA6 to start an OTC transfer of 1, 4 or 16 words and reads timer 2 k NOPs later. Each entry gives the cycles from the store to the read with the channel enabled in DPCR and then with it disabled, and each row runs three times.[^dsk] FSL zeroes timer 2 in KSEG1 code, makes a call by jalr and reads the timer after the return. The jalr sits at word 3 of a line, so that its delay slot begins the next line, or at word 0, and the target is cached or in KSEG1.[^fsl]
	+
	+	See also:
	+
	+	- [DMA Priority Against the CPU and Between Channels](/tests/dma-priority/)
	+
	+	## Results
	+
	+	### OTC Start Stall
	+
	+	With the channel disabled the read came k + 1 cycles after the store from k 1 on. With the channel enabled and 0 to 3 NOPs, the read came at the same time as with it disabled. With 4 or more NOPs the read waited for the transfer. The wait ended at 11 cycles for 1 word and at 14 cycles for 4 words. For 16 words it ended at 26 cycles. Once the NOPs took longer than that, the enabled and the disabled times were the same again.[^dsk]
	+
	+	Table: Cycles from the CHCR store to the timer read with the channel enabled / disabled in the third run
	+
	+	\| k \| 1 word \| 4 words \| 16 words \|
	+	\| --- \| --- \| --- \| --- \|
	+	\| 0 \| 2 / 2 \| 2 / 2 \| 2 / 2 \|
	+	\| 1 \| 2 / 2 \| 2 / 2 \| 2 / 2 \|
	+	\| 2 \| 3 / 3 \| 3 / 3 \| 3 / 3 \|
	+	\| 3 \| 4 / 4 \| 4 / 4 \| 4 / 4 \|
	+	\| 4 \| 11 / 5 \| 14 / 5 \| 26 / 5 \|
	+	\| 8 \| 11 / 9 \| 14 / 9 \| 26 / 9 \|
	+	\| 16 \| 17 / 17 \| 17 / 17 \| 26 / 17 \|
	+	\| 32 \| 33 / 33 \| 33 / 33 \| 33 / 33 \|
	+
	+	The first run of the 1-word transfer took longer with the channel enabled: 7 cycles at k 0 and 1, 22 at k 3 to 8, 44 at k 16 and 84 at k 32. The 16-word transfer took 29 and 36 cycles in one run each.[^dsk]
	+
	+	### Delay Slot at a Line Start
	+
	+	With a cached target, the call took 25 cycles cold when the jalr was at word 3 and 26 cycles when it was at word 0, and 11 cycles warm in both places. With a target in KSEG1 it took 30 and 31 cycles cold and 16 cycles warm.[^fsl]
	+
	+	## Runs
	+
	+	### 8 October 2026
	+
	+	[followup35/00RUN.txt](/tests/raw/20261008T0000Z-5501a-card-followup35/followup35/00RUN.txt)
	+
	+	```
	+	===== 00 RUN \| BIOS 19951204 System ROM Version 3.0 11/18/96 A
	+	2 tests
	+	Saved on the card in slot 2, from image 1
	+	COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02B68 DCIC 00000000 BadVaddr 00000480 BDAM 00000000
	+	BPCM 00000000 SR 00000000 Cause C0000024 EPC BFC02B78 PRId 00000002
	+	```
	+
	+	[followup35/01DSK.txt](/tests/raw/20261008T0000Z-5501a-card-followup35/followup35/01DSK.txt)
	+
	+	```
	+	===== 01 DSK F35 DMA STOP \| BIOS 19951204 System ROM Version 3.0 11/18/96 A
	+	BadVaddr as the group starts: 00000480
	+	Clocks from a CHCR store to a timer read k NOPs on, OTC, the channel enabled / disabled
	+	in DPCR, three times each (row 240):
	+	OTC 1 words, k 0: 7/2 2/2 2/2
	+	OTC 1 words, k 1: 7/2 2/2 2/2
	+	OTC 1 words, k 2: 7/3 3/3 3/3
	+	OTC 1 words, k 3: 22/4 4/4 4/4
	+	OTC 1 words, k 4: 22/5 11/5 11/5
	+	OTC 1 words, k 8: 22/9 11/9 11/9
	+	OTC 1 words, k 16: 44/17 17/17 17/17
	+	OTC 1 words, k 32: 84/33 33/33 33/33
	+	OTC 4 words, k 0: 2/2 2/2 2/2
	+	OTC 4 words, k 1: 2/2 2/2 2/2
	+	OTC 4 words, k 2: 3/3 3/3 3/3
	+	OTC 4 words, k 3: 4/4 4/4 4/4
	+	OTC 4 words, k 4: 14/5 14/5 14/5
	+	OTC 4 words, k 8: 14/9 14/9 14/9
	+	OTC 4 words, k 16: 17/17 17/17 17/17
	+	OTC 4 words, k 32: 33/33 33/33 33/33
	+	OTC 16 words, k 0: 2/2 2/2 2/2
	+	OTC 16 words, k 1: 2/2 2/2 2/2
	+	OTC 16 words, k 2: 3/3 3/3 3/3
	+	OTC 16 words, k 3: 4/4 4/4 4/4
	+	OTC 16 words, k 4: 26/5 29/5 26/5
	+	OTC 16 words, k 8: 36/9 26/9 26/9
	+	OTC 16 words, k 16: 26/17 26/17 26/17
	+	OTC 16 words, k 32: 33/33 33/33 33/33
	+	Done.
	+	```
	+
	+	[followup35/02FSL.txt](/tests/raw/20261008T0000Z-5501a-card-followup35/followup35/02FSL.txt)
	+
	+	```
	+	===== 02 FSL F35 FILL SLOT \| BIOS 19951204 System ROM Version 3.0 11/18/96 A
	+	BadVaddr as the group starts: 00000480
	+	Timer 2 from its zeroing in a KSEG1 shell to lhu of it after a call and its return,
	+	cold (FlushCache first) three times, then warm (row 241):
	+	jalr at word 3, slot begins a line, target cached: cold 25 25 25, warm 11
	+	jalr at word 3, slot begins a line, target KSEG1: cold 30 30 30, warm 16
	+	jalr at word 0, slot word 1, target cached: cold 26 26 26, warm 11
	+	jalr at word 0, slot word 1, target KSEG1: cold 31 31 31, warm 16
	+	Done.
	+	```
	+
	+	## References
	+
	+	[^run]: SCPH-5501 output: [followup35/00RUN.txt](/tests/raw/20261008T0000Z-5501a-card-followup35/followup35/00RUN.txt)
	+	[^dsk]: SCPH-5501 output: [followup35/01DSK.txt](/tests/raw/20261008T0000Z-5501a-card-followup35/followup35/01DSK.txt)
	+	[^fsl]: SCPH-5501 output: [followup35/02FSL.txt](/tests/raw/20261008T0000Z-5501a-card-followup35/followup35/02FSL.txt)

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