Instruction Fetch During DMA2: Difference between revisions
| Revision as of 05:40, 23 October 2026 RemmyLee (Hardware tests: 15 more test pages (CPU, DMA, SPU, GPU, MDEC, CD-ROM, bus), each with See also links to the pages that measure the same parts) | Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | ||
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| The program has two groups. LFE times code that misses the instruction cache on every line, the same code run from KSEG1, a cached block that hits, and byte stores. Each runs alone and straight after a DMA2 list starts, and then in a race in which the CPU runs cache-missing code before it stores a pointer into the list. TBT reads the MDEC status and root counter 2 back to back after the last word of a quantization or scale table.[^run] | The program has two groups. LFE times code that misses the instruction cache on every line, the same code run from KSEG1, a cached block that hits, and byte stores. Each runs alone and straight after a DMA2 list starts, and then in a race in which the CPU runs cache-missing code before it stores a pointer into the list. TBT reads the MDEC status and root counter 2 back to back after the last word of a quantization or scale table.[^run] | ||
| + | See also: | ||
| + | |||
| + | - [CPU Timing on BIOS DMA2 List Shapes](/tests/dma2-list-shapes/) | ||
| + | |||
| ## Results | ## Results | ||