Load and Use During a DMA2 List: Difference between revisions
| Revision as of 05:18, 23 October 2026 RemmyLee (Hardware tests: nine DMA, MDEC and BIOS test pages with part names for titles; join one-sentence paragraphs per voice.md) | Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | ||
| Line 22: | Line 22: | ||
| | ALN | Alone only: an I_STAT load then a RAM load, and a store, NOPs and a load | | | ALN | Alone only: an I_STAT load then a RAM load, and a store, NOPs and a load | | ||
| + | See also: | ||
| + | |||
| + | - [CPU Stores and Device Delays](/tests/cpu-stores-device-delays/) | ||
| + | - [DMA2 Progress and Cache Line Fills](/tests/dma2-progress-line-fills/) | ||
| + | - [CPU Timing on BIOS DMA2 List Shapes](/tests/dma2-list-shapes/) | ||
| + | |||
| ## Results | ## Results | ||