RAM Access During a DMA2 List: Difference between revisions
| Revision as of 05:18, 23 October 2026 RemmyLee (Hardware tests: nine DMA, MDEC and BIOS test pages with part names for titles; join one-sentence paragraphs per voice.md) | Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | ||
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| | LSS | A RAM load, k NOPs, and a halfword store to a word in another cache line | | | LSS | A RAM load, k NOPs, and a halfword store to a word in another cache line | | ||
| + | See also: | ||
| + | |||
| + | - [CPU Stores and Device Delays](/tests/cpu-stores-device-delays/) | ||
| + | - [CPU Timing on BIOS DMA2 List Shapes](/tests/dma2-list-shapes/) | ||
| + | - [SPU Loads and Cold Calls During a DMA2 List](/tests/dma2-spu-loads-cold-calls/) | ||
| + | |||
| ## Results | ## Results | ||