GTE LZCS Write Delay: Difference between revisions
| Revision as of 04:48, 23 October 2026 RemmyLee (Main page: drop the Hardware Tests lede) | Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | ||
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| + | --- | ||
| + | title: GTE LZCS Write Delay | ||
| + | type: test | ||
| + | summary: Measures how soon LZCR shows the leading-bit count after a write to LZCS. | ||
| + | category: Hardware tests | ||
| + | info: Machine = SCPH-5501 | ||
| + | info: Program = gte-latency-lzcs (pcsx-redux nugget) | ||
| + | --- | ||
| + | |||
| + | ## Overview | ||
| + | |||
| + | Writing the [GTE](/hardware/gte/) register LZCS (register 30) makes the GTE count its leading bits into LZCR (register 31). The program writes a value whose count is 31, waits 24 NOPs, writes a new value, runs N NOPs with N from 0 to 8 and reads LZCR with MFC2. The smallest N that reads the new count is the delay.[^src] | ||
| + | |||
| + | The new values sweep every leading-bit count as a dense and a sparse pattern. There are 126 values in all. The sweep runs once from cached memory (KSEG0) and once from uncached memory (KSEG1). Further arms put one other instruction between the write and the read: a load from I_STAT, a multiply or divide read back with MFLO, and a lone MULT.[^src] | ||
| + | |||
| + | ## Results | ||
| + | |||
| + | From cached memory LZCR showed the new count after 2 NOPs for all 126 values, and with 0 or 1 NOP it still showed 31. From uncached memory it showed the new count after 1 NOP.[^run] | ||
| + | |||
| + | The delay was the same for every value. A value with one leading zero and a value with 15 leading zeros both needed 2 NOPs, so the count does not take longer for more leading bits.[^run] | ||
| + | |||
| + | A single instruction that stalls covers the delay. With one load from I_STAT, or a multiply or divide followed by MFLO, between the write and the read, all 126 reads returned the new count from both cached and uncached memory.[^run] | ||
| + | |||
| + | A lone MULT, which nothing waits for, did not cover it in cached code: all 126 reads returned the old count 31. The same MULT in uncached code returned the new count every time.[^run] | ||
| + | |||
| + | ## Runs | ||
| + | |||
| + | ### 22 October 2026 | ||
| + | |||
| + | [gtelatencylzcs/GTELATENCYLZCS.txt](/tests/raw/20261022T2233Z-5501a-link-2/gtelatencylzcs/GTELATENCYLZCS.txt) | ||
| + | |||
| + | [gtelatencylzcs/bench.txt](/tests/raw/20261022T2233Z-5501a-link-2/gtelatencylzcs/bench.txt) | ||
| + | |||
| + | ``` | ||
| + | 30994 bytes of TTY text in psx.log | ||
| + | ``` | ||
| + | |||
| + | [gtelatencylzcs/when.txt](/tests/raw/20261022T2233Z-5501a-link-2/gtelatencylzcs/when.txt) | ||
| + | |||
| + | ``` | ||
| + | 20261022T2233Z | ||
| + | ``` | ||
| + | |||
| + | ## References | ||
| + | |||
| + | [^src]: pcsx-redux nugget, tests/gte-latency-lzcs/gte-latency-lzcs.c, header comment and arm definitions. MIT License. https://github.com/pcsx-redux/nugget | ||
| + | [^run]: Hardware test run 20261022T2233Z-5501a-link-2 on the SCPH-5501: [GTELATENCYLZCS.txt](/tests/raw/20261022T2233Z-5501a-link-2/gtelatencylzcs/GTELATENCYLZCS.txt). | ||