Interrupt Controller and Serial Ports: Difference between revisions
| Revision as of 04:48, 23 October 2026 RemmyLee (Main page: drop the Hardware Tests lede) | Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | ||
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| + | --- | ||
| + | title: Interrupt Controller and Serial Ports | ||
| + | type: test | ||
| + | summary: Measures I_STAT and I_MASK, interrupt edges and latency, the SIO0 and SIO1 registers, byte timing and the pad protocol. | ||
| + | category: Hardware tests | ||
| + | info: Machine = SCPH-5501 | ||
| + | info: Program = irqsio | ||
| + | --- | ||
| + | |||
| + | ## Overview | ||
| + | |||
| + | The program tests the [interrupt controller](/hardware/interrupts/) and the two [serial ports](/hardware/sio/). It writes I_MASK and I_STAT at every width, raises interrupts from the GPU, the DMA controller and the root counters, and measures when CAUSE.IP2 and the exception follow. It then reads and writes every SIO0 and SIO1 register, times a byte through each port, and talks to the [controller](/hardware/controller/) in slot 1.[^run] | ||
| + | |||
| + | Every group runs with SR.IEc cleared by MTC0 and puts back SR, I_MASK and the root counters at the end. JOY_CTRL bit 13 (slot 2) is never written as 1. Times are counted on root counter 2 in system clock cycles from the write that starts the event. The handler group runs last because it can hang the console.[^run] | ||
| + | |||
| + | ## Results | ||
| + | |||
| + | ### I_MASK | ||
| + | |||
| + | I_MASK keeps bits 0 to 10. A word read returned 960507FFh after FFFFFFFFh was written, so the upper half reads a value left on the bus.[^h-imr] | ||
| + | |||
| + | A store of any width at offset +0 writes the whole source register, masked to 11 bits: a byte store of AABBCCDDh at +0 gave 4DDh. A byte store at +1 writes the source's low byte shifted left by 8 bits, so AABBCCDDh gave 500h. Stores at +2 and +3 write 0.[^h-imr] | ||
| + | |||
| + | ### I_STAT | ||
| + | |||
| + | GP0(1Fh), the DICR force bit and the three root counters raised I_STAT to 007Ah. Writing 0 to a bit acknowledges it, writing 1 leaves it, and no write sets a bit. A byte store at +1, +2 or +3 or a halfword store at +2 cleared every bit, because the low lanes receive 0.[^h-ist] | ||
| + | |||
| + | ### Edges | ||
| + | |||
| + | Each I_STAT bit is set by a rising edge of its source. With DICR bit 15 still set, I_STAT bit 3 stayed 0 after it was acknowledged, and it was set again only after the force bit was cleared and set. The GPU interrupt behaves the same way: a second GP0(1Fh) with GPUSTAT bit 24 still set raised nothing until GP1(02h) cleared it.[^h-ied] | ||
| + | |||
| + | Root counter 0 at target 99 in repeat mode set I_STAT bit 4 990 times in 100000 cycles in pulse mode and 495 times in toggle mode.[^h-ied] | ||
| + | |||
| + | ### CAUSE.IP2 | ||
| + | |||
| + | CAUSE.IP2 is set while I_STAT AND I_MASK is not zero, whatever the SR interrupt mask holds. MTC0 of FFFFFFFFh to CAUSE leaves 00000300h: only IP0 and IP1 can be written.[^h-ip2] | ||
| + | |||
| + | Table: Instructions before CAUSE.IP2 follows a write | ||
| + | |||
| + | | Write | IP2 changes after | | ||
| + | | --- | --- | | ||
| + | | sh I_MASK = 8 with I_STAT bit 3 set | 2 NOPs | | ||
| + | | sw I_STAT = 0 (acknowledge) | 2 NOPs | | ||
| + | | sw DICR force bit, I_MASK = 8 | 4 NOPs | | ||
| + | |||
| + | The DICR flag and I_STAT bit 3 are set at the same poll as CHCR bit 24 clearing after an OTC. Root counter 1 reset at vblank read 57856 to 57869 system clock cycles at each vblank interrupt, and 263 hblanks passed between two vblank interrupts.[^h-ilt] | ||
| + | |||
| + | ### Exception Entry | ||
| + | |||
| + | The program installs its own handler at 80000080h and counts the instructions executed between the trigger and the exception.[^run] | ||
| + | |||
| + | Table: Instructions executed after the trigger | ||
| + | |||
| + | | Trigger | Instructions | Cycles on root counter 2 | | ||
| + | | --- | --- | --- | | ||
| + | | MTC0 SR IEc 0 to 1 with an IRQ pending | 2 | 54 to 68 | | ||
| + | | sw DICR force bit, I_MASK 8 | 8 | 59 to 63 | | ||
| + | |||
| + | When root counter 2 interrupted a loop of 3 instructions, CAUSE.BD was set in 5 of 16 cases.[^h-iex] | ||
| + | |||
| + | ### SIO0 Registers | ||
| + | |||
| + | JOY_MODE keeps bits 0 to 5 and 8 (013Fh), JOY_BAUD keeps 16 bits, and JOY_CTRL keeps bits 0 to 3, 5 and 8 to 12. CTRL bit 6 resets the port: MODE, BAUD and CTRL read 0 and STAT 00000005h. A read of the empty receive buffer returned 47h in every byte lane.[^h-jrg] | ||
| + | |||
| + | CTRL bit 10 (TX IRQ) and bit 11 (RX IRQ) set STAT bit 9 and I_STAT bit 7 at once when their condition is already true.[^h-jrg] | ||
| + | |||
| + | ### Baud Timer | ||
| + | |||
| + | JOY_STAT bits 11 to 31 hold the baud timer. After a BAUD write the timer starts at BAUD times the factor divided by 2 and counts down. MODE factor 0 behaves as factor 1.[^h-jbd] | ||
| + | |||
| + | Table: Baud timer start value for BAUD 0088h | ||
| + | |||
| + | | MODE bits 0 and 1 | Factor | Start value | | ||
| + | | --- | --- | --- | | ||
| + | | 0 | 1 | 44h | | ||
| + | | 1 | 1 | 44h | | ||
| + | | 2 | 16 | 440h | | ||
| + | | 3 | 64 | 1100h | | ||
| + | |||
| + | SIO1 has the same timer in SIO_STAT bits 11 to 25.[^h-jbd] | ||
| + | |||
| + | ### Byte Time on SIO0 | ||
| + | |||
| + | The time from the JOY_DATA write to STAT bit 2 (transfer finished) depends on BAUD and the character length.[^h-jtx] | ||
| + | |||
| + | Table: Byte time on SIO0 with nothing selected | ||
| + | |||
| + | | MODE | BAUD | STAT bit 2 set at | | ||
| + | | --- | --- | --- | | ||
| + | | 000Dh, 8 bits | 0022h | 312 to 347 | | ||
| + | | 000Dh, 8 bits | 0044h | 610 to 627 | | ||
| + | | 000Dh, 8 bits | 0088h | 1194 to 1226 | | ||
| + | | 000Dh, 8 bits | 0089h | 1232 to 1274 | | ||
| + | | 000Dh, 8 bits | 0110h | 2348 to 2588 | | ||
| + | | 000Eh, 8 bits, factor 16 | 0088h | 19167 to 19204 | | ||
| + | | 0001h, 5 bits | 0088h | 805 to 850 | | ||
| + | |||
| + | With RXEN set the received byte is FFh. STAT bit 1 (receive buffer not empty) was set about 300 cycles before bit 2.[^h-jtx] | ||
| + | |||
| + | ### Controller | ||
| + | |||
| + | The pad in slot 1 answered 01h 42h with FFh 41h 5Ah FFh FFh and pulled /ACK low after each of the first four bytes. /ACK fell 1613 to 1755 cycles after each JOY_DATA write and stayed low for 90 to 152 cycles. An acknowledge written while /ACK was low did not clear STAT bit 9. A second acknowledge after /ACK went high cleared it.[^h-jpd] | ||
| + | |||
| + | After command 43h with 01h, which was answered FFh 41h 5Ah 01h, the pad still gave ID 41h. Commands 45h, 46h, 47h, 4Ch and 48h were acknowledged only after their first byte.[^h-jcf] | ||
| + | |||
| + | ### SIO1 | ||
| + | |||
| + | SIO1 read STAT 00000185h and MISC DFFDh as found. SIO_MODE keeps 8 bits. A byte written with TXEN set and no device on the port finished in 1464 to 1593 cycles. No byte was received.[^h-srg][^h-stx] | ||
| + | |||
| + | ## Runs | ||
| + | |||
| + | ### 27 September 2026 card-b | ||
| + | |||
| + | Raw output: [00RUN.txt](/tests/raw/20260927T0000Z-5501a-card-b/irqsio/00RUN.txt) · [01IMR.txt](/tests/raw/20260927T0000Z-5501a-card-b/irqsio/01IMR.txt) · [02IST.txt](/tests/raw/20260927T0000Z-5501a-card-b/irqsio/02IST.txt) · [03IED.txt](/tests/raw/20260927T0000Z-5501a-card-b/irqsio/03IED.txt) · [04IP2.txt](/tests/raw/20260927T0000Z-5501a-card-b/irqsio/04IP2.txt) · [05ILT.txt](/tests/raw/20260927T0000Z-5501a-card-b/irqsio/05ILT.txt) · [06JRG.txt](/tests/raw/20260927T0000Z-5501a-card-b/irqsio/06JRG.txt) · [07JBD.txt](/tests/raw/20260927T0000Z-5501a-card-b/irqsio/07JBD.txt) · [08JTX.txt](/tests/raw/20260927T0000Z-5501a-card-b/irqsio/08JTX.txt) · [09JFF.txt](/tests/raw/20260927T0000Z-5501a-card-b/irqsio/09JFF.txt) · [10SRG.txt](/tests/raw/20260927T0000Z-5501a-card-b/irqsio/10SRG.txt) · [11STX.txt](/tests/raw/20260927T0000Z-5501a-card-b/irqsio/11STX.txt) · [12JPD.txt](/tests/raw/20260927T0000Z-5501a-card-b/irqsio/12JPD.txt) · [13JCF.txt](/tests/raw/20260927T0000Z-5501a-card-b/irqsio/13JCF.txt) · [14IEX.txt](/tests/raw/20260927T0000Z-5501a-card-b/irqsio/14IEX.txt) | ||
| + | |||
| + | 00RUN.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | 14 tests | ||
| + | A chain program, linked at 80010000 | ||
| + | Saved on the card in slot 2, from image 1 | ||
| + | COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 00000480 BDAM 00000000 | ||
| + | BPCM 00000000 SR 40000000 Cause 00000020 EPC 80110540 PRId 00000002 | ||
| + | ``` | ||
| + | |||
| + | 01IMR.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 01 IMR I MASK READBACK | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | I_MASK as found: 0009 | ||
| + | sw FFFFFFFF, then lw 960507FF | ||
| + | sw FFFFFFFF, then lhu +0 07FF, lhu +2 3C03 | ||
| + | sw FFFFFFFF, then lbu +0..+3 FF 07 C6 30 | ||
| + | sw 0000F800 (bits 11-15), then lhu 0000 | ||
| + | sw 12345555, then lhu 0555 | ||
| + | sw 0, then lw 24840000 | ||
| + | Partial stores: baseline, source, op, then the low half read back | ||
| + | base 000 src AABBCCDD: sb+0=4DD sb+1=500 sb+2=000 sb+3=000 sh+0=4DD sh+2=000 sw=4DD | ||
| + | base 000 src FEDCBA98: sb+0=298 sb+1=000 sb+2=000 sb+3=000 sh+0=298 sh+2=000 sw=298 | ||
| + | base 7FF src AABBCCDD: sb+0=4DD sb+1=500 sb+2=000 sb+3=000 sh+0=4DD sh+2=000 sw=4DD | ||
| + | base 7FF src FEDCBA98: sb+0=298 sb+1=000 sb+2=000 sb+3=000 sh+0=298 sh+2=000 sw=298 | ||
| + | sw 2A5 then lw at once: 000002A5 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 02IST.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 02 IST I STAT ACK | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Raised by GP0 1Fh, DICR force, timers 0-2: I_STAT 007A (lw 3C03007A) | ||
| + | lhu +2 9067, lbu +0..+3 7A 00 A2 AF | ||
| + | sw FFFFFFFF: 007A | ||
| + | sw ~10h (ack timer 0): 006A | ||
| + | sw 0: 0000 | ||
| + | sw FFFFFFFF after 0 (can a write set a bit?): 0000 | ||
| + | With I_MASK 07FF: I_STAT 007A, I_MASK 07FF | ||
| + | Partial stores after raise_all: op=result (bits 0 and 2 may come and go) | ||
| + | src 00000000: sb+0=07A/000 sb+1=07A/000 sb+2=07A/000 sb+3=07A/000 sh+0=07A/000 sh+2=07A/000 sw=07A/000 | ||
| + | src FFFFFFFF: sb+0=07A/07A sb+1=07A/000 sb+2=07A/000 sb+3=07A/000 sh+0=07A/07A sh+2=07A/000 sw=07A/07A | ||
| + | src FFFFFFEF: sb+0=07A/06A sb+1=07A/000 sb+2=07A/000 sb+3=07A/000 sh+0=07A/06A sh+2=07A/000 sw=07A/06A | ||
| + | src 000000FF: sb+0=07A/07A sb+1=07A/000 sb+2=07A/000 sb+3=07A/000 sh+0=07A/07A sh+2=07A/000 sw=07A/07A | ||
| + | sb+1 src 000000FB: before 07A after 000 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 03IED.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 03 IED I STAT EDGES | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | DICR force on: I_STAT.3 1, DICR 80008000 | ||
| + | Ack I_STAT.3 with force still on: 0 | ||
| + | Force written 1 again: 0 | ||
| + | Force off: 0 | ||
| + | Force on again: 1 | ||
| + | GP0 1Fh: I_STAT.1 1 GPUSTAT.24 1 | ||
| + | Ack I_STAT.1, GP0 1Fh again with GPUSTAT.24 set: I_STAT.1 0 | ||
| + | GP1 02h: GPUSTAT.24 0, I_STAT.1 0 | ||
| + | GP0 1Fh after GP1 02h: I_STAT.1 1 | ||
| + | Timer 0 target 99 repeat pulse: I_STAT.4 set 990 times in 100000 cycles | ||
| + | Timer 0 target 99 repeat toggle: I_STAT.4 set 495 times in 100000 cycles | ||
| + | Toggle mode, bit 10 of 16 mode reads: 0 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1 | ||
| + | Pulse mode, bit 10 of 16 mode reads: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| + | One-shot target 99, after acking the first: I_STAT.4 0, mode 0C18 | ||
| + | One-shot, target and FFFFh on, counter FFF0h: I_STAT.4 1 mode 1C30 | ||
| + | ... then 120000 cycles on (past target 30000): I_STAT.4 0 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 04IP2.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 04 IP2 CAUSE IP2 | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | SR 40000400 CAUSE 00000000 with interrupts off here | ||
| + | I_STAT.3 set, I_MASK 0: CAUSE 00000000 | ||
| + | I_MASK 8: CAUSE 00000400 | ||
| + | SR Im all 0 (SR 40000000): CAUSE 00000400 | ||
| + | I_MASK 0 again: CAUSE 00000000 | ||
| + | mtc0 CAUSE FFFFFFFF: 00000300; then 0: 00000000 | ||
| + | mtc0 CAUSE 00000400 with no IRQ: 00000000 | ||
| + | IP2 after sh I_MASK=8 (I_STAT.3 set), n nops: 0:0 1:0 2:1 3:1 4:1 6:1 | ||
| + | IP2 after sh I_MASK=8 (I_STAT.3 set), n nops: 0:0 1:0 2:1 3:1 4:1 6:1 | ||
| + | IP2 after sw I_STAT=0 (was set, I_MASK 8), n nops: 0:1 1:1 2:0 3:0 4:0 6:0 | ||
| + | IP2 after sw DICR force (I_MASK 8), n nops: 0:0 1:0 2:0 3:0 4:1 6:1 | ||
| + | I_STAT.3 after all that, acked: 0; CAUSE 00000000 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 05ILT.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 05 ILT IRQ LATENCY POLLED | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Poll loop period, 1000 turns: 15020 cycles | ||
| + | Counter at the turn that saw the IRQ, minus the target (targets 300-307): | ||
| + | T2 sysclk, I_STAT.6: 11 5 4 3 2 1 15 14 | ||
| + | T2 sysclk, CAUSE.IP2: 4 12 11 10 9 8 7 6 | ||
| + | T2 sysclk/8, I_STAT.6 (in 8s): 1 1 1 0 1 1 0 0 | ||
| + | T0 sysclk, I_STAT.4: 6 5 4 3 2 1 15 14 | ||
| + | T1 sysclk, I_STAT.5: 6 5 4 3 2 1 15 14 | ||
| + | T0 sysclk, CAUSE.IP2: 13 12 11 10 9 8 7 6 | ||
| + | T1 sysclk reset at VBlank, value when I_STAT.0 seen: 43416 57862 57863 57865 57857 57859 57867 57864 | ||
| + | T1 hblank reset at VBlank, value when I_STAT.0 seen: 237 237 237 237 237 237 237 237 | ||
| + | T1 hblank free, hblanks between VBlank IRQs: 263 263 263 263 | ||
| + | OTC 16 words: CHCR.24 clear at 55, I_STAT.3 at 55, DICR 31-24 C0 | ||
| + | OTC 16 words: CHCR.24 clear at 31, I_STAT.3 at 31, DICR 31-24 C0 | ||
| + | OTC 16 words: CHCR.24 clear at 31, I_STAT.3 at 31, DICR 31-24 C0 | ||
| + | OTC 64 words: CHCR.24 clear at 89, I_STAT.3 at 89, DICR 31-24 C0 | ||
| + | OTC 64 words: CHCR.24 clear at 89, I_STAT.3 at 89, DICR 31-24 C0 | ||
| + | OTC 64 words: CHCR.24 clear at 79, I_STAT.3 at 79, DICR 31-24 C0 | ||
| + | OTC 256 words: CHCR.24 clear at 286, I_STAT.3 at 286, DICR 31-24 C0 | ||
| + | OTC 256 words: CHCR.24 clear at 286, I_STAT.3 at 286, DICR 31-24 C0 | ||
| + | OTC 256 words: CHCR.24 clear at 286, I_STAT.3 at 286, DICR 31-24 C0 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 06JRG.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 06 JRG JOY REGISTERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | As found: STAT 00008805 MODE 000D CTRL 0000 BAUD 0088 | ||
| + | lw 1F801048 0000000D, lw 1F80104C 00880000, lhu 1F80104C 0000, lhu 1F801046 0000 | ||
| + | lbu STAT +0..+3 05 C0 00 00 | ||
| + | Empty RX: lbu 47, lhu 4747, lw 47474747 | ||
| + | MODE FFFF: 013F | ||
| + | MODE 0: 0000 | ||
| + | BAUD FFFF: FFFF | ||
| + | BAUD 1235: 1235 | ||
| + | CTRL one bit at a time (13 never): read, STAT, I_STAT.7 | ||
| + | bit 0: CTRL 0001 STAT 0005 I7 0 | ||
| + | bit 1: CTRL 0002 STAT 0005 I7 0 | ||
| + | bit 2: CTRL 0004 STAT 0005 I7 0 | ||
| + | bit 3: CTRL 0008 STAT 0007 I7 0 | ||
| + | bit 5: CTRL 0020 STAT 0007 I7 0 | ||
| + | bit 7: CTRL 0000 STAT 0007 I7 0 | ||
| + | bit 8: CTRL 0100 STAT 0007 I7 0 | ||
| + | bit 9: CTRL 0200 STAT 0007 I7 0 | ||
| + | bit 10: CTRL 0400 STAT 0207 I7 1 | ||
| + | bit 11: CTRL 0800 STAT 0207 I7 1 | ||
| + | bit 12: CTRL 1000 STAT 0007 I7 0 | ||
| + | bit 14: CTRL 0000 STAT 0007 I7 0 | ||
| + | bit 15: CTRL 0000 STAT 0007 I7 0 | ||
| + | CTRL DFAF: 1F2F, STAT 0207 | ||
| + | CTRL 0410 (ack with TX IRQ on): 0400, STAT 0207 | ||
| + | Before reset: MODE 013E BAUD 1234 CTRL 0828 STAT 0207 | ||
| + | CTRL 0040: MODE 0000 BAUD 0000 CTRL 0000 STAT 00000005 | ||
| + | sw 0000000D to 1F801048: MODE 000D CTRL 0000 | ||
| + | sb 44 to BAUD: 0044 | ||
| + | sb 01 to BAUD+1: 0100 | ||
| + | Left: MODE 000D BAUD 0088 CTRL 0000 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 07JBD.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 07 JBD JOY SIO BAUD TIMER | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | JOY_STAT >> 11, 8 lw in a row, after sh BAUD in the same run | ||
| + | MODE 000D BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 005) | ||
| + | MODE 000D BAUD 0001: 0 0 0 0 0 0 0 0 (low 005) | ||
| + | MODE 000D BAUD 0002: 1 1 1 1 1 1 1 1 (low 005) | ||
| + | MODE 000D BAUD 1000: 800 7FC 7F8 7ED 7E9 7E5 7E1 7D6 (low 005) | ||
| + | MODE 000D BAUD FFFF: 7FFF 7FFB 7FF7 7FEC 7FE8 7FE4 7FE0 7FD5 (low 005) | ||
| + | MODE 000E BAUD 0088: 440 43C 438 42D 429 425 421 416 (low 005) | ||
| + | MODE 000E BAUD 0001: 8 4 8 5 1 5 1 6 (low 005) | ||
| + | MODE 000E BAUD 0002: 10 C 8 D 9 5 1 6 (low 005) | ||
| + | MODE 000E BAUD 1000: 8000 7FFC 7FF8 7FED 7FE9 7FE5 7FE1 7FD6 (low 005) | ||
| + | MODE 000E BAUD FFFF: 7FFF8 7FFF4 7FFF0 7FFE5 7FFE1 7FFDD 7FFD9 7FFCE (low 005) | ||
| + | MODE 000F BAUD 0088: 1100 10FC 10F8 10ED 10E9 10E5 10E1 10D6 (low 005) | ||
| + | MODE 000F BAUD 0001: 20 1C 18 D 9 5 1 16 (low 005) | ||
| + | MODE 000F BAUD 0002: 40 3C 38 28 24 20 1C 11 (low 005) | ||
| + | MODE 000F BAUD 1000: 20000 1FFFC 1FFF8 1FFED 1FFE9 1FFE5 1FFE1 1FFD6 (low 005) | ||
| + | MODE 000F BAUD FFFF: 1FFFE0 1FFFDC 1FFFD8 1FFFCD 1FFFC9 1FFFC5 1FFFC1 1FFFB6 (low 005) | ||
| + | MODE 000C BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 005) | ||
| + | MODE 000C BAUD 0001: 0 0 0 0 0 0 0 0 (low 005) | ||
| + | MODE 000C BAUD 0002: 1 1 1 1 1 1 1 1 (low 005) | ||
| + | MODE 000C BAUD 1000: 800 7FC 7F8 7ED 7E9 7E5 7E1 7D6 (low 005) | ||
| + | MODE 000C BAUD FFFF: 7FFF 7FFB 7FF7 7FEC 7FE8 7FE4 7FE0 7FD5 (low 005) | ||
| + | No write, MODE 000D BAUD 0088: 2B 1E 1A 16 12 7 3 43 (low 005) | ||
| + | No write, MODE 000E BAUD 1000: 7FA9 7F9E 7F9A 7F96 7F92 7F87 7F83 7F7F (low 005) | ||
| + | MODE 000E->000F write, BAUD 1000: timer before 31B7 after 31A8 | ||
| + | SIO_STAT >> 11 (SIO1 as found MODE 0000 BAUD 0000) | ||
| + | MODE 004D BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 185) | ||
| + | MODE 004D BAUD 0002: 1 1 1 1 1 1 1 1 (low 185) | ||
| + | MODE 004D BAUD FFFF: 7FFF 7FFB 7FF7 7FEC 7FE8 7FE4 7FE0 7FD5 (low 185) | ||
| + | MODE 004E BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 185) | ||
| + | MODE 004E BAUD 0002: 1 1 1 1 1 1 1 1 (low 185) | ||
| + | MODE 004E BAUD FFFF: 7FFF 7FFB 7FF7 7FEC 7FE8 7FE4 7FE0 7FD5 (low 185) | ||
| + | MODE 004F BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 185) | ||
| + | MODE 004F BAUD 0002: 1 1 1 1 1 1 1 1 (low 185) | ||
| + | MODE 004F BAUD FFFF: 7FFF 7FFB 7FF7 7FE7 7FE3 7FDF 7FDB 7FD0 (low 185) | ||
| + | MODE 004C BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 185) | ||
| + | MODE 004C BAUD 0002: 1 1 1 1 1 1 1 1 (low 185) | ||
| + | MODE 004C BAUD FFFF: 7FFF 7FFB 7FF7 7FEC 7FE8 7FE4 7FE0 7FD5 (low 185) | ||
| + | No write, MODE 004E BAUD 00DC: 10 5 1 6B 67 5C 58 54 (low 185) | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 08JTX.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 08 JTX JOY BYTE TIMES | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Each row: stopwatch:STAT&3FF at every change, from the write to JOY_DATA | ||
| + | TXEN only (M000D B0088 C0001): | ||
| + | 128:1 1213:5 | ||
| + | 77:0 206:1 1195:5 | ||
| + | 82:0 187:1 1231:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | TXEN RXEN (M000D B0088 C0005): | ||
| + | 77:0 182:1 952:3 1251:7 | ||
| + | 77:0 201:1 974:3 1217:7 | ||
| + | 77:0 184:1 960:3 1253:7 | ||
| + | then CTRL 0001, rx FF (1) | ||
| + | TXEN, slot 1 selected (M000D B0088 C0003): | ||
| + | 77:0 187:1 1225:5 1359:7 | ||
| + | 77:0 206:1 1246:5 1383:7 | ||
| + | 77:0 182:1 1225:5 1363:7 | ||
| + | then CTRL 0003, rx FF (1) | ||
| + | BAUD 0044 (M000D B0044 C0001): | ||
| + | 77:1 611:5 | ||
| + | 82:1 635:5 | ||
| + | 82:1 617:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | BAUD 0022 (M000D B0022 C0001): | ||
| + | 81:1 294:5 | ||
| + | 77:1 317:5 | ||
| + | 77:1 293:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | BAUD 0110 (M000D B0110 C0001): | ||
| + | 77:0 182:1 2347:5 | ||
| + | 77:0 418:1 2577:5 | ||
| + | 77:0 185:1 2341:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | BAUD 0089 (M000D B0089 C0001): | ||
| + | 87:0 192:1 1230:5 | ||
| + | 77:0 206:1 1244:5 | ||
| + | 77:0 185:1 1275:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | MUL16 (M000E B0088 C0001): | ||
| + | 82:0 1788:1 19208:5 | ||
| + | 77:0 1750:1 19167:5 | ||
| + | 77:0 1780:1 19188:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | factor 0 (M000C B0088 C0001): | ||
| + | 82:0 187:1 1223:5 | ||
| + | 77:0 201:1 1194:5 | ||
| + | 77:0 188:1 1227:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | 5 bits (M0001 B0088 C0001): | ||
| + | 82:0 187:1 851:5 | ||
| + | 77:0 201:1 820:5 | ||
| + | 77:0 184:1 850:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | 8 bits parity (M001D B0088 C0005): | ||
| + | 81:0 186:1 1124:3 1364:7 | ||
| + | 82:0 206:1 1091:3 1336:7 | ||
| + | 77:0 185:1 1122:3 1367:7 | ||
| + | then CTRL 0001, rx FF (1) | ||
| + | CLK inverted (M010D B0088 C0001): | ||
| + | 74:0 185:1 1230:5 | ||
| + | 87:0 211:1 1202:5 | ||
| + | 83:0 188:1 1232:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | Poll turn: 73 turns in 4000 cycles | ||
| + | TXEN 0 at the write: 93:4 | ||
| + | then TXEN 1: 93:0 219:1 1264:5 | ||
| + | TXEN cleared after the write: 98:0 203:1 1241:5 | ||
| + | Two writes in a row: 93:0 198:1 977:3 1220:7 | ||
| + | bytes in RX after: 1 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 09JFF.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 09 JFF JOY FIFO AND IRQS | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | 10 bytes with RXEN, none read: STAT 0007 | ||
| + | lw DATA FFFFFFFF (1st and 3 previews), STAT after 0007 | ||
| + | lbu until STAT.1 clears: FF FF FF FF (4), then 3 more: 00 00 00 | ||
| + | 3 bytes, lhu DATA FFFF then STAT 0007, 2 left | ||
| + | TX IRQ CTRL 0401: before a byte STAT 0205 I7 1; 129:10200 294:10201 1316:10205 | ||
| + | acked, cond. still true: STAT 0205 I7 1 | ||
| + | RX IRQ 1 byte CTRL 0805: before a byte STAT 0005 I7 0; 91:10203 1243:10207 | ||
| + | acked, cond. still true: STAT 0207 I7 1 | ||
| + | RX IRQ 2 bytes CTRL 0905: before a byte STAT 0005 I7 0; 86:10203 1238:10207 | ||
| + | 2nd byte: 93:10203 1237:10207 | ||
| + | acked, cond. still true: STAT 0207 I7 1 | ||
| + | ACK IRQ CTRL 1001: before a byte STAT 0005 I7 0; 86:0 247:1 1277:5 | ||
| + | acked, cond. still true: STAT 0005 I7 0 | ||
| + | TX+RX IRQ CTRL 0C01: before a byte STAT 0205 I7 1; 86:10201 1238:10205 | ||
| + | acked, cond. still true: STAT 0205 I7 1 | ||
| + | RX IRQ 8 bytes CTRL 0B05: before a byte STAT 0005 I7 0; 91:10203 1243:10207 | ||
| + | acked, cond. still true: STAT 0207 I7 1 | ||
| + | TX IRQ held, I_STAT.7 acked alone: I7 0 STAT 0205 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 10SRG.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 10 SRG SIO REGISTERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | As found: STAT 00000185 MODE 0000 CTRL 0000 MISC DFDD BAUD 0000 | ||
| + | lw 1F801058 00000000, lw 1F80105C 0000DFDD, lhu 1F801052 FFFF, lhu 1F801056 0000 | ||
| + | Empty RX: lbu FE lhu FFFF lw FFFF7FFF | ||
| + | MODE FFFF: 00FF | ||
| + | MODE 0: 0000 | ||
| + | BAUD FFFF: FFFF | ||
| + | BAUD 1235: 1235 | ||
| + | CTRL one bit at a time, MODE 0 then MODE 004E: CTRL, STAT, I_STAT.8 | ||
| + | M0 bit 0: 0001 0185 0 | ||
| + | M0 bit 1: 0002 0185 0 | ||
| + | M0 bit 2: 0004 0185 0 | ||
| + | M0 bit 3: 0008 0185 0 | ||
| + | M0 bit 5: 0020 0185 0 | ||
| + | M0 bit 7: 0000 0185 0 | ||
| + | M0 bit 8: 0100 0185 0 | ||
| + | M0 bit 9: 0200 0185 0 | ||
| + | M0 bit 10: 0400 0385 1 | ||
| + | M0 bit 11: 0800 0185 0 | ||
| + | M0 bit 12: 1000 0385 1 | ||
| + | M0 bit 13: 0000 0185 0 | ||
| + | M0 bit 14: 0000 0185 0 | ||
| + | M0 bit 15: 0000 0185 0 | ||
| + | M1 bit 0: 0001 0185 0 | ||
| + | M1 bit 1: 0002 0185 0 | ||
| + | M1 bit 2: 0004 0185 0 | ||
| + | M1 bit 3: 0008 0185 0 | ||
| + | M1 bit 5: 0020 0185 0 | ||
| + | M1 bit 7: 0080 0185 0 | ||
| + | M1 bit 8: 0100 0185 0 | ||
| + | M1 bit 9: 0200 0185 0 | ||
| + | M1 bit 10: 0400 0385 1 | ||
| + | M1 bit 11: 0800 0185 0 | ||
| + | M1 bit 12: 1000 0385 1 | ||
| + | M1 bit 13: 0000 0185 0 | ||
| + | M1 bit 14: 0000 0185 0 | ||
| + | M1 bit 15: 0000 0185 0 | ||
| + | MODE 004E CTRL FFAF: 1FAF | ||
| + | MISC write, read with MODE 004E (8 bits) and 0042 (5 bits): | ||
| + | 1234: 3412 D4D2, read again D4D2 | ||
| + | FFFF: FFFF DFDF, read again DFDF | ||
| + | 0000: 0000 C0C0, read again C0C0 | ||
| + | A5C3: C3A5 C3C5, read again C3C5 | ||
| + | MISC 1234 then 5000 cycles: 3412 | ||
| + | Before reset: MODE 004E CTRL 0023 MISC 7856 BAUD 00DC STAT 0385 | ||
| + | CTRL 0040: MODE 0000 CTRL 0000 MISC 7856 BAUD 0000 STAT 0000E185 | ||
| + | Put back: MODE 0000 CTRL 0000 BAUD 0000 (MISC left 7856) | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 11STX.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 11 STX SIO TRANSFERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | MODE 004D (8N1 MUL1) BAUD 0088; stopwatch:STAT&3FF (+I_STAT.7,8 at bits 16,17) | ||
| + | TXEN C0001: before STAT 0185 I8 0; write 55h: 144:180 307:181 1591:185 | ||
| + | RX bytes 0, CTRL 0001 | ||
| + | TXEN DTR RTS C0023: before STAT 0185 I8 0; write 55h: 116:181 1526:185 | ||
| + | RX bytes 0, CTRL 0023 | ||
| + | +TX IRQ C0423: before STAT 0385 I8 1; write 55h: 110:20381 1511:20385 | ||
| + | RX bytes 0, CTRL 0423 | ||
| + | TXEN RXEN DTR RTS C0027: before STAT 0185 I8 0; write 55h: 115:180 270:181 1547:185 | ||
| + | RX bytes 0, CTRL 0027 | ||
| + | +RX IRQ C0827: before STAT 0185 I8 0; write 55h: 120:181 1524:185 | ||
| + | RX bytes 0, CTRL 0827 | ||
| + | +DSR IRQ C1027: before STAT 0385 I8 1; write 55h: 115:20381 1466:20385 | ||
| + | RX bytes 0, CTRL 1027 | ||
| + | RXEN only, 20000 cycles: 102:20185 | ||
| + | RX bytes 0 | ||
| + | Write with TXEN 0, TXEN 1 later: 1114:180 1251:181 2553:185 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 12JPD.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 12 JPD PAD IN SLOT 1 | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Slot 1, 01 42 00 00 00..., every change of JOY_STAT (+I_STAT.7 at bit 16): | ||
| + | 01->FF 145:0 289:1 1318:5 1470:7 1746:10287 1836:10207 | ||
| + | 42->41 92:1 1226:5 1378:7 1655:10287 1745:10207 | ||
| + | 00->5A 92:0 232:1 1269:5 1421:7 1759:10287 1849:10207 | ||
| + | 00->FF 93:0 228:1 1250:5 1404:7 1681:10007 1771:10287 1861:10207 | ||
| + | 00->FF 92:0 232:1 1256:5 1408:7 | ||
| + | send 01 42 00 00 00 00 00 00 00 | ||
| + | got FF 41 5A FF FF (4 acked) | ||
| + | /ACK at 1746 1655 1759 1771; low for 90 90 90 90 | ||
| + | 8 more reads (/ACK times per byte): | ||
| + | 4: FF 41 5A FF FF | 1676 1671 1797 1735 | ||
| + | 4: FF 41 5A FF FF | 1663 1680 1613 1729 | ||
| + | 4: FF 41 5A FF FF | 1671 1678 1695 1740 | ||
| + | 4: FF 41 5A FF FF | 1664 1666 1618 1730 | ||
| + | 4: FF 41 5A FF FF | 1661 1675 1672 1741 | ||
| + | 4: FF 41 5A FF FF | 1671 1678 1605 1740 | ||
| + | 4: FF 41 5A FF FF | 1664 1666 1618 1730 | ||
| + | 4: FF 41 5A FF FF | 1661 1675 1672 1741 | ||
| + | 01h, tight loop: /ACK after, low for: 1702/95 1702/107 1702/107 1713/96 1702/107 1702/96 1702/107 1702/107 | ||
| + | Ack while /ACK low (seen at 1696): STAT then 0287; after /ACK high 0207; acked again 0007 | ||
| + | 01h with CTRL 0003 (no ACK IRQ): 93:1 1158:5 1315:7 1653:87 1743:7 | ||
| + | 01h at once after selecting: 98:0 212:1 1301:5 1462:7 1738:10287 1828:10207 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 13JCF.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 13 JCF PAD CONFIG MODE | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Slot 1 01 42 first:send 01 42 00 00 00 00 00 00 00 | ||
| + | got FF 41 5A FF FF (4 acked) | ||
| + | /ACK at 1831 1736 1673 1741; low for 90 90 90 90 | ||
| + | send 01 43 00 01 00 00 00 00 00 | ||
| + | got FF 41 5A 01 (3 acked) | ||
| + | /ACK at 1676 1667 1667; low for 90 90 90 | ||
| + | send 01 45 00 00 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1671; low for 90 | ||
| + | send 01 46 00 00 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1671; low for 90 | ||
| + | send 01 46 00 01 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1671; low for 90 | ||
| + | send 01 47 00 00 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1671; low for 90 | ||
| + | send 01 4C 00 00 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1671; low for 90 | ||
| + | send 01 4C 00 01 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1671; low for 90 | ||
| + | send 01 48 00 00 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1671; low for 90 | ||
| + | send 01 42 00 00 00 00 00 00 00 | ||
| + | got FF 41 5A FF FF (4 acked) | ||
| + | /ACK at 1671 1680 1746 1687; low for 90 90 90 90 | ||
| + | send 01 43 00 00 00 00 00 00 00 | ||
| + | got FF 41 5A 01 (3 acked) | ||
| + | /ACK at 1671 1680 1746; low for 90 90 90 | ||
| + | send 01 42 00 00 00 00 00 00 00 | ||
| + | got FF 41 5A FF FF (4 acked) | ||
| + | /ACK at 1664 1672 1737 1730; low for 90 90 152 90 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 14IEX.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 14 IEX IRQ ENTRY | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Kernel's 80000080h: 3C1A0000 275A0C80 03400008 00000000 | ||
| + | SR as found 40000401. Rows: instructions after the trigger @ timer 2 in the handler | ||
| + | mtc0 SR IEc 0->1, IRQ pending: 2@64 2@54 2@54 2@58 2@54 2@54 | ||
| + | last CAUSE 00000000 SR 40000404 I_STAT 0009 | ||
| + | mtc0 SR Im2 0->1, IEc 1, IRQ pending: 1@76 none none none none none | ||
| + | sh I_MASK 8, I_STAT.3 set, IEc 1: none none none none none none | ||
| + | sw DICR force, I_MASK 8, IEc 1: 8@60 8@59 8@59 8@59 8@59 8@59 | ||
| + | T2 target 100-107: 100@135 101@141 102@142 103@143 104@144 105@145 106@146 107@147 | ||
| + | T2 target 150-157: 150@190 151@191 152@192 153@193 154@200 155@195 156@198 157@197 | ||
| + | last CAUSE 00000000 SR 40000404 I_STAT 0049 | ||
| + | T2 into a 3 instruction loop, target 100-115: EPC word (from the mode write) and BD | ||
| + | 2/0 2/1 1/0 2/0 2/1 1/0 2/0 2/1 1/0 2/0 2/1 1/0 2/0 2/1 1/0 2/0 | ||
| + | Kernel's vector back: 3C1A0000 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | ### 27 September 2026 card-g | ||
| + | |||
| + | Raw output: [00RUN.txt](/tests/raw/20260927T0000Z-5501a-card-g/irqsio/00RUN.txt) · [01IMR.txt](/tests/raw/20260927T0000Z-5501a-card-g/irqsio/01IMR.txt) · [02IST.txt](/tests/raw/20260927T0000Z-5501a-card-g/irqsio/02IST.txt) · [03IED.txt](/tests/raw/20260927T0000Z-5501a-card-g/irqsio/03IED.txt) · [04IP2.txt](/tests/raw/20260927T0000Z-5501a-card-g/irqsio/04IP2.txt) · [05ILT.txt](/tests/raw/20260927T0000Z-5501a-card-g/irqsio/05ILT.txt) · [06JRG.txt](/tests/raw/20260927T0000Z-5501a-card-g/irqsio/06JRG.txt) · [07JBD.txt](/tests/raw/20260927T0000Z-5501a-card-g/irqsio/07JBD.txt) · [08JTX.txt](/tests/raw/20260927T0000Z-5501a-card-g/irqsio/08JTX.txt) · [09JFF.txt](/tests/raw/20260927T0000Z-5501a-card-g/irqsio/09JFF.txt) · [10SRG.txt](/tests/raw/20260927T0000Z-5501a-card-g/irqsio/10SRG.txt) · [11STX.txt](/tests/raw/20260927T0000Z-5501a-card-g/irqsio/11STX.txt) · [12JPD.txt](/tests/raw/20260927T0000Z-5501a-card-g/irqsio/12JPD.txt) · [13JCF.txt](/tests/raw/20260927T0000Z-5501a-card-g/irqsio/13JCF.txt) · [14IEX.txt](/tests/raw/20260927T0000Z-5501a-card-g/irqsio/14IEX.txt) | ||
| + | |||
| + | 00RUN.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | 14 tests | ||
| + | A chain program, linked at 80010000 | ||
| + | Saved on the card in slot 2, from image 1 | ||
| + | COP0 at start: BPC 00000000 BDA 00000000 TAR 8010F9D4 DCIC 00000000 BadVaddr 00000480 BDAM 00000000 | ||
| + | BPCM 00000000 SR 40000000 Cause 00000020 EPC 80110540 PRId 00000002 | ||
| + | ``` | ||
| + | |||
| + | 01IMR.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 01 IMR I MASK READBACK | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | I_MASK as found: 0009 | ||
| + | sw FFFFFFFF, then lw 960507FF | ||
| + | sw FFFFFFFF, then lhu +0 07FF, lhu +2 3C03 | ||
| + | sw FFFFFFFF, then lbu +0..+3 FF 07 C6 30 | ||
| + | sw 0000F800 (bits 11-15), then lhu 0000 | ||
| + | sw 12345555, then lhu 0555 | ||
| + | sw 0, then lw 24840000 | ||
| + | Partial stores: baseline, source, op, then the low half read back | ||
| + | base 000 src AABBCCDD: sb+0=4DD sb+1=500 sb+2=000 sb+3=000 sh+0=4DD sh+2=000 sw=4DD | ||
| + | base 000 src FEDCBA98: sb+0=298 sb+1=000 sb+2=000 sb+3=000 sh+0=298 sh+2=000 sw=298 | ||
| + | base 7FF src AABBCCDD: sb+0=4DD sb+1=500 sb+2=000 sb+3=000 sh+0=4DD sh+2=000 sw=4DD | ||
| + | base 7FF src FEDCBA98: sb+0=298 sb+1=000 sb+2=000 sb+3=000 sh+0=298 sh+2=000 sw=298 | ||
| + | sw 2A5 then lw at once: 000002A5 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 02IST.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 02 IST I STAT ACK | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Raised by GP0 1Fh, DICR force, timers 0-2: I_STAT 007A (lw 3C03007A) | ||
| + | lhu +2 9067, lbu +0..+3 7A 00 A2 AF | ||
| + | sw FFFFFFFF: 007A | ||
| + | sw ~10h (ack timer 0): 006A | ||
| + | sw 0: 0000 | ||
| + | sw FFFFFFFF after 0 (can a write set a bit?): 0000 | ||
| + | With I_MASK 07FF: I_STAT 007A, I_MASK 07FF | ||
| + | Partial stores after raise_all: op=result (bits 0 and 2 may come and go) | ||
| + | src 00000000: sb+0=07A/000 sb+1=07A/000 sb+2=07A/000 sb+3=07A/000 sh+0=07A/000 sh+2=07A/000 sw=07A/000 | ||
| + | src FFFFFFFF: sb+0=07A/07A sb+1=07A/000 sb+2=07A/000 sb+3=07A/000 sh+0=07A/07A sh+2=07A/000 sw=07A/07A | ||
| + | src FFFFFFEF: sb+0=07A/06A sb+1=07A/000 sb+2=07A/000 sb+3=07A/000 sh+0=07A/06A sh+2=07A/000 sw=07A/06A | ||
| + | src 000000FF: sb+0=07A/07A sb+1=07A/000 sb+2=07A/000 sb+3=07A/000 sh+0=07A/07A sh+2=07A/000 sw=07A/07A | ||
| + | sb+1 src 000000FB: before 07A after 000 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 03IED.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 03 IED I STAT EDGES | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | DICR force on: I_STAT.3 1, DICR 80008000 | ||
| + | Ack I_STAT.3 with force still on: 0 | ||
| + | Force written 1 again: 0 | ||
| + | Force off: 0 | ||
| + | Force on again: 1 | ||
| + | GP0 1Fh: I_STAT.1 1 GPUSTAT.24 1 | ||
| + | Ack I_STAT.1, GP0 1Fh again with GPUSTAT.24 set: I_STAT.1 0 | ||
| + | GP1 02h: GPUSTAT.24 0, I_STAT.1 0 | ||
| + | GP0 1Fh after GP1 02h: I_STAT.1 1 | ||
| + | Timer 0 target 99 repeat pulse: I_STAT.4 set 990 times in 100000 cycles | ||
| + | Timer 0 target 99 repeat toggle: I_STAT.4 set 495 times in 100000 cycles | ||
| + | Toggle mode, bit 10 of 16 mode reads: 0 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1 | ||
| + | Pulse mode, bit 10 of 16 mode reads: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| + | One-shot target 99, after acking the first: I_STAT.4 0, mode 0C18 | ||
| + | One-shot, target and FFFFh on, counter FFF0h: I_STAT.4 1 mode 1C30 | ||
| + | ... then 120000 cycles on (past target 30000): I_STAT.4 0 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 04IP2.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 04 IP2 CAUSE IP2 | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | SR 40000400 CAUSE 00000000 with interrupts off here | ||
| + | I_STAT.3 set, I_MASK 0: CAUSE 00000000 | ||
| + | I_MASK 8: CAUSE 00000400 | ||
| + | SR Im all 0 (SR 40000000): CAUSE 00000400 | ||
| + | I_MASK 0 again: CAUSE 00000000 | ||
| + | mtc0 CAUSE FFFFFFFF: 00000300; then 0: 00000000 | ||
| + | mtc0 CAUSE 00000400 with no IRQ: 00000000 | ||
| + | IP2 after sh I_MASK=8 (I_STAT.3 set), n nops: 0:0 1:0 2:1 3:1 4:1 6:1 | ||
| + | IP2 after sh I_MASK=8 (I_STAT.3 set), n nops: 0:0 1:0 2:1 3:1 4:1 6:1 | ||
| + | IP2 after sw I_STAT=0 (was set, I_MASK 8), n nops: 0:1 1:1 2:0 3:0 4:0 6:0 | ||
| + | IP2 after sw DICR force (I_MASK 8), n nops: 0:0 1:0 2:0 3:0 4:1 6:1 | ||
| + | I_STAT.3 after all that, acked: 0; CAUSE 00000000 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 05ILT.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 05 ILT IRQ LATENCY POLLED | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Poll loop period, 1000 turns: 15020 cycles | ||
| + | Counter at the turn that saw the IRQ, minus the target (targets 300-307): | ||
| + | T2 sysclk, I_STAT.6: 11 5 4 3 2 1 15 14 | ||
| + | T2 sysclk, CAUSE.IP2: 4 12 11 10 9 8 7 6 | ||
| + | T2 sysclk/8, I_STAT.6 (in 8s): 1 1 1 0 1 1 0 0 | ||
| + | T0 sysclk, I_STAT.4: 6 5 4 3 2 1 15 14 | ||
| + | T1 sysclk, I_STAT.5: 6 5 4 3 2 1 15 14 | ||
| + | T0 sysclk, CAUSE.IP2: 13 12 11 10 9 8 7 6 | ||
| + | T1 sysclk reset at VBlank, value when I_STAT.0 seen: 43431 57866 57863 57861 57869 57856 57855 57861 | ||
| + | T1 hblank reset at VBlank, value when I_STAT.0 seen: 237 237 237 237 237 237 237 237 | ||
| + | T1 hblank free, hblanks between VBlank IRQs: 263 263 263 263 | ||
| + | OTC 16 words: CHCR.24 clear at 55, I_STAT.3 at 55, DICR 31-24 C0 | ||
| + | OTC 16 words: CHCR.24 clear at 31, I_STAT.3 at 31, DICR 31-24 C0 | ||
| + | OTC 16 words: CHCR.24 clear at 31, I_STAT.3 at 31, DICR 31-24 C0 | ||
| + | OTC 64 words: CHCR.24 clear at 89, I_STAT.3 at 89, DICR 31-24 C0 | ||
| + | OTC 64 words: CHCR.24 clear at 89, I_STAT.3 at 89, DICR 31-24 C0 | ||
| + | OTC 64 words: CHCR.24 clear at 79, I_STAT.3 at 79, DICR 31-24 C0 | ||
| + | OTC 256 words: CHCR.24 clear at 286, I_STAT.3 at 286, DICR 31-24 C0 | ||
| + | OTC 256 words: CHCR.24 clear at 286, I_STAT.3 at 286, DICR 31-24 C0 | ||
| + | OTC 256 words: CHCR.24 clear at 286, I_STAT.3 at 286, DICR 31-24 C0 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 06JRG.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 06 JRG JOY REGISTERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | As found: STAT 0001E805 MODE 000D CTRL 0000 BAUD 0088 | ||
| + | lw 1F801048 0000000D, lw 1F80104C 00880000, lhu 1F80104C 0000, lhu 1F801046 0001 | ||
| + | lbu STAT +0..+3 05 70 00 00 | ||
| + | Empty RX: lbu 47, lhu 4747, lw 47474747 | ||
| + | MODE FFFF: 013F | ||
| + | MODE 0: 0000 | ||
| + | BAUD FFFF: FFFF | ||
| + | BAUD 1235: 1235 | ||
| + | CTRL one bit at a time (13 never): read, STAT, I_STAT.7 | ||
| + | bit 0: CTRL 0001 STAT 0005 I7 0 | ||
| + | bit 1: CTRL 0002 STAT 0005 I7 0 | ||
| + | bit 2: CTRL 0004 STAT 0005 I7 0 | ||
| + | bit 3: CTRL 0008 STAT 0007 I7 0 | ||
| + | bit 5: CTRL 0020 STAT 0007 I7 0 | ||
| + | bit 7: CTRL 0000 STAT 0007 I7 0 | ||
| + | bit 8: CTRL 0100 STAT 0007 I7 0 | ||
| + | bit 9: CTRL 0200 STAT 0007 I7 0 | ||
| + | bit 10: CTRL 0400 STAT 0207 I7 1 | ||
| + | bit 11: CTRL 0800 STAT 0207 I7 1 | ||
| + | bit 12: CTRL 1000 STAT 0007 I7 0 | ||
| + | bit 14: CTRL 0000 STAT 0007 I7 0 | ||
| + | bit 15: CTRL 0000 STAT 0007 I7 0 | ||
| + | CTRL DFAF: 1F2F, STAT 0207 | ||
| + | CTRL 0410 (ack with TX IRQ on): 0400, STAT 0207 | ||
| + | Before reset: MODE 013E BAUD 1234 CTRL 0828 STAT 0207 | ||
| + | CTRL 0040: MODE 0000 BAUD 0000 CTRL 0000 STAT 00000005 | ||
| + | sw 0000000D to 1F801048: MODE 000D CTRL 0000 | ||
| + | sb 44 to BAUD: 0044 | ||
| + | sb 01 to BAUD+1: 0100 | ||
| + | Left: MODE 000D BAUD 0088 CTRL 0000 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 07JBD.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 07 JBD JOY SIO BAUD TIMER | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | JOY_STAT >> 11, 8 lw in a row, after sh BAUD in the same run | ||
| + | MODE 000D BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 005) | ||
| + | MODE 000D BAUD 0001: 0 0 0 0 0 0 0 0 (low 005) | ||
| + | MODE 000D BAUD 0002: 1 1 1 1 1 1 1 1 (low 005) | ||
| + | MODE 000D BAUD 1000: 800 7FC 7F8 7ED 7E9 7E5 7E1 7D6 (low 005) | ||
| + | MODE 000D BAUD FFFF: 7FFF 7FFB 7FF7 7FEC 7FE8 7FE4 7FE0 7FD5 (low 005) | ||
| + | MODE 000E BAUD 0088: 440 43C 438 42D 429 425 421 416 (low 005) | ||
| + | MODE 000E BAUD 0001: 8 4 8 5 1 5 1 6 (low 005) | ||
| + | MODE 000E BAUD 0002: 10 C 8 8 4 10 C 1 (low 005) | ||
| + | MODE 000E BAUD 1000: 8000 7FFC 7FF8 7FED 7FE9 7FE5 7FE1 7FD6 (low 005) | ||
| + | MODE 000E BAUD FFFF: 7FFF8 7FFF4 7FFF0 7FFE5 7FFE1 7FFDD 7FFD9 7FFCE (low 005) | ||
| + | MODE 000F BAUD 0088: 1100 10FC 10F8 10ED 10E9 10E5 10E1 10D6 (low 005) | ||
| + | MODE 000F BAUD 0001: 20 1C 18 D 9 5 1 16 (low 005) | ||
| + | MODE 000F BAUD 0002: 40 3C 38 2D 29 25 21 16 (low 005) | ||
| + | MODE 000F BAUD 1000: 20000 1FFFC 1FFF8 1FFE9 1FFE5 1FFE1 1FFDD 1FFD2 (low 005) | ||
| + | MODE 000F BAUD FFFF: 1FFFE0 1FFFDC 1FFFD8 1FFFCD 1FFFC9 1FFFC5 1FFFC1 1FFFB6 (low 005) | ||
| + | MODE 000C BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 005) | ||
| + | MODE 000C BAUD 0001: 0 0 0 0 0 0 0 0 (low 005) | ||
| + | MODE 000C BAUD 0002: 1 1 1 1 1 1 1 1 (low 005) | ||
| + | MODE 000C BAUD 1000: 800 7FC 7F8 7E9 7E5 7E1 7DD 7D2 (low 005) | ||
| + | MODE 000C BAUD FFFF: 7FFF 7FFB 7FF7 7FEC 7FE8 7FE4 7FE0 7FD5 (low 005) | ||
| + | No write, MODE 000D BAUD 0088: 25 1A 16 12 E 3 43 3F (low 005) | ||
| + | No write, MODE 000E BAUD 1000: 7FA9 7F9E 7F9A 7F96 7F92 7F87 7F83 7F7F (low 005) | ||
| + | MODE 000E->000F write, BAUD 1000: timer before 31B7 after 31A8 | ||
| + | SIO_STAT >> 11 (SIO1 as found MODE 0000 BAUD 0000) | ||
| + | MODE 004D BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 185) | ||
| + | MODE 004D BAUD 0002: 1 1 1 1 1 1 1 1 (low 185) | ||
| + | MODE 004D BAUD FFFF: 7FFF 7FFB 7FF7 7FEC 7FE8 7FE4 7FE0 7FD5 (low 185) | ||
| + | MODE 004E BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 185) | ||
| + | MODE 004E BAUD 0002: 1 1 1 1 1 1 1 1 (low 185) | ||
| + | MODE 004E BAUD FFFF: 7FFF 7FFB 7FF7 7FEC 7FE8 7FE4 7FE0 7FD5 (low 185) | ||
| + | MODE 004F BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 185) | ||
| + | MODE 004F BAUD 0002: 1 1 1 1 1 1 1 1 (low 185) | ||
| + | MODE 004F BAUD FFFF: 7FFF 7FFB 7FF7 7FE7 7FE3 7FDF 7FDB 7FD0 (low 185) | ||
| + | MODE 004C BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 185) | ||
| + | MODE 004C BAUD 0002: 1 1 1 1 1 1 1 1 (low 185) | ||
| + | MODE 004C BAUD FFFF: 7FFF 7FFB 7FF7 7FEC 7FE8 7FE4 7FE0 7FD5 (low 185) | ||
| + | No write, MODE 004E BAUD 00DC: 10 5 1 6B 67 5C 58 54 (low 185) | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 08JTX.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 08 JTX JOY BYTE TIMES | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Each row: stopwatch:STAT&3FF at every change, from the write to JOY_DATA | ||
| + | TXEN only (M000D B0088 C0001): | ||
| + | 128:1 1213:5 | ||
| + | 77:0 206:1 1195:5 | ||
| + | 82:0 187:1 1231:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | TXEN RXEN (M000D B0088 C0005): | ||
| + | 77:0 182:1 952:3 1251:7 | ||
| + | 77:0 201:1 974:3 1217:7 | ||
| + | 77:0 184:1 960:3 1253:7 | ||
| + | then CTRL 0001, rx FF (1) | ||
| + | TXEN, slot 1 selected (M000D B0088 C0003): | ||
| + | 77:0 187:1 1225:5 1359:7 | ||
| + | 77:0 206:1 1246:5 1383:7 | ||
| + | 77:0 182:1 1225:5 1363:7 | ||
| + | then CTRL 0003, rx FF (1) | ||
| + | BAUD 0044 (M000D B0044 C0001): | ||
| + | 77:1 611:5 | ||
| + | 82:1 635:5 | ||
| + | 82:1 617:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | BAUD 0022 (M000D B0022 C0001): | ||
| + | 81:1 294:5 | ||
| + | 77:1 317:5 | ||
| + | 77:1 293:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | BAUD 0110 (M000D B0110 C0001): | ||
| + | 77:0 182:1 2347:5 | ||
| + | 77:0 418:1 2577:5 | ||
| + | 77:0 185:1 2341:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | BAUD 0089 (M000D B0089 C0001): | ||
| + | 87:0 192:1 1230:5 | ||
| + | 77:0 206:1 1244:5 | ||
| + | 77:0 185:1 1275:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | MUL16 (M000E B0088 C0001): | ||
| + | 82:0 1788:1 19208:5 | ||
| + | 77:0 1750:1 19167:5 | ||
| + | 77:0 1780:1 19188:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | factor 0 (M000C B0088 C0001): | ||
| + | 82:0 187:1 1223:5 | ||
| + | 77:0 201:1 1194:5 | ||
| + | 77:0 188:1 1227:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | 5 bits (M0001 B0088 C0001): | ||
| + | 82:0 187:1 851:5 | ||
| + | 77:0 201:1 820:5 | ||
| + | 77:0 184:1 850:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | 8 bits parity (M001D B0088 C0005): | ||
| + | 81:0 186:1 1124:3 1364:7 | ||
| + | 82:0 206:1 1091:3 1336:7 | ||
| + | 77:0 185:1 1122:3 1367:7 | ||
| + | then CTRL 0001, rx FF (1) | ||
| + | CLK inverted (M010D B0088 C0001): | ||
| + | 74:0 185:1 1230:5 | ||
| + | 87:0 211:1 1202:5 | ||
| + | 83:0 188:1 1232:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | Poll turn: 73 turns in 4000 cycles | ||
| + | TXEN 0 at the write: 93:4 | ||
| + | then TXEN 1: 93:0 219:1 1264:5 | ||
| + | TXEN cleared after the write: 98:0 203:1 1241:5 | ||
| + | Two writes in a row: 93:0 198:1 977:3 1220:7 | ||
| + | bytes in RX after: 1 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 09JFF.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 09 JFF JOY FIFO AND IRQS | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | 10 bytes with RXEN, none read: STAT 0007 | ||
| + | lw DATA FFFFFFFF (1st and 3 previews), STAT after 0007 | ||
| + | lbu until STAT.1 clears: FF FF FF FF (4), then 3 more: 00 00 00 | ||
| + | 3 bytes, lhu DATA FFFF then STAT 0007, 2 left | ||
| + | TX IRQ CTRL 0401: before a byte STAT 0205 I7 1; 129:10200 294:10201 1316:10205 | ||
| + | acked, cond. still true: STAT 0205 I7 1 | ||
| + | RX IRQ 1 byte CTRL 0805: before a byte STAT 0005 I7 0; 91:10203 1243:10207 | ||
| + | acked, cond. still true: STAT 0207 I7 1 | ||
| + | RX IRQ 2 bytes CTRL 0905: before a byte STAT 0005 I7 0; 86:10203 1238:10207 | ||
| + | 2nd byte: 93:10203 1237:10207 | ||
| + | acked, cond. still true: STAT 0207 I7 1 | ||
| + | ACK IRQ CTRL 1001: before a byte STAT 0005 I7 0; 86:0 247:1 1277:5 | ||
| + | acked, cond. still true: STAT 0005 I7 0 | ||
| + | TX+RX IRQ CTRL 0C01: before a byte STAT 0205 I7 1; 86:10201 1238:10205 | ||
| + | acked, cond. still true: STAT 0205 I7 1 | ||
| + | RX IRQ 8 bytes CTRL 0B05: before a byte STAT 0005 I7 0; 91:10203 1243:10207 | ||
| + | acked, cond. still true: STAT 0207 I7 1 | ||
| + | TX IRQ held, I_STAT.7 acked alone: I7 0 STAT 0205 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 10SRG.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 10 SRG SIO REGISTERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | As found: STAT 00000185 MODE 0000 CTRL 0000 MISC DFFD BAUD 0000 | ||
| + | lw 1F801058 00000000, lw 1F80105C 0000DFFD, lhu 1F801052 FFFF, lhu 1F801056 0000 | ||
| + | Empty RX: lbu FE lhu FFFF lw FFFF7FFF | ||
| + | MODE FFFF: 00FF | ||
| + | MODE 0: 0000 | ||
| + | BAUD FFFF: FFFF | ||
| + | BAUD 1235: 1235 | ||
| + | CTRL one bit at a time, MODE 0 then MODE 004E: CTRL, STAT, I_STAT.8 | ||
| + | M0 bit 0: 0001 0185 0 | ||
| + | M0 bit 1: 0002 0185 0 | ||
| + | M0 bit 2: 0004 0185 0 | ||
| + | M0 bit 3: 0008 0185 0 | ||
| + | M0 bit 5: 0020 0185 0 | ||
| + | M0 bit 7: 0000 0185 0 | ||
| + | M0 bit 8: 0100 0185 0 | ||
| + | M0 bit 9: 0200 0185 0 | ||
| + | M0 bit 10: 0400 0385 1 | ||
| + | M0 bit 11: 0800 0185 0 | ||
| + | M0 bit 12: 1000 0385 1 | ||
| + | M0 bit 13: 0000 0185 0 | ||
| + | M0 bit 14: 0000 0185 0 | ||
| + | M0 bit 15: 0000 0185 0 | ||
| + | M1 bit 0: 0001 0185 0 | ||
| + | M1 bit 1: 0002 0185 0 | ||
| + | M1 bit 2: 0004 0185 0 | ||
| + | M1 bit 3: 0008 0185 0 | ||
| + | M1 bit 5: 0020 0185 0 | ||
| + | M1 bit 7: 0080 0185 0 | ||
| + | M1 bit 8: 0100 0185 0 | ||
| + | M1 bit 9: 0200 0185 0 | ||
| + | M1 bit 10: 0400 0385 1 | ||
| + | M1 bit 11: 0800 0185 0 | ||
| + | M1 bit 12: 1000 0385 1 | ||
| + | M1 bit 13: 0000 0185 0 | ||
| + | M1 bit 14: 0000 0185 0 | ||
| + | M1 bit 15: 0000 0185 0 | ||
| + | MODE 004E CTRL FFAF: 1FAF | ||
| + | MISC write, read with MODE 004E (8 bits) and 0042 (5 bits): | ||
| + | 1234: 3412 D4D2, read again D4D2 | ||
| + | FFFF: FFFF DFDF, read again DFDF | ||
| + | 0000: 0000 C0C0, read again C0C0 | ||
| + | A5C3: C3A5 C3C5, read again C3C5 | ||
| + | MISC 1234 then 5000 cycles: 3412 | ||
| + | Before reset: MODE 004E CTRL 0023 MISC 7856 BAUD 00DC STAT 0385 | ||
| + | CTRL 0040: MODE 0000 CTRL 0000 MISC 7856 BAUD 0000 STAT 0000E185 | ||
| + | Put back: MODE 0000 CTRL 0000 BAUD 0000 (MISC left 7856) | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 11STX.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 11 STX SIO TRANSFERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | MODE 004D (8N1 MUL1) BAUD 0088; stopwatch:STAT&3FF (+I_STAT.7,8 at bits 16,17) | ||
| + | TXEN C0001: before STAT 0185 I8 0; write 55h: 144:180 307:181 1591:185 | ||
| + | RX bytes 0, CTRL 0001 | ||
| + | TXEN DTR RTS C0023: before STAT 0185 I8 0; write 55h: 116:181 1526:185 | ||
| + | RX bytes 0, CTRL 0023 | ||
| + | +TX IRQ C0423: before STAT 0385 I8 1; write 55h: 110:20381 1511:20385 | ||
| + | RX bytes 0, CTRL 0423 | ||
| + | TXEN RXEN DTR RTS C0027: before STAT 0185 I8 0; write 55h: 115:180 270:181 1547:185 | ||
| + | RX bytes 0, CTRL 0027 | ||
| + | +RX IRQ C0827: before STAT 0185 I8 0; write 55h: 120:181 1524:185 | ||
| + | RX bytes 0, CTRL 0827 | ||
| + | +DSR IRQ C1027: before STAT 0385 I8 1; write 55h: 115:20381 1466:20385 | ||
| + | RX bytes 0, CTRL 1027 | ||
| + | RXEN only, 20000 cycles: 102:20185 | ||
| + | RX bytes 0 | ||
| + | Write with TXEN 0, TXEN 1 later: 1114:180 1251:181 2553:185 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 12JPD.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 12 JPD PAD IN SLOT 1 | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Slot 1, 01 42 00 00 00..., every change of JOY_STAT (+I_STAT.7 at bit 16): | ||
| + | 01->FF 145:0 290:1 1321:5 1473:7 1750:10287 1842:10207 | ||
| + | 42->41 97:0 232:1 1263:5 1355:7 1693:10287 1783:10207 | ||
| + | 00->5A 92:0 232:1 1331:5 1421:7 1759:10287 1849:10207 | ||
| + | 00->FF 93:0 228:1 1314:5 1404:7 1743:10287 1843:10207 | ||
| + | 00->FF 92:0 232:1 1269:5 1421:7 | ||
| + | send 01 42 00 00 00 00 00 00 00 | ||
| + | got FF 41 5A FF FF (4 acked) | ||
| + | /ACK at 1750 1693 1759 1743; low for 92 90 90 100 | ||
| + | 8 more reads (/ACK times per byte): | ||
| + | 4: FF 41 5A FF FF | 1671 1681 1800 1734 | ||
| + | 4: FF 41 5A FF FF | 1664 1673 1708 1739 | ||
| + | 4: FF 41 5A FF FF | 1668 1686 1792 1735 | ||
| + | 4: FF 41 5A FF FF | 1671 1678 1695 1740 | ||
| + | 4: FF 41 5A FF FF | 1664 1666 1618 1730 | ||
| + | 4: FF 41 5A FF FF | 1661 1675 1672 1741 | ||
| + | 4: FF 41 5A FF FF | 1671 1678 1605 1740 | ||
| + | 4: FF 41 5A FF FF | 1664 1666 1618 1730 | ||
| + | 01h, tight loop: /ACK after, low for: 1691/95 1713/96 1702/96 1702/107 1713/107 1713/96 1702/96 1713/96 | ||
| + | Ack while /ACK low (seen at 1701): STAT then 0287; after /ACK high 0207; acked again 0007 | ||
| + | 01h with CTRL 0003 (no ACK IRQ): 93:0 207:1 1297:5 1449:7 1789:87 1879:7 | ||
| + | 01h at once after selecting: 98:0 212:1 1301:5 1462:7 1738:10287 1828:10207 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 13JCF.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 13 JCF PAD CONFIG MODE | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Slot 1 01 42 first:send 01 42 00 00 00 00 00 00 00 | ||
| + | got FF 41 5A FF FF (4 acked) | ||
| + | /ACK at 1749 1730 1686 1615; low for 92 152 90 152 | ||
| + | send 01 43 00 01 00 00 00 00 00 | ||
| + | got FF 41 5A 01 (3 acked) | ||
| + | /ACK at 1662 1677 1831; low for 90 90 90 | ||
| + | send 01 45 00 00 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1662; low for 92 | ||
| + | send 01 46 00 00 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1669; low for 92 | ||
| + | send 01 46 00 01 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1669; low for 92 | ||
| + | send 01 47 00 00 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1669; low for 92 | ||
| + | send 01 4C 00 00 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1669; low for 92 | ||
| + | send 01 4C 00 01 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1669; low for 92 | ||
| + | send 01 48 00 00 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1669; low for 92 | ||
| + | send 01 42 00 00 00 00 00 00 00 | ||
| + | got FF 41 5A FF FF (4 acked) | ||
| + | /ACK at 1669 1675 1610 1741; low for 92 90 152 90 | ||
| + | send 01 43 00 00 00 00 00 00 00 | ||
| + | got FF 41 5A 01 (3 acked) | ||
| + | /ACK at 1746 1674 1699; low for 90 100 90 | ||
| + | send 01 42 00 00 00 00 00 00 00 | ||
| + | got FF 41 5A FF FF (4 acked) | ||
| + | /ACK at 1671 1680 1746 1687; low for 90 90 90 90 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 14IEX.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 14 IEX IRQ ENTRY | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Kernel's 80000080h: 3C1A0000 275A0C80 03400008 00000000 | ||
| + | SR as found 40000401. Rows: instructions after the trigger @ timer 2 in the handler | ||
| + | mtc0 SR IEc 0->1, IRQ pending: 2@68 2@54 2@59 2@54 2@54 2@58 | ||
| + | last CAUSE 00000000 SR 40000404 I_STAT 0009 | ||
| + | mtc0 SR Im2 0->1, IEc 1, IRQ pending: 1@72 none none none none none | ||
| + | sh I_MASK 8, I_STAT.3 set, IEc 1: none none none none none none | ||
| + | sw DICR force, I_MASK 8, IEc 1: 8@60 8@63 8@59 8@59 8@59 8@59 | ||
| + | T2 target 100-107: 100@135 101@141 102@142 103@149 100@144 105@149 106@146 107@147 | ||
| + | T2 target 150-157: 150@190 151@197 152@192 153@193 150@194 155@195 156@196 157@197 | ||
| + | last CAUSE 00000000 SR 40000404 I_STAT 0049 | ||
| + | T2 into a 3 instruction loop, target 100-115: EPC word (from the mode write) and BD | ||
| + | 2/0 2/1 1/0 2/0 2/1 1/0 2/0 2/1 1/0 2/0 2/1 1/0 2/0 2/1 1/0 2/0 | ||
| + | Kernel's vector back: 3C1A0000 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | ### 27 September 2026 card-g3 | ||
| + | |||
| + | Raw output: [00RUN.txt](/tests/raw/20260927T0000Z-5501a-card-g3/irqsio/00RUN.txt) · [01IMR.txt](/tests/raw/20260927T0000Z-5501a-card-g3/irqsio/01IMR.txt) · [02IST.txt](/tests/raw/20260927T0000Z-5501a-card-g3/irqsio/02IST.txt) · [03IED.txt](/tests/raw/20260927T0000Z-5501a-card-g3/irqsio/03IED.txt) · [04IP2.txt](/tests/raw/20260927T0000Z-5501a-card-g3/irqsio/04IP2.txt) · [05ILT.txt](/tests/raw/20260927T0000Z-5501a-card-g3/irqsio/05ILT.txt) · [06JRG.txt](/tests/raw/20260927T0000Z-5501a-card-g3/irqsio/06JRG.txt) · [07JBD.txt](/tests/raw/20260927T0000Z-5501a-card-g3/irqsio/07JBD.txt) · [08JTX.txt](/tests/raw/20260927T0000Z-5501a-card-g3/irqsio/08JTX.txt) · [09JFF.txt](/tests/raw/20260927T0000Z-5501a-card-g3/irqsio/09JFF.txt) · [10SRG.txt](/tests/raw/20260927T0000Z-5501a-card-g3/irqsio/10SRG.txt) · [11STX.txt](/tests/raw/20260927T0000Z-5501a-card-g3/irqsio/11STX.txt) · [12JPD.txt](/tests/raw/20260927T0000Z-5501a-card-g3/irqsio/12JPD.txt) · [13JCF.txt](/tests/raw/20260927T0000Z-5501a-card-g3/irqsio/13JCF.txt) · [14IEX.txt](/tests/raw/20260927T0000Z-5501a-card-g3/irqsio/14IEX.txt) | ||
| + | |||
| + | 00RUN.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | 14 tests | ||
| + | A chain program, linked at 80100000 | ||
| + | Saved on the card in slot 2, from image 1 | ||
| + | COP0 at start: BPC 00000000 BDA 00000000 TAR 8001C060 DCIC 00000000 BadVaddr 00000480 BDAM 00000000 | ||
| + | BPCM 00000000 SR 40000000 Cause 00000020 EPC 8001CBCC PRId 00000002 | ||
| + | ``` | ||
| + | |||
| + | 01IMR.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 01 IMR I MASK READBACK | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | I_MASK as found: 0009 | ||
| + | sw FFFFFFFF, then lw 960507FF | ||
| + | sw FFFFFFFF, then lhu +0 07FF, lhu +2 3C03 | ||
| + | sw FFFFFFFF, then lbu +0..+3 FF 07 C6 30 | ||
| + | sw 0000F800 (bits 11-15), then lhu 0000 | ||
| + | sw 12345555, then lhu 0555 | ||
| + | sw 0, then lw 24840000 | ||
| + | Partial stores: baseline, source, op, then the low half read back | ||
| + | base 000 src AABBCCDD: sb+0=4DD sb+1=500 sb+2=000 sb+3=000 sh+0=4DD sh+2=000 sw=4DD | ||
| + | base 000 src FEDCBA98: sb+0=298 sb+1=000 sb+2=000 sb+3=000 sh+0=298 sh+2=000 sw=298 | ||
| + | base 7FF src AABBCCDD: sb+0=4DD sb+1=500 sb+2=000 sb+3=000 sh+0=4DD sh+2=000 sw=4DD | ||
| + | base 7FF src FEDCBA98: sb+0=298 sb+1=000 sb+2=000 sb+3=000 sh+0=298 sh+2=000 sw=298 | ||
| + | sw 2A5 then lw at once: 000002A5 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 02IST.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 02 IST I STAT ACK | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Raised by GP0 1Fh, DICR force, timers 0-2: I_STAT 007A (lw 3C03007A) | ||
| + | lhu +2 9067, lbu +0..+3 7A 00 A2 AF | ||
| + | sw FFFFFFFF: 007A | ||
| + | sw ~10h (ack timer 0): 006A | ||
| + | sw 0: 0000 | ||
| + | sw FFFFFFFF after 0 (can a write set a bit?): 0000 | ||
| + | With I_MASK 07FF: I_STAT 007A, I_MASK 07FF | ||
| + | Partial stores after raise_all: op=result (bits 0 and 2 may come and go) | ||
| + | src 00000000: sb+0=07A/000 sb+1=07A/000 sb+2=07A/000 sb+3=07A/000 sh+0=07A/000 sh+2=07A/000 sw=07A/000 | ||
| + | src FFFFFFFF: sb+0=07A/07A sb+1=07A/000 sb+2=07A/000 sb+3=07A/000 sh+0=07A/07A sh+2=07A/000 sw=07A/07A | ||
| + | src FFFFFFEF: sb+0=07A/06A sb+1=07A/000 sb+2=07A/000 sb+3=07A/000 sh+0=07A/06A sh+2=07A/000 sw=07A/06A | ||
| + | src 000000FF: sb+0=07A/07A sb+1=07A/000 sb+2=07A/000 sb+3=07A/000 sh+0=07A/07A sh+2=07A/000 sw=07A/07A | ||
| + | sb+1 src 000000FB: before 07A after 000 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 03IED.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 03 IED I STAT EDGES | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | DICR force on: I_STAT.3 1, DICR 80008000 | ||
| + | Ack I_STAT.3 with force still on: 0 | ||
| + | Force written 1 again: 0 | ||
| + | Force off: 0 | ||
| + | Force on again: 1 | ||
| + | GP0 1Fh: I_STAT.1 1 GPUSTAT.24 1 | ||
| + | Ack I_STAT.1, GP0 1Fh again with GPUSTAT.24 set: I_STAT.1 0 | ||
| + | GP1 02h: GPUSTAT.24 0, I_STAT.1 0 | ||
| + | GP0 1Fh after GP1 02h: I_STAT.1 1 | ||
| + | Timer 0 target 99 repeat pulse: I_STAT.4 set 990 times in 100000 cycles | ||
| + | Timer 0 target 99 repeat toggle: I_STAT.4 set 495 times in 100000 cycles | ||
| + | Toggle mode, bit 10 of 16 mode reads: 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 | ||
| + | Pulse mode, bit 10 of 16 mode reads: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| + | One-shot target 99, after acking the first: I_STAT.4 0, mode 0C18 | ||
| + | One-shot, target and FFFFh on, counter FFF0h: I_STAT.4 1 mode 1C30 | ||
| + | ... then 120000 cycles on (past target 30000): I_STAT.4 0 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 04IP2.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 04 IP2 CAUSE IP2 | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | SR 40000400 CAUSE 30000000 with interrupts off here | ||
| + | I_STAT.3 set, I_MASK 0: CAUSE 30000000 | ||
| + | I_MASK 8: CAUSE 30000400 | ||
| + | SR Im all 0 (SR 40000000): CAUSE 30000400 | ||
| + | I_MASK 0 again: CAUSE 30000000 | ||
| + | mtc0 CAUSE FFFFFFFF: 30000300; then 0: 30000000 | ||
| + | mtc0 CAUSE 00000400 with no IRQ: 30000000 | ||
| + | IP2 after sh I_MASK=8 (I_STAT.3 set), n nops: 0:0 1:0 2:1 3:1 4:1 6:1 | ||
| + | IP2 after sh I_MASK=8 (I_STAT.3 set), n nops: 0:0 1:0 2:1 3:1 4:1 6:1 | ||
| + | IP2 after sw I_STAT=0 (was set, I_MASK 8), n nops: 0:1 1:1 2:0 3:0 4:0 6:0 | ||
| + | IP2 after sw DICR force (I_MASK 8), n nops: 0:0 1:0 2:0 3:0 4:1 6:1 | ||
| + | I_STAT.3 after all that, acked: 0; CAUSE 30000000 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 05ILT.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 05 ILT IRQ LATENCY POLLED | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Poll loop period, 1000 turns: 15020 cycles | ||
| + | Counter at the turn that saw the IRQ, minus the target (targets 300-307): | ||
| + | T2 sysclk, I_STAT.6: 11 5 4 3 2 1 15 14 | ||
| + | T2 sysclk, CAUSE.IP2: 4 12 11 10 9 8 7 6 | ||
| + | T2 sysclk/8, I_STAT.6 (in 8s): 1 1 1 0 1 1 0 0 | ||
| + | T0 sysclk, I_STAT.4: 6 5 4 3 2 1 15 14 | ||
| + | T1 sysclk, I_STAT.5: 6 5 4 3 2 1 15 14 | ||
| + | T0 sysclk, CAUSE.IP2: 13 12 11 10 9 8 7 6 | ||
| + | T1 sysclk reset at VBlank, value when I_STAT.0 seen: 43476 57859 57861 57866 57863 57869 57866 57857 | ||
| + | T1 hblank reset at VBlank, value when I_STAT.0 seen: 237 237 237 237 237 237 237 237 | ||
| + | T1 hblank free, hblanks between VBlank IRQs: 263 263 263 263 | ||
| + | OTC 16 words: CHCR.24 clear at 55, I_STAT.3 at 55, DICR 31-24 C0 | ||
| + | OTC 16 words: CHCR.24 clear at 41, I_STAT.3 at 41, DICR 31-24 C0 | ||
| + | OTC 16 words: CHCR.24 clear at 31, I_STAT.3 at 31, DICR 31-24 C0 | ||
| + | OTC 64 words: CHCR.24 clear at 11, I_STAT.3 at 11, DICR 31-24 C0 | ||
| + | OTC 64 words: CHCR.24 clear at 79, I_STAT.3 at 79, DICR 31-24 C0 | ||
| + | OTC 64 words: CHCR.24 clear at 79, I_STAT.3 at 79, DICR 31-24 C0 | ||
| + | OTC 256 words: CHCR.24 clear at 286, I_STAT.3 at 286, DICR 31-24 C0 | ||
| + | OTC 256 words: CHCR.24 clear at 286, I_STAT.3 at 286, DICR 31-24 C0 | ||
| + | OTC 256 words: CHCR.24 clear at 286, I_STAT.3 at 286, DICR 31-24 C0 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 06JRG.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 06 JRG JOY REGISTERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | As found: STAT 00003805 MODE 000D CTRL 0000 BAUD 0088 | ||
| + | lw 1F801048 0000000D, lw 1F80104C 00880000, lhu 1F80104C 0000, lhu 1F801046 0001 | ||
| + | lbu STAT +0..+3 05 90 01 00 | ||
| + | Empty RX: lbu 47, lhu 4747, lw 47474747 | ||
| + | MODE FFFF: 013F | ||
| + | MODE 0: 0000 | ||
| + | BAUD FFFF: FFFF | ||
| + | BAUD 1235: 1235 | ||
| + | CTRL one bit at a time (13 never): read, STAT, I_STAT.7 | ||
| + | bit 0: CTRL 0001 STAT 0005 I7 0 | ||
| + | bit 1: CTRL 0002 STAT 0005 I7 0 | ||
| + | bit 2: CTRL 0004 STAT 0005 I7 0 | ||
| + | bit 3: CTRL 0008 STAT 0007 I7 0 | ||
| + | bit 5: CTRL 0020 STAT 0007 I7 0 | ||
| + | bit 7: CTRL 0000 STAT 0007 I7 0 | ||
| + | bit 8: CTRL 0100 STAT 0007 I7 0 | ||
| + | bit 9: CTRL 0200 STAT 0007 I7 0 | ||
| + | bit 10: CTRL 0400 STAT 0207 I7 1 | ||
| + | bit 11: CTRL 0800 STAT 0207 I7 1 | ||
| + | bit 12: CTRL 1000 STAT 0007 I7 0 | ||
| + | bit 14: CTRL 0000 STAT 0007 I7 0 | ||
| + | bit 15: CTRL 0000 STAT 0007 I7 0 | ||
| + | CTRL DFAF: 1F2F, STAT 0207 | ||
| + | CTRL 0410 (ack with TX IRQ on): 0400, STAT 0207 | ||
| + | Before reset: MODE 013E BAUD 1234 CTRL 0828 STAT 0207 | ||
| + | CTRL 0040: MODE 0000 BAUD 0000 CTRL 0000 STAT 00000005 | ||
| + | sw 0000000D to 1F801048: MODE 000D CTRL 0000 | ||
| + | sb 44 to BAUD: 0044 | ||
| + | sb 01 to BAUD+1: 0100 | ||
| + | Left: MODE 000D BAUD 0088 CTRL 0000 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 07JBD.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 07 JBD JOY SIO BAUD TIMER | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | JOY_STAT >> 11, 8 lw in a row, after sh BAUD in the same run | ||
| + | MODE 000D BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 005) | ||
| + | MODE 000D BAUD 0001: 0 0 0 0 0 0 0 0 (low 005) | ||
| + | MODE 000D BAUD 0002: 1 1 1 1 1 1 1 1 (low 005) | ||
| + | MODE 000D BAUD 1000: 800 7FC 7F8 7E9 7E5 7E1 7DD 7D2 (low 005) | ||
| + | MODE 000D BAUD FFFF: 7FFF 7FFB 7FF7 7FEC 7FE8 7FE4 7FE0 7FD5 (low 005) | ||
| + | MODE 000E BAUD 0088: 440 43C 438 42D 429 425 421 416 (low 005) | ||
| + | MODE 000E BAUD 0001: 8 4 8 5 1 5 1 6 (low 005) | ||
| + | MODE 000E BAUD 0002: 10 C 8 D 9 5 1 6 (low 005) | ||
| + | MODE 000E BAUD 1000: 8000 7FFC 7FF8 7FED 7FE9 7FE5 7FE1 7FD6 (low 005) | ||
| + | MODE 000E BAUD FFFF: 7FFF8 7FFF4 7FFF0 7FFE5 7FFE1 7FFDD 7FFD9 7FFCE (low 005) | ||
| + | MODE 000F BAUD 0088: 1100 10FC 10F8 10ED 10E9 10E5 10E1 10D6 (low 005) | ||
| + | MODE 000F BAUD 0001: 20 1C 18 D 9 5 1 16 (low 005) | ||
| + | MODE 000F BAUD 0002: 40 3C 38 2D 29 25 21 16 (low 005) | ||
| + | MODE 000F BAUD 1000: 20000 1FFFC 1FFF8 1FFED 1FFE9 1FFE5 1FFE1 1FFD6 (low 005) | ||
| + | MODE 000F BAUD FFFF: 1FFFE0 1FFFDC 1FFFD8 1FFFCD 1FFFC9 1FFFC5 1FFFC1 1FFFB6 (low 005) | ||
| + | MODE 000C BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 005) | ||
| + | MODE 000C BAUD 0001: 0 0 0 0 0 0 0 0 (low 005) | ||
| + | MODE 000C BAUD 0002: 1 1 1 1 1 1 1 1 (low 005) | ||
| + | MODE 000C BAUD 1000: 800 7FC 7F8 7ED 7E9 7E5 7E1 7D6 (low 005) | ||
| + | MODE 000C BAUD FFFF: 7FFF 7FFB 7FF7 7FEC 7FE8 7FE4 7FE0 7FD5 (low 005) | ||
| + | No write, MODE 000D BAUD 0088: 2B 1E 1A 16 12 7 3 43 (low 005) | ||
| + | No write, MODE 000E BAUD 1000: 7FA9 7F9E 7F9A 7F96 7F92 7F87 7F83 7F7F (low 005) | ||
| + | MODE 000E->000F write, BAUD 1000: timer before 31B7 after 31A8 | ||
| + | SIO_STAT >> 11 (SIO1 as found MODE 0000 BAUD 0000) | ||
| + | MODE 004D BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 185) | ||
| + | MODE 004D BAUD 0002: 1 1 1 1 1 1 1 1 (low 185) | ||
| + | MODE 004D BAUD FFFF: 7FFF 7FFB 7FF7 7FEC 7FE8 7FE4 7FE0 7FD5 (low 185) | ||
| + | MODE 004E BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 185) | ||
| + | MODE 004E BAUD 0002: 1 1 1 1 1 1 1 1 (low 185) | ||
| + | MODE 004E BAUD FFFF: 7FFF 7FFB 7FF7 7FEC 7FE8 7FE4 7FE0 7FD5 (low 185) | ||
| + | MODE 004F BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 185) | ||
| + | MODE 004F BAUD 0002: 1 1 1 1 1 1 1 1 (low 185) | ||
| + | MODE 004F BAUD FFFF: 7FFF 7FFB 7FF7 7FE7 7FE3 7FDF 7FDB 7FD0 (low 185) | ||
| + | MODE 004C BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 185) | ||
| + | MODE 004C BAUD 0002: 1 1 1 1 1 1 1 1 (low 185) | ||
| + | MODE 004C BAUD FFFF: 7FFF 7FFB 7FF7 7FEC 7FE8 7FE4 7FE0 7FD5 (low 185) | ||
| + | No write, MODE 004E BAUD 00DC: 10 5 1 6B 67 5C 58 54 (low 185) | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 08JTX.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 08 JTX JOY BYTE TIMES | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Each row: stopwatch:STAT&3FF at every change, from the write to JOY_DATA | ||
| + | TXEN only (M000D B0088 C0001): | ||
| + | 127:1 1219:5 | ||
| + | 77:0 206:1 1195:5 | ||
| + | 82:0 187:1 1231:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | TXEN RXEN (M000D B0088 C0005): | ||
| + | 77:0 182:1 952:3 1251:7 | ||
| + | 77:0 201:1 974:3 1217:7 | ||
| + | 77:0 184:1 960:3 1253:7 | ||
| + | then CTRL 0001, rx FF (1) | ||
| + | TXEN, slot 1 selected (M000D B0088 C0003): | ||
| + | 77:0 187:1 1225:5 1359:7 | ||
| + | 77:0 206:1 1246:5 1383:7 | ||
| + | 77:0 182:1 1225:5 1363:7 | ||
| + | then CTRL 0003, rx FF (1) | ||
| + | BAUD 0044 (M000D B0044 C0001): | ||
| + | 77:1 611:5 | ||
| + | 82:1 635:5 | ||
| + | 82:1 617:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | BAUD 0022 (M000D B0022 C0001): | ||
| + | 81:1 294:5 | ||
| + | 77:1 317:5 | ||
| + | 77:1 293:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | BAUD 0110 (M000D B0110 C0001): | ||
| + | 77:0 182:1 2347:5 | ||
| + | 77:0 418:1 2577:5 | ||
| + | 77:0 185:1 2341:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | BAUD 0089 (M000D B0089 C0001): | ||
| + | 87:0 192:1 1230:5 | ||
| + | 77:0 206:1 1244:5 | ||
| + | 77:0 185:1 1275:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | MUL16 (M000E B0088 C0001): | ||
| + | 82:0 1788:1 19208:5 | ||
| + | 77:0 1750:1 19167:5 | ||
| + | 77:0 1780:1 19188:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | factor 0 (M000C B0088 C0001): | ||
| + | 82:0 187:1 1223:5 | ||
| + | 77:0 201:1 1194:5 | ||
| + | 77:0 188:1 1227:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | 5 bits (M0001 B0088 C0001): | ||
| + | 82:0 187:1 851:5 | ||
| + | 77:0 201:1 820:5 | ||
| + | 77:0 184:1 850:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | 8 bits parity (M001D B0088 C0005): | ||
| + | 81:0 186:1 1124:3 1364:7 | ||
| + | 82:0 206:1 1091:3 1336:7 | ||
| + | 77:0 185:1 1122:3 1367:7 | ||
| + | then CTRL 0001, rx FF (1) | ||
| + | CLK inverted (M010D B0088 C0001): | ||
| + | 74:0 185:1 1230:5 | ||
| + | 87:0 211:1 1202:5 | ||
| + | 83:0 188:1 1232:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | Poll turn: 73 turns in 4000 cycles | ||
| + | TXEN 0 at the write: 93:4 | ||
| + | then TXEN 1: 93:0 219:1 1264:5 | ||
| + | TXEN cleared after the write: 98:0 203:1 1241:5 | ||
| + | Two writes in a row: 93:0 198:1 977:3 1220:7 | ||
| + | bytes in RX after: 1 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 09JFF.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 09 JFF JOY FIFO AND IRQS | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | 10 bytes with RXEN, none read: STAT 0007 | ||
| + | lw DATA FFFFFFFF (1st and 3 previews), STAT after 0007 | ||
| + | lbu until STAT.1 clears: FF FF FF FF (4), then 3 more: 00 00 00 | ||
| + | 3 bytes, lhu DATA FFFF then STAT 0007, 2 left | ||
| + | TX IRQ CTRL 0401: before a byte STAT 0205 I7 1; 129:10200 294:10201 1316:10205 | ||
| + | acked, cond. still true: STAT 0205 I7 1 | ||
| + | RX IRQ 1 byte CTRL 0805: before a byte STAT 0005 I7 0; 91:10203 1243:10207 | ||
| + | acked, cond. still true: STAT 0207 I7 1 | ||
| + | RX IRQ 2 bytes CTRL 0905: before a byte STAT 0005 I7 0; 86:10203 1238:10207 | ||
| + | 2nd byte: 93:10203 1237:10207 | ||
| + | acked, cond. still true: STAT 0207 I7 1 | ||
| + | ACK IRQ CTRL 1001: before a byte STAT 0005 I7 0; 86:0 247:1 1277:5 | ||
| + | acked, cond. still true: STAT 0005 I7 0 | ||
| + | TX+RX IRQ CTRL 0C01: before a byte STAT 0205 I7 1; 86:10201 1238:10205 | ||
| + | acked, cond. still true: STAT 0205 I7 1 | ||
| + | RX IRQ 8 bytes CTRL 0B05: before a byte STAT 0005 I7 0; 91:10203 1243:10207 | ||
| + | acked, cond. still true: STAT 0207 I7 1 | ||
| + | TX IRQ held, I_STAT.7 acked alone: I7 0 STAT 0205 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 10SRG.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 10 SRG SIO REGISTERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | As found: STAT 00000185 MODE 0000 CTRL 0000 MISC DFDD BAUD 0000 | ||
| + | lw 1F801058 00000000, lw 1F80105C 0000DFDD, lhu 1F801052 FFFF, lhu 1F801056 0000 | ||
| + | Empty RX: lbu FE lhu FFFF lw FFFF7FFF | ||
| + | MODE FFFF: 00FF | ||
| + | MODE 0: 0000 | ||
| + | BAUD FFFF: FFFF | ||
| + | BAUD 1235: 1235 | ||
| + | CTRL one bit at a time, MODE 0 then MODE 004E: CTRL, STAT, I_STAT.8 | ||
| + | M0 bit 0: 0001 0185 0 | ||
| + | M0 bit 1: 0002 0185 0 | ||
| + | M0 bit 2: 0004 0185 0 | ||
| + | M0 bit 3: 0008 0185 0 | ||
| + | M0 bit 5: 0020 0185 0 | ||
| + | M0 bit 7: 0000 0185 0 | ||
| + | M0 bit 8: 0100 0185 0 | ||
| + | M0 bit 9: 0200 0185 0 | ||
| + | M0 bit 10: 0400 0385 1 | ||
| + | M0 bit 11: 0800 0185 0 | ||
| + | M0 bit 12: 1000 0385 1 | ||
| + | M0 bit 13: 0000 0185 0 | ||
| + | M0 bit 14: 0000 0185 0 | ||
| + | M0 bit 15: 0000 0185 0 | ||
| + | M1 bit 0: 0001 0185 0 | ||
| + | M1 bit 1: 0002 0185 0 | ||
| + | M1 bit 2: 0004 0185 0 | ||
| + | M1 bit 3: 0008 0185 0 | ||
| + | M1 bit 5: 0020 0185 0 | ||
| + | M1 bit 7: 0080 0185 0 | ||
| + | M1 bit 8: 0100 0185 0 | ||
| + | M1 bit 9: 0200 0185 0 | ||
| + | M1 bit 10: 0400 0385 1 | ||
| + | M1 bit 11: 0800 0185 0 | ||
| + | M1 bit 12: 1000 0385 1 | ||
| + | M1 bit 13: 0000 0185 0 | ||
| + | M1 bit 14: 0000 0185 0 | ||
| + | M1 bit 15: 0000 0185 0 | ||
| + | MODE 004E CTRL FFAF: 1FAF | ||
| + | MISC write, read with MODE 004E (8 bits) and 0042 (5 bits): | ||
| + | 1234: 3412 D4D2, read again D4D2 | ||
| + | FFFF: FFFF DFDF, read again DFDF | ||
| + | 0000: 0000 C0C0, read again C0C0 | ||
| + | A5C3: C3A5 C3C5, read again C3C5 | ||
| + | MISC 1234 then 5000 cycles: 3412 | ||
| + | Before reset: MODE 004E CTRL 0023 MISC 7856 BAUD 00DC STAT 0385 | ||
| + | CTRL 0040: MODE 0000 CTRL 0000 MISC 7856 BAUD 0000 STAT 0000E185 | ||
| + | Put back: MODE 0000 CTRL 0000 BAUD 0000 (MISC left 7856) | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 11STX.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 11 STX SIO TRANSFERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | MODE 004D (8N1 MUL1) BAUD 0088; stopwatch:STAT&3FF (+I_STAT.7,8 at bits 16,17) | ||
| + | TXEN C0001: before STAT 0185 I8 0; write 55h: 144:180 304:181 1593:185 | ||
| + | RX bytes 0, CTRL 0001 | ||
| + | TXEN DTR RTS C0023: before STAT 0185 I8 0; write 55h: 120:181 1464:185 | ||
| + | RX bytes 0, CTRL 0023 | ||
| + | +TX IRQ C0423: before STAT 0385 I8 1; write 55h: 110:20381 1511:20385 | ||
| + | RX bytes 0, CTRL 0423 | ||
| + | TXEN RXEN DTR RTS C0027: before STAT 0185 I8 0; write 55h: 115:180 270:181 1547:185 | ||
| + | RX bytes 0, CTRL 0027 | ||
| + | +RX IRQ C0827: before STAT 0185 I8 0; write 55h: 120:181 1524:185 | ||
| + | RX bytes 0, CTRL 0827 | ||
| + | +DSR IRQ C1027: before STAT 0385 I8 1; write 55h: 115:20381 1466:20385 | ||
| + | RX bytes 0, CTRL 1027 | ||
| + | RXEN only, 20000 cycles: 102:20185 | ||
| + | RX bytes 0 | ||
| + | Write with TXEN 0, TXEN 1 later: 1114:180 1251:181 2553:185 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 12JPD.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 12 JPD PAD IN SLOT 1 | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Slot 1, 01 42 00 00 00..., every change of JOY_STAT (+I_STAT.7 at bit 16): | ||
| + | 01->FF 145:0 290:1 1321:5 1473:7 1750:10287 1842:10207 | ||
| + | 42->41 97:0 232:1 1263:5 1355:7 1693:10287 1783:10207 | ||
| + | 00->5A 92:0 232:1 1331:5 1421:7 1759:10287 1849:10207 | ||
| + | 00->FF 93:0 228:1 1314:5 1404:7 1743:10287 1843:10207 | ||
| + | 00->FF 92:0 232:1 1269:5 1421:7 | ||
| + | send 01 42 00 00 00 00 00 00 00 | ||
| + | got FF 41 5A FF FF (4 acked) | ||
| + | /ACK at 1750 1693 1759 1743; low for 92 90 90 100 | ||
| + | 8 more reads (/ACK times per byte): | ||
| + | 4: FF 41 5A FF FF | 1671 1681 1838 1761 | ||
| + | 4: FF 41 5A FF FF | 1664 1673 1618 1730 | ||
| + | 4: FF 41 5A FF FF | 1661 1675 1672 1741 | ||
| + | 4: FF 41 5A FF FF | 1671 1678 1605 1740 | ||
| + | 4: FF 41 5A FF FF | 1664 1666 1618 1730 | ||
| + | 4: FF 41 5A FF FF | 1661 1675 1672 1741 | ||
| + | 4: FF 41 5A FF FF | 1671 1678 1605 1740 | ||
| + | 4: FF 41 5A FF FF | 1664 1666 1618 1730 | ||
| + | 01h, tight loop: /ACK after, low for: 1680/106 1713/96 1702/107 1713/96 1702/96 1702/107 1702/107 1702/107 | ||
| + | Ack while /ACK low (seen at 1694): STAT then 0287; after /ACK high 0207; acked again 0007 | ||
| + | 01h with CTRL 0003 (no ACK IRQ): 103:0 217:1 1305:5 1457:7 1734:87 1834:7 | ||
| + | 01h at once after selecting: 93:0 207:1 1294:5 1448:7 1786:10287 1876:10207 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 13JCF.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 13 JCF PAD CONFIG MODE | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Slot 1 01 42 first:send 01 42 00 00 00 00 00 00 00 | ||
| + | got FF 41 5A FF FF (4 acked) | ||
| + | /ACK at 1749 1746 1675 1790; low for 100 90 90 90 | ||
| + | send 01 43 00 01 00 00 00 00 00 | ||
| + | got FF 41 5A 01 (3 acked) | ||
| + | /ACK at 1661 1679 1790; low for 90 90 90 | ||
| + | send 01 45 00 00 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1671; low for 90 | ||
| + | send 01 46 00 00 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1668; low for 100 | ||
| + | send 01 46 00 01 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1668; low for 90 | ||
| + | send 01 47 00 00 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1668; low for 100 | ||
| + | send 01 4C 00 00 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1668; low for 90 | ||
| + | send 01 4C 00 01 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1668; low for 100 | ||
| + | send 01 48 00 00 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1668; low for 90 | ||
| + | send 01 42 00 00 00 00 00 00 00 | ||
| + | got FF 41 5A FF FF (4 acked) | ||
| + | /ACK at 1668 1678 1734 1675; low for 100 90 90 90 | ||
| + | send 01 43 00 00 00 00 00 00 00 | ||
| + | got FF 41 5A 01 (3 acked) | ||
| + | /ACK at 1676 1667 1667; low for 90 152 90 | ||
| + | send 01 42 00 00 00 00 00 00 00 | ||
| + | got FF 41 5A FF FF (4 acked) | ||
| + | /ACK at 1669 1675 1610 1741; low for 92 90 152 90 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 14IEX.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 14 IEX IRQ ENTRY | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Kernel's 80000080h: 3C1A0000 275A0C80 03400008 00000000 | ||
| + | SR as found 40000401. Rows: instructions after the trigger @ timer 2 in the handler | ||
| + | mtc0 SR IEc 0->1, IRQ pending: 2@64 2@54 2@54 2@60 2@54 2@54 | ||
| + | last CAUSE 00000000 SR 40000404 I_STAT 0009 | ||
| + | mtc0 SR Im2 0->1, IEc 1, IRQ pending: 1@75 none none none none none | ||
| + | sh I_MASK 8, I_STAT.3 set, IEc 1: none none none none none none | ||
| + | sw DICR force, I_MASK 8, IEc 1: 8@60 8@59 8@64 8@59 8@59 8@59 | ||
| + | T2 target 100-107: 100@135 101@141 102@146 99@143 104@144 105@145 106@146 107@147 | ||
| + | T2 target 150-157: 150@190 151@191 152@192 153@193 154@194 155@195 156@200 157@197 | ||
| + | last CAUSE 00000000 SR 40000404 I_STAT 0049 | ||
| + | T2 into a 3 instruction loop, target 100-115: EPC word (from the mode write) and BD | ||
| + | 2/0 2/1 1/0 2/0 2/1 1/0 2/0 2/1 1/0 2/0 2/1 1/0 2/0 2/1 1/0 2/0 | ||
| + | Kernel's vector back: 3C1A0000 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | ### 28 September 2026 card-h | ||
| + | |||
| + | Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/00RUN.txt) · [01IMR.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/01IMR.txt) · [02IST.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/02IST.txt) · [03IED.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/03IED.txt) · [04IP2.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/04IP2.txt) · [05ILT.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/05ILT.txt) · [06JRG.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/06JRG.txt) · [07JBD.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/07JBD.txt) · [08JTX.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/08JTX.txt) · [09JFF.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/09JFF.txt) · [10SRG.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/10SRG.txt) · [11STX.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/11STX.txt) · [12JPD.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/12JPD.txt) · [13JCF.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/13JCF.txt) · [14IEX.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/14IEX.txt) | ||
| + | |||
| + | 00RUN.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | 14 tests | ||
| + | A chain program, linked at 80100000 | ||
| + | Saved on the card in slot 2, from image 1 | ||
| + | COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 00000480 BDAM 00000000 | ||
| + | BPCM 00000000 SR 40000000 Cause 00000020 EPC 8001CBCC PRId 00000002 | ||
| + | ``` | ||
| + | |||
| + | 01IMR.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 01 IMR I MASK READBACK | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | I_MASK as found: 0009 | ||
| + | sw FFFFFFFF, then lw 960507FF | ||
| + | sw FFFFFFFF, then lhu +0 07FF, lhu +2 3C03 | ||
| + | sw FFFFFFFF, then lbu +0..+3 FF 07 C6 30 | ||
| + | sw 0000F800 (bits 11-15), then lhu 0000 | ||
| + | sw 12345555, then lhu 0555 | ||
| + | sw 0, then lw 24840000 | ||
| + | Partial stores: baseline, source, op, then the low half read back | ||
| + | base 000 src AABBCCDD: sb+0=4DD sb+1=500 sb+2=000 sb+3=000 sh+0=4DD sh+2=000 sw=4DD | ||
| + | base 000 src FEDCBA98: sb+0=298 sb+1=000 sb+2=000 sb+3=000 sh+0=298 sh+2=000 sw=298 | ||
| + | base 7FF src AABBCCDD: sb+0=4DD sb+1=500 sb+2=000 sb+3=000 sh+0=4DD sh+2=000 sw=4DD | ||
| + | base 7FF src FEDCBA98: sb+0=298 sb+1=000 sb+2=000 sb+3=000 sh+0=298 sh+2=000 sw=298 | ||
| + | sw 2A5 then lw at once: 000002A5 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 02IST.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 02 IST I STAT ACK | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Raised by GP0 1Fh, DICR force, timers 0-2: I_STAT 007A (lw 3C03007A) | ||
| + | lhu +2 9067, lbu +0..+3 7A 00 A2 AF | ||
| + | sw FFFFFFFF: 007A | ||
| + | sw ~10h (ack timer 0): 006A | ||
| + | sw 0: 0000 | ||
| + | sw FFFFFFFF after 0 (can a write set a bit?): 0000 | ||
| + | With I_MASK 07FF: I_STAT 007A, I_MASK 07FF | ||
| + | Partial stores after raise_all: op=result (bits 0 and 2 may come and go) | ||
| + | src 00000000: sb+0=07A/000 sb+1=07A/000 sb+2=07A/000 sb+3=07A/000 sh+0=07A/000 sh+2=07A/000 sw=07A/000 | ||
| + | src FFFFFFFF: sb+0=07A/07A sb+1=07A/000 sb+2=07A/000 sb+3=07A/000 sh+0=07A/07A sh+2=07A/000 sw=07A/07A | ||
| + | src FFFFFFEF: sb+0=07A/06A sb+1=07A/000 sb+2=07A/000 sb+3=07A/000 sh+0=07A/06A sh+2=07A/000 sw=07A/06A | ||
| + | src 000000FF: sb+0=07A/07A sb+1=07A/000 sb+2=07A/000 sb+3=07A/000 sh+0=07A/07A sh+2=07A/000 sw=07A/07A | ||
| + | sb+1 src 000000FB: before 07A after 000 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 03IED.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 03 IED I STAT EDGES | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | DICR force on: I_STAT.3 1, DICR 80008000 | ||
| + | Ack I_STAT.3 with force still on: 0 | ||
| + | Force written 1 again: 0 | ||
| + | Force off: 0 | ||
| + | Force on again: 1 | ||
| + | GP0 1Fh: I_STAT.1 1 GPUSTAT.24 1 | ||
| + | Ack I_STAT.1, GP0 1Fh again with GPUSTAT.24 set: I_STAT.1 0 | ||
| + | GP1 02h: GPUSTAT.24 0, I_STAT.1 0 | ||
| + | GP0 1Fh after GP1 02h: I_STAT.1 1 | ||
| + | Timer 0 target 99 repeat pulse: I_STAT.4 set 990 times in 100000 cycles | ||
| + | Timer 0 target 99 repeat toggle: I_STAT.4 set 495 times in 100000 cycles | ||
| + | Toggle mode, bit 10 of 16 mode reads: 0 0 0 1 1 1 0 0 0 1 1 0 0 0 1 1 | ||
| + | Pulse mode, bit 10 of 16 mode reads: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| + | One-shot target 99, after acking the first: I_STAT.4 0, mode 0C18 | ||
| + | One-shot, target and FFFFh on, counter FFF0h: I_STAT.4 1 mode 1C30 | ||
| + | ... then 120000 cycles on (past target 30000): I_STAT.4 0 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 04IP2.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 04 IP2 CAUSE IP2 | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | SR 40000400 CAUSE 00000000 with interrupts off here | ||
| + | I_STAT.3 set, I_MASK 0: CAUSE 00000000 | ||
| + | I_MASK 8: CAUSE 00000400 | ||
| + | SR Im all 0 (SR 40000000): CAUSE 00000400 | ||
| + | I_MASK 0 again: CAUSE 00000000 | ||
| + | mtc0 CAUSE FFFFFFFF: 00000300; then 0: 00000000 | ||
| + | mtc0 CAUSE 00000400 with no IRQ: 00000000 | ||
| + | IP2 after sh I_MASK=8 (I_STAT.3 set), n nops: 0:0 1:0 2:1 3:1 4:1 6:1 | ||
| + | IP2 after sh I_MASK=8 (I_STAT.3 set), n nops: 0:0 1:0 2:1 3:1 4:1 6:1 | ||
| + | IP2 after sw I_STAT=0 (was set, I_MASK 8), n nops: 0:1 1:1 2:0 3:0 4:0 6:0 | ||
| + | IP2 after sw DICR force (I_MASK 8), n nops: 0:0 1:0 2:0 3:0 4:1 6:1 | ||
| + | I_STAT.3 after all that, acked: 0; CAUSE 00000000 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 05ILT.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 05 ILT IRQ LATENCY POLLED | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Poll loop period, 1000 turns: 15020 cycles | ||
| + | Counter at the turn that saw the IRQ, minus the target (targets 300-307): | ||
| + | T2 sysclk, I_STAT.6: 11 5 4 3 2 1 15 14 | ||
| + | T2 sysclk, CAUSE.IP2: 4 12 11 10 9 8 7 6 | ||
| + | T2 sysclk/8, I_STAT.6 (in 8s): 1 0 0 0 0 0 1 1 | ||
| + | T0 sysclk, I_STAT.4: 6 5 4 3 2 1 15 14 | ||
| + | T1 sysclk, I_STAT.5: 6 5 4 3 2 1 15 14 | ||
| + | T0 sysclk, CAUSE.IP2: 13 12 11 10 9 8 7 6 | ||
| + | T1 sysclk reset at VBlank, value when I_STAT.0 seen: 43466 57856 57869 57856 57869 57861 57858 57868 | ||
| + | T1 hblank reset at VBlank, value when I_STAT.0 seen: 237 237 237 237 237 237 237 237 | ||
| + | T1 hblank free, hblanks between VBlank IRQs: 263 263 263 263 | ||
| + | OTC 16 words: CHCR.24 clear at 55, I_STAT.3 at 55, DICR 31-24 C0 | ||
| + | OTC 16 words: CHCR.24 clear at 31, I_STAT.3 at 31, DICR 31-24 C0 | ||
| + | OTC 16 words: CHCR.24 clear at 31, I_STAT.3 at 31, DICR 31-24 C0 | ||
| + | OTC 64 words: CHCR.24 clear at 79, I_STAT.3 at 79, DICR 31-24 C0 | ||
| + | OTC 64 words: CHCR.24 clear at 89, I_STAT.3 at 89, DICR 31-24 C0 | ||
| + | OTC 64 words: CHCR.24 clear at 89, I_STAT.3 at 89, DICR 31-24 C0 | ||
| + | OTC 256 words: CHCR.24 clear at 286, I_STAT.3 at 286, DICR 31-24 C0 | ||
| + | OTC 256 words: CHCR.24 clear at 286, I_STAT.3 at 286, DICR 31-24 C0 | ||
| + | OTC 256 words: CHCR.24 clear at 286, I_STAT.3 at 286, DICR 31-24 C0 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 06JRG.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 06 JRG JOY REGISTERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | As found: STAT 00010005 MODE 000D CTRL 0000 BAUD 0088 | ||
| + | lw 1F801048 0000000D, lw 1F80104C 00880000, lhu 1F80104C 0000, lhu 1F801046 0000 | ||
| + | lbu STAT +0..+3 05 90 01 00 | ||
| + | Empty RX: lbu 47, lhu 4747, lw 47474747 | ||
| + | MODE FFFF: 013F | ||
| + | MODE 0: 0000 | ||
| + | BAUD FFFF: FFFF | ||
| + | BAUD 1235: 1235 | ||
| + | CTRL one bit at a time (13 never): read, STAT, I_STAT.7 | ||
| + | bit 0: CTRL 0001 STAT 0005 I7 0 | ||
| + | bit 1: CTRL 0002 STAT 0005 I7 0 | ||
| + | bit 2: CTRL 0004 STAT 0005 I7 0 | ||
| + | bit 3: CTRL 0008 STAT 0007 I7 0 | ||
| + | bit 5: CTRL 0020 STAT 0007 I7 0 | ||
| + | bit 7: CTRL 0000 STAT 0007 I7 0 | ||
| + | bit 8: CTRL 0100 STAT 0007 I7 0 | ||
| + | bit 9: CTRL 0200 STAT 0007 I7 0 | ||
| + | bit 10: CTRL 0400 STAT 0207 I7 1 | ||
| + | bit 11: CTRL 0800 STAT 0207 I7 1 | ||
| + | bit 12: CTRL 1000 STAT 0007 I7 0 | ||
| + | bit 14: CTRL 0000 STAT 0007 I7 0 | ||
| + | bit 15: CTRL 0000 STAT 0007 I7 0 | ||
| + | CTRL DFAF: 1F2F, STAT 0207 | ||
| + | CTRL 0410 (ack with TX IRQ on): 0400, STAT 0207 | ||
| + | Before reset: MODE 013E BAUD 1234 CTRL 0828 STAT 0207 | ||
| + | CTRL 0040: MODE 0000 BAUD 0000 CTRL 0000 STAT 00000005 | ||
| + | sw 0000000D to 1F801048: MODE 000D CTRL 0000 | ||
| + | sb 44 to BAUD: 0044 | ||
| + | sb 01 to BAUD+1: 0100 | ||
| + | Left: MODE 000D BAUD 0088 CTRL 0000 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 07JBD.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 07 JBD JOY SIO BAUD TIMER | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | JOY_STAT >> 11, 8 lw in a row, after sh BAUD in the same run | ||
| + | MODE 000D BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 005) | ||
| + | MODE 000D BAUD 0001: 0 0 0 0 0 0 0 0 (low 005) | ||
| + | MODE 000D BAUD 0002: 1 1 1 1 1 1 1 1 (low 005) | ||
| + | MODE 000D BAUD 1000: 800 7FC 7F8 7ED 7E9 7E5 7E1 7D6 (low 005) | ||
| + | MODE 000D BAUD FFFF: 7FFF 7FFB 7FF7 7FEC 7FE8 7FE4 7FE0 7FD5 (low 005) | ||
| + | MODE 000E BAUD 0088: 440 43C 438 42D 429 425 421 416 (low 005) | ||
| + | MODE 000E BAUD 0001: 8 4 8 5 1 5 1 6 (low 005) | ||
| + | MODE 000E BAUD 0002: 10 C 8 8 4 10 C 1 (low 005) | ||
| + | MODE 000E BAUD 1000: 8000 7FFC 7FF8 7FED 7FE9 7FE5 7FE1 7FD6 (low 005) | ||
| + | MODE 000E BAUD FFFF: 7FFF8 7FFF4 7FFF0 7FFE5 7FFE1 7FFDD 7FFD9 7FFCE (low 005) | ||
| + | MODE 000F BAUD 0088: 1100 10FC 10F8 10ED 10E9 10E5 10E1 10D6 (low 005) | ||
| + | MODE 000F BAUD 0001: 20 1C 18 D 9 5 1 16 (low 005) | ||
| + | MODE 000F BAUD 0002: 40 3C 38 2D 29 25 21 16 (low 005) | ||
| + | MODE 000F BAUD 1000: 20000 1FFFC 1FFF8 1FFE9 1FFE5 1FFE1 1FFDD 1FFD2 (low 005) | ||
| + | MODE 000F BAUD FFFF: 1FFFE0 1FFFDC 1FFFD8 1FFFCD 1FFFC9 1FFFC5 1FFFC1 1FFFB6 (low 005) | ||
| + | MODE 000C BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 005) | ||
| + | MODE 000C BAUD 0001: 0 0 0 0 0 0 0 0 (low 005) | ||
| + | MODE 000C BAUD 0002: 1 1 1 1 1 1 1 1 (low 005) | ||
| + | MODE 000C BAUD 1000: 800 7FC 7F8 7E9 7E5 7E1 7DD 7D2 (low 005) | ||
| + | MODE 000C BAUD FFFF: 7FFF 7FFB 7FF7 7FEC 7FE8 7FE4 7FE0 7FD5 (low 005) | ||
| + | No write, MODE 000D BAUD 0088: 25 1A 16 12 E 3 43 3F (low 005) | ||
| + | No write, MODE 000E BAUD 1000: 7FA9 7F9E 7F9A 7F96 7F92 7F87 7F83 7F7F (low 005) | ||
| + | MODE 000E->000F write, BAUD 1000: timer before 31B7 after 31A8 | ||
| + | SIO_STAT >> 11 (SIO1 as found MODE 0000 BAUD 0000) | ||
| + | MODE 004D BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 185) | ||
| + | MODE 004D BAUD 0002: 1 1 1 1 1 1 1 1 (low 185) | ||
| + | MODE 004D BAUD FFFF: 7FFF 7FFB 7FF7 7FEC 7FE8 7FE4 7FE0 7FD5 (low 185) | ||
| + | MODE 004E BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 185) | ||
| + | MODE 004E BAUD 0002: 1 1 1 1 1 1 1 1 (low 185) | ||
| + | MODE 004E BAUD FFFF: 7FFF 7FFB 7FF7 7FEC 7FE8 7FE4 7FE0 7FD5 (low 185) | ||
| + | MODE 004F BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 185) | ||
| + | MODE 004F BAUD 0002: 1 1 1 1 1 1 1 1 (low 185) | ||
| + | MODE 004F BAUD FFFF: 7FFF 7FFB 7FF7 7FE7 7FE3 7FDF 7FDB 7FD0 (low 185) | ||
| + | MODE 004C BAUD 0088: 44 40 3C 31 2D 29 25 1A (low 185) | ||
| + | MODE 004C BAUD 0002: 1 1 1 1 1 1 1 1 (low 185) | ||
| + | MODE 004C BAUD FFFF: 7FFF 7FFB 7FF7 7FEC 7FE8 7FE4 7FE0 7FD5 (low 185) | ||
| + | No write, MODE 004E BAUD 00DC: 10 5 1 6B 67 5C 58 54 (low 185) | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 08JTX.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 08 JTX JOY BYTE TIMES | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Each row: stopwatch:STAT&3FF at every change, from the write to JOY_DATA | ||
| + | TXEN only (M000D B0088 C0001): | ||
| + | 132:1 1218:5 | ||
| + | 77:0 201:1 1194:5 | ||
| + | 77:0 182:1 1226:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | TXEN RXEN (M000D B0088 C0005): | ||
| + | 82:0 187:1 966:3 1259:7 | ||
| + | 77:0 206:1 934:3 1230:7 | ||
| + | 77:0 182:1 960:3 1258:7 | ||
| + | then CTRL 0001, rx FF (1) | ||
| + | TXEN, slot 1 selected (M000D B0088 C0003): | ||
| + | 77:0 182:1 1226:5 1360:7 | ||
| + | 82:0 206:1 1250:5 1384:7 | ||
| + | 77:0 185:1 1228:5 1362:7 | ||
| + | then CTRL 0003, rx FF (1) | ||
| + | BAUD 0044 (M000D B0044 C0001): | ||
| + | 82:1 614:5 | ||
| + | 77:1 627:5 | ||
| + | 77:1 610:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | BAUD 0022 (M000D B0022 C0001): | ||
| + | 77:1 341:5 | ||
| + | 77:1 312:5 | ||
| + | 82:1 347:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | BAUD 0110 (M000D B0110 C0001): | ||
| + | 77:0 182:1 2348:5 | ||
| + | 87:0 423:1 2588:5 | ||
| + | 83:0 188:1 2353:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | BAUD 0089 (M000D B0089 C0001): | ||
| + | 77:0 182:1 1274:5 | ||
| + | 87:0 211:1 1255:5 | ||
| + | 83:0 188:1 1232:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | MUL16 (M000E B0088 C0001): | ||
| + | 77:0 1783:1 19191:5 | ||
| + | 77:0 1749:1 19167:5 | ||
| + | 82:0 1787:1 19204:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | factor 0 (M000C B0088 C0001): | ||
| + | 81:0 186:1 1230:5 | ||
| + | 77:0 204:1 1194:5 | ||
| + | 82:0 187:1 1224:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | 5 bits (M0001 B0088 C0001): | ||
| + | 77:0 182:1 850:5 | ||
| + | 82:0 206:1 817:5 | ||
| + | 77:0 182:1 805:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | 8 bits parity (M001D B0088 C0005): | ||
| + | 77:0 184:1 1119:3 1360:7 | ||
| + | 82:0 206:1 1084:3 1382:7 | ||
| + | 77:0 182:1 1117:3 1357:7 | ||
| + | then CTRL 0001, rx FF (1) | ||
| + | CLK inverted (M010D B0088 C0001): | ||
| + | 74:0 185:1 1230:5 | ||
| + | 87:0 211:1 1202:5 | ||
| + | 83:0 188:1 1232:5 | ||
| + | then CTRL 0001, rx (0) | ||
| + | Poll turn: 73 turns in 4000 cycles | ||
| + | TXEN 0 at the write: 93:4 | ||
| + | then TXEN 1: 93:0 219:1 1264:5 | ||
| + | TXEN cleared after the write: 98:0 203:1 1241:5 | ||
| + | Two writes in a row: 93:0 198:1 977:3 1220:7 | ||
| + | bytes in RX after: 1 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 09JFF.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 09 JFF JOY FIFO AND IRQS | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | 10 bytes with RXEN, none read: STAT 0007 | ||
| + | lw DATA FFFFFFFF (1st and 3 previews), STAT after 0007 | ||
| + | lbu until STAT.1 clears: FF FF FF FF (4), then 3 more: 00 00 00 | ||
| + | 3 bytes, lhu DATA FFFF then STAT 0007, 2 left | ||
| + | TX IRQ CTRL 0401: before a byte STAT 0205 I7 1; 129:10200 294:10201 1316:10205 | ||
| + | acked, cond. still true: STAT 0205 I7 1 | ||
| + | RX IRQ 1 byte CTRL 0805: before a byte STAT 0005 I7 0; 91:10203 1243:10207 | ||
| + | acked, cond. still true: STAT 0207 I7 1 | ||
| + | RX IRQ 2 bytes CTRL 0905: before a byte STAT 0005 I7 0; 86:10203 1238:10207 | ||
| + | 2nd byte: 93:10203 1237:10207 | ||
| + | acked, cond. still true: STAT 0207 I7 1 | ||
| + | ACK IRQ CTRL 1001: before a byte STAT 0005 I7 0; 86:0 247:1 1277:5 | ||
| + | acked, cond. still true: STAT 0005 I7 0 | ||
| + | TX+RX IRQ CTRL 0C01: before a byte STAT 0205 I7 1; 86:10201 1238:10205 | ||
| + | acked, cond. still true: STAT 0205 I7 1 | ||
| + | RX IRQ 8 bytes CTRL 0B05: before a byte STAT 0005 I7 0; 91:10203 1243:10207 | ||
| + | acked, cond. still true: STAT 0207 I7 1 | ||
| + | TX IRQ held, I_STAT.7 acked alone: I7 0 STAT 0205 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 10SRG.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 10 SRG SIO REGISTERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | As found: STAT 00000185 MODE 0000 CTRL 0000 MISC DFFD BAUD 0000 | ||
| + | lw 1F801058 00000000, lw 1F80105C 0000DFFD, lhu 1F801052 FFFF, lhu 1F801056 0000 | ||
| + | Empty RX: lbu FE lhu FFFF lw FFFF7FFF | ||
| + | MODE FFFF: 00FF | ||
| + | MODE 0: 0000 | ||
| + | BAUD FFFF: FFFF | ||
| + | BAUD 1235: 1235 | ||
| + | CTRL one bit at a time, MODE 0 then MODE 004E: CTRL, STAT, I_STAT.8 | ||
| + | M0 bit 0: 0001 0185 0 | ||
| + | M0 bit 1: 0002 0185 0 | ||
| + | M0 bit 2: 0004 0185 0 | ||
| + | M0 bit 3: 0008 0185 0 | ||
| + | M0 bit 5: 0020 0185 0 | ||
| + | M0 bit 7: 0000 0185 0 | ||
| + | M0 bit 8: 0100 0185 0 | ||
| + | M0 bit 9: 0200 0185 0 | ||
| + | M0 bit 10: 0400 0385 1 | ||
| + | M0 bit 11: 0800 0185 0 | ||
| + | M0 bit 12: 1000 0385 1 | ||
| + | M0 bit 13: 0000 0185 0 | ||
| + | M0 bit 14: 0000 0185 0 | ||
| + | M0 bit 15: 0000 0185 0 | ||
| + | M1 bit 0: 0001 0185 0 | ||
| + | M1 bit 1: 0002 0185 0 | ||
| + | M1 bit 2: 0004 0185 0 | ||
| + | M1 bit 3: 0008 0185 0 | ||
| + | M1 bit 5: 0020 0185 0 | ||
| + | M1 bit 7: 0080 0185 0 | ||
| + | M1 bit 8: 0100 0185 0 | ||
| + | M1 bit 9: 0200 0185 0 | ||
| + | M1 bit 10: 0400 0385 1 | ||
| + | M1 bit 11: 0800 0185 0 | ||
| + | M1 bit 12: 1000 0385 1 | ||
| + | M1 bit 13: 0000 0185 0 | ||
| + | M1 bit 14: 0000 0185 0 | ||
| + | M1 bit 15: 0000 0185 0 | ||
| + | MODE 004E CTRL FFAF: 1FAF | ||
| + | MISC write, read with MODE 004E (8 bits) and 0042 (5 bits): | ||
| + | 1234: 3412 D4D2, read again D4D2 | ||
| + | FFFF: FFFF DFDF, read again DFDF | ||
| + | 0000: 0000 C0C0, read again C0C0 | ||
| + | A5C3: C3A5 C3C5, read again C3C5 | ||
| + | MISC 1234 then 5000 cycles: 3412 | ||
| + | Before reset: MODE 004E CTRL 0023 MISC 7856 BAUD 00DC STAT 0385 | ||
| + | CTRL 0040: MODE 0000 CTRL 0000 MISC 7856 BAUD 0000 STAT 0000E185 | ||
| + | Put back: MODE 0000 CTRL 0000 BAUD 0000 (MISC left 7856) | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 11STX.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 11 STX SIO TRANSFERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | MODE 004D (8N1 MUL1) BAUD 0088; stopwatch:STAT&3FF (+I_STAT.7,8 at bits 16,17) | ||
| + | TXEN C0001: before STAT 0185 I8 0; write 55h: 144:180 304:181 1593:185 | ||
| + | RX bytes 0, CTRL 0001 | ||
| + | TXEN DTR RTS C0023: before STAT 0185 I8 0; write 55h: 120:181 1464:185 | ||
| + | RX bytes 0, CTRL 0023 | ||
| + | +TX IRQ C0423: before STAT 0385 I8 1; write 55h: 110:20381 1511:20385 | ||
| + | RX bytes 0, CTRL 0423 | ||
| + | TXEN RXEN DTR RTS C0027: before STAT 0185 I8 0; write 55h: 115:180 270:181 1547:185 | ||
| + | RX bytes 0, CTRL 0027 | ||
| + | +RX IRQ C0827: before STAT 0185 I8 0; write 55h: 120:181 1524:185 | ||
| + | RX bytes 0, CTRL 0827 | ||
| + | +DSR IRQ C1027: before STAT 0385 I8 1; write 55h: 115:20381 1466:20385 | ||
| + | RX bytes 0, CTRL 1027 | ||
| + | RXEN only, 20000 cycles: 102:20185 | ||
| + | RX bytes 0 | ||
| + | Write with TXEN 0, TXEN 1 later: 1114:180 1251:181 2553:185 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 12JPD.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 12 JPD PAD IN SLOT 1 | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Slot 1, 01 42 00 00 00..., every change of JOY_STAT (+I_STAT.7 at bit 16): | ||
| + | 01->FF 150:0 296:1 1320:5 1472:7 1749:10287 1849:10207 | ||
| + | 42->41 101:0 236:1 1259:5 1413:7 1689:10287 1779:10207 | ||
| + | 00->5A 92:0 227:1 1311:5 1464:7 1742:10287 1894:10207 | ||
| + | 00->FF 92:0 227:1 1248:5 1404:7 1689:10287 1779:10207 | ||
| + | 00->FF 92:1 1170:5 1322:7 | ||
| + | send 01 42 00 00 00 00 00 00 00 | ||
| + | got FF 41 5A FF FF (4 acked) | ||
| + | /ACK at 1749 1689 1742 1689; low for 100 90 152 90 | ||
| + | 8 more reads (/ACK times per byte): | ||
| + | 4: FF 41 5A FF FF | 1665 1665 1667 1730 | ||
| + | 4: FF 41 5A FF FF | 1663 1680 1613 1729 | ||
| + | 4: FF 41 5A FF FF | 1671 1678 1605 1740 | ||
| + | 4: FF 41 5A FF FF | 1664 1666 1618 1730 | ||
| + | 4: FF 41 5A FF FF | 1661 1675 1672 1741 | ||
| + | 4: FF 41 5A FF FF | 1671 1678 1695 1740 | ||
| + | 4: FF 41 5A FF FF | 1664 1666 1618 1730 | ||
| + | 4: FF 41 5A FF FF | 1661 1675 1672 1741 | ||
| + | 01h, tight loop: /ACK after, low for: 1702/95 1702/107 1713/107 1713/107 1702/107 1702/107 1702/107 1713/107 | ||
| + | Ack while /ACK low (seen at 1696): STAT then 0287; after /ACK high 0207; acked again 0007 | ||
| + | 01h with CTRL 0003 (no ACK IRQ): 93:1 1212:5 1364:7 1640:87 1730:7 | ||
| + | 01h at once after selecting: 93:0 210:1 1300:5 1452:7 1790:10287 1880:10207 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 13JCF.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 13 JCF PAD CONFIG MODE | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Slot 1 01 42 first:send 01 42 00 00 00 00 00 00 00 | ||
| + | got FF 41 5A FF FF (4 acked) | ||
| + | /ACK at 1755 1744 1681 1615; low for 90 90 152 152 | ||
| + | send 01 43 00 01 00 00 00 00 00 | ||
| + | got FF 41 5A 01 (3 acked) | ||
| + | /ACK at 1670 1671 1747; low for 90 90 90 | ||
| + | send 01 45 00 00 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1671; low for 90 | ||
| + | send 01 46 00 00 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1668; low for 100 | ||
| + | send 01 46 00 01 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1668; low for 90 | ||
| + | send 01 47 00 00 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1668; low for 100 | ||
| + | send 01 4C 00 00 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1668; low for 90 | ||
| + | send 01 4C 00 01 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1668; low for 100 | ||
| + | send 01 48 00 00 00 00 00 00 00 | ||
| + | got FF 41 (1 acked) | ||
| + | /ACK at 1668; low for 90 | ||
| + | send 01 42 00 00 00 00 00 00 00 | ||
| + | got FF 41 5A FF FF (4 acked) | ||
| + | /ACK at 1668 1678 1734 1686; low for 100 90 152 90 | ||
| + | send 01 43 00 00 00 00 00 00 00 | ||
| + | got FF 41 5A 01 (3 acked) | ||
| + | /ACK at 1668 1678 1792; low for 90 90 90 | ||
| + | send 01 42 00 00 00 00 00 00 00 | ||
| + | got FF 41 5A FF FF (4 acked) | ||
| + | /ACK at 1671 1680 1746 1687; low for 90 90 90 90 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | 14IEX.txt: | ||
| + | |||
| + | ``` | ||
| + | ===== 14 IEX IRQ ENTRY | BIOS 19951204 System ROM Version 3.0 11/18/96 A | ||
| + | BadVaddr as the group starts: 00000480 | ||
| + | Kernel's 80000080h: 3C1A0000 275A0C80 03400008 00000000 | ||
| + | SR as found 40000401. Rows: instructions after the trigger @ timer 2 in the handler | ||
| + | mtc0 SR IEc 0->1, IRQ pending: 2@68 2@54 2@59 2@54 2@54 2@58 | ||
| + | last CAUSE 00000000 SR 40000404 I_STAT 0009 | ||
| + | mtc0 SR Im2 0->1, IEc 1, IRQ pending: 1@72 none none none none none | ||
| + | sh I_MASK 8, I_STAT.3 set, IEc 1: none none none none none none | ||
| + | sw DICR force, I_MASK 8, IEc 1: 8@60 8@63 8@59 8@59 8@59 8@59 | ||
| + | T2 target 100-107: 100@135 101@141 102@142 103@149 100@144 105@149 106@146 107@147 | ||
| + | T2 target 150-157: 150@190 151@197 152@192 153@193 150@194 155@195 156@196 157@197 | ||
| + | last CAUSE 00000000 SR 40000404 I_STAT 0049 | ||
| + | T2 into a 3 instruction loop, target 100-115: EPC word (from the mode write) and BD | ||
| + | 2/0 2/1 1/0 2/0 2/1 1/0 2/0 2/1 1/0 2/0 2/1 1/0 2/0 2/1 1/0 2/0 | ||
| + | Kernel's vector back: 3C1A0000 | ||
| + | Done. | ||
| + | ``` | ||
| + | |||
| + | ## References | ||
| + | |||
| + | [^run]: SCPH-5501 output: [irqsio/14IEX.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/14IEX.txt). | ||
| + | [^h-imr]: Run 20260928T0000Z-5501a-card-h: [irqsio/01IMR.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/01IMR.txt). | ||
| + | [^h-ist]: Run 20260928T0000Z-5501a-card-h: [irqsio/02IST.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/02IST.txt). | ||
| + | [^h-ied]: Run 20260928T0000Z-5501a-card-h: [irqsio/03IED.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/03IED.txt). | ||
| + | [^h-ip2]: Run 20260928T0000Z-5501a-card-h: [irqsio/04IP2.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/04IP2.txt). | ||
| + | [^h-ilt]: Run 20260928T0000Z-5501a-card-h: [irqsio/05ILT.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/05ILT.txt). | ||
| + | [^h-iex]: Run 20260928T0000Z-5501a-card-h: [irqsio/14IEX.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/14IEX.txt). | ||
| + | [^h-jrg]: Run 20260928T0000Z-5501a-card-h: [irqsio/06JRG.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/06JRG.txt). | ||
| + | [^h-jbd]: Run 20260928T0000Z-5501a-card-h: [irqsio/07JBD.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/07JBD.txt). | ||
| + | [^h-jtx]: Run 20260928T0000Z-5501a-card-h: [irqsio/08JTX.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/08JTX.txt). | ||
| + | [^h-jpd]: Run 20260928T0000Z-5501a-card-h: [irqsio/12JPD.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/12JPD.txt). | ||
| + | [^h-jcf]: Run 20260928T0000Z-5501a-card-h: [irqsio/13JCF.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/13JCF.txt). | ||
| + | [^h-srg]: Run 20260928T0000Z-5501a-card-h: [irqsio/10SRG.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/10SRG.txt). | ||
| + | [^h-stx]: Run 20260928T0000Z-5501a-card-h: [irqsio/11STX.txt](/tests/raw/20260928T0000Z-5501a-card-h/irqsio/11STX.txt). | ||
| + | |||