Interrupt Controller and Serial Ports: Difference between revisions
| Revision as of 05:40, 23 October 2026 RemmyLee (Hardware tests: 15 more test pages (CPU, DMA, SPU, GPU, MDEC, CD-ROM, bus), each with See also links to the pages that measure the same parts) | Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | ||
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| Every group runs with SR.IEc cleared by MTC0 and puts back SR, I_MASK and the root counters at the end. JOY_CTRL bit 13 (slot 2) is never written as 1. Times are counted on root counter 2 in system clock cycles from the write that starts the event. The handler group runs last because it can hang the console.[^run] | Every group runs with SR.IEc cleared by MTC0 and puts back SR, I_MASK and the root counters at the end. JOY_CTRL bit 13 (slot 2) is never written as 1. Times are counted on root counter 2 in system clock cycles from the write that starts the event. The handler group runs last because it can hang the console.[^run] | ||
| + | See also: | ||
| + | |||
| + | - [Peripheral Registers and Bus Delays](/tests/peripheral-bus-delays/) | ||
| + | |||
| ## Results | ## Results | ||