Interrupt Controller and Serial Ports: Difference between revisions
| Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | ||
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| Every group runs with SR.IEc cleared by MTC0 and puts back SR, I_MASK and the root counters at the end. JOY_CTRL bit 13 (slot 2) is never written as 1. Times are counted on root counter 2 in system clock cycles from the write that starts the event. The handler group runs last because it can hang the console.[^run] | Every group runs with SR.IEc cleared by MTC0 and puts back SR, I_MASK and the root counters at the end. JOY_CTRL bit 13 (slot 2) is never written as 1. Times are counted on root counter 2 in system clock cycles from the write that starts the event. The handler group runs last because it can hang the console.[^run] | ||
| + | See also: | ||
| + | |||
| + | - [Peripheral Registers and Bus Delays](/tests/peripheral-bus-delays/) | ||
| + | |||
| ## Results | ## Results | ||
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| ### Edges | ### Edges | ||
| − | Each I_STAT bit is set by a rising edge of its source. With DICR bit 15 still set, I_STAT bit 3 stayed 0 after it was acknowledged, and it was set again only after the force bit was cleared and set. The GPU interrupt behaves the same way: a second GP0(1Fh) with GPUSTAT bit 24 still set raised nothing until GP1(02h) cleared it.[^h-ied] | + | Each I_STAT bit is set by a rising edge of its source. With DICR bit 15 still set, I_STAT bit 3 stayed 0 after it was acknowledged, and it was set again only after the force bit was cleared and set. The GPU interrupt behaves the same way: a second GP0(1Fh) with GPUSTAT bit 24 still set raised nothing until GP1(02h) cleared it.[^h-ied] Root counter 0 at target 99 in repeat mode set I_STAT bit 4 990 times in 100000 cycles in pulse mode and 495 times in toggle mode.[^h-ied] |
| − | Root counter 0 at target 99 in repeat mode set I_STAT bit 4 990 times in 100000 cycles in pulse mode and 495 times in toggle mode.[^h-ied] | ||
| − | |||
| ### CAUSE.IP2 | ### CAUSE.IP2 | ||
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| ### SIO0 Registers | ### SIO0 Registers | ||
| − | JOY_MODE keeps bits 0 to 5 and 8 (013Fh), JOY_BAUD keeps 16 bits, and JOY_CTRL keeps bits 0 to 3, 5 and 8 to 12. CTRL bit 6 resets the port: MODE, BAUD and CTRL read 0 and STAT 00000005h. A read of the empty receive buffer returned 47h in every byte lane.[^h-jrg] | + | JOY_MODE keeps bits 0 to 5 and 8 (013Fh), JOY_BAUD keeps 16 bits, and JOY_CTRL keeps bits 0 to 3, 5 and 8 to 12. CTRL bit 6 resets the port: MODE, BAUD and CTRL read 0 and STAT 00000005h. A read of the empty receive buffer returned 47h in every byte lane.[^h-jrg] CTRL bit 10 (TX IRQ) and bit 11 (RX IRQ) set STAT bit 9 and I_STAT bit 7 at once when their condition is already true.[^h-jrg] |
| − | CTRL bit 10 (TX IRQ) and bit 11 (RX IRQ) set STAT bit 9 and I_STAT bit 7 at once when their condition is already true.[^h-jrg] | ||
| − | |||
| ### Baud Timer | ### Baud Timer | ||