Load Landing and Device Loads: Difference between revisions
| Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | Revision as of 05:49, 23 October 2026 RemmyLee (Hardware tests: the last 15 test pages (timers, SPU, CPU, GPU, DMA, CD-ROM, GTE), See also links both ways; uncited clock claim removed) | ||
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| Its GTE groups time single NOP steps on inputs that earlier runs left as ranges. Each of the three vectors of RTPT is timed on its own. Each GTE row runs cold from RAM and then cached.[^runh] | Its GTE groups time single NOP steps on inputs that earlier runs left as ranges. Each of the three vectors of RTPT is timed on its own. Each GTE row runs cold from RAM and then cached.[^runh] | ||
| + | See also: | ||
| + | |||
| + | - [CPU Pipeline Timing and Cache Isolation](/tests/cpu-pipeline-cache-isolation/) | ||
| + | - [Bus Access and Device Register Timing](/tests/bus-access-register-timing/) | ||
| + | - [Load Delay Slot Collisions](/tests/load-delay-slot-collisions/) | ||
| + | - [KSEG0 and KSEG1 Code Fetch](/tests/kseg0-kseg1-code-fetch/) | ||
| + | |||
| ## Results | ## Results | ||