Load Landing and Device Loads: Difference between revisions
| Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | Revision as of 05:49, 23 October 2026 RemmyLee (Hardware tests: the last 15 test pages (timers, SPU, CPU, GPU, DMA, CD-ROM, GTE), See also links both ways; uncited clock claim removed) | ||
| Line 18: | Line 18: | ||
| - [CPU Pipeline Timing and Cache Isolation](/tests/cpu-pipeline-cache-isolation/) | - [CPU Pipeline Timing and Cache Isolation](/tests/cpu-pipeline-cache-isolation/) | ||
| - [Bus Access and Device Register Timing](/tests/bus-access-register-timing/) | - [Bus Access and Device Register Timing](/tests/bus-access-register-timing/) | ||
| + | - [Load Delay Slot Collisions](/tests/load-delay-slot-collisions/) | ||
| + | - [KSEG0 and KSEG1 Code Fetch](/tests/kseg0-kseg1-code-fetch/) | ||
| ## Results | ## Results | ||