Load Landing and Device Loads: Difference between revisions
| Revision as of 05:40, 23 October 2026 RemmyLee (Hardware tests: 15 more test pages (CPU, DMA, SPU, GPU, MDEC, CD-ROM, bus), each with See also links to the pages that measure the same parts) | Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | ||
| Line 14: | Line 14: | ||
| Its GTE groups time single NOP steps on inputs that earlier runs left as ranges. Each of the three vectors of RTPT is timed on its own. Each GTE row runs cold from RAM and then cached.[^runh] | Its GTE groups time single NOP steps on inputs that earlier runs left as ranges. Each of the three vectors of RTPT is timed on its own. Each GTE row runs cold from RAM and then cached.[^runh] | ||
| + | See also: | ||
| + | |||
| + | - [CPU Pipeline Timing and Cache Isolation](/tests/cpu-pipeline-cache-isolation/) | ||
| + | - [Bus Access and Device Register Timing](/tests/bus-access-register-timing/) | ||
| + | |||
| ## Results | ## Results | ||