MDEC Start and Interrupt Entry Timing: Difference between revisions
| Revision as of 05:40, 23 October 2026 RemmyLee (Hardware tests: 15 more test pages (CPU, DMA, SPU, GPU, MDEC, CD-ROM, bus), each with See also links to the pages that measure the same parts) | Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | ||
| Line 22: | Line 22: | ||
| | TIE | Interrupt entry when the DMA interrupt is enabled by MTC0 to SR or by a store to I_MASK | | | TIE | Interrupt entry when the DMA interrupt is enabled by MTC0 to SR or by a store to I_MASK | | ||
| + | See also: | ||
| + | |||
| + | - [MDEC Status and Decode Timing](/tests/mdec-status-decode-timing/) | ||
| + | - [MDEC Block Timing](/tests/mdec-block-timing/) | ||
| + | |||
| ## Results | ## Results | ||