MDEC Start and Interrupt Entry Timing: Difference between revisions
| Revision as of 05:18, 23 October 2026 RemmyLee (Hardware tests: nine DMA, MDEC and BIOS test pages with part names for titles; join one-sentence paragraphs per voice.md) | Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | ||
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| | TIE | Interrupt entry when the DMA interrupt is enabled by MTC0 to SR or by a store to I_MASK | | | TIE | Interrupt entry when the DMA interrupt is enabled by MTC0 to SR or by a store to I_MASK | | ||
| + | See also: | ||
| + | |||
| + | - [MDEC Status and Decode Timing](/tests/mdec-status-decode-timing/) | ||
| + | - [MDEC Block Timing](/tests/mdec-block-timing/) | ||
| + | |||
| ## Results | ## Results | ||