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MDEC Status and Decode Timing: Difference between revisions

Revision as of 05:27, 23 October 2026
RemmyLee
(GTE Lighting Input Latency: split the cross-link sentence)		Revision as of 05:40, 23 October 2026
RemmyLee
(Hardware tests: 15 more test pages (CPU, DMA, SPU, GPU, MDEC, CD-ROM, bus), each with See also links to the pages that measure the same parts)
Line 1:Line 1:
+---
+title: MDEC Status and Decode Timing
+type: test
+summary: Measures MDEC output after short decodes, the status block field during a decode, commands written while the MDEC is busy, reset in a stuck decode, DMA0 table and decode times, and a whole frame read by the CPU.
+category: Hardware tests
+info: Machine = SCPH-5501
+info: Program = followup19 and followup19m
+---
+
+## Overview
+
+Each group writes the MDEC with the CPU or by DMA0 and DMA1, and prints the status word, the words that came out, their CRC and counts of root counter 2 in system clock cycles. Short decodes send a decode command for N words of a known block stream after a decode of 32 words, and print what comes out. Another group polls the status after the last word of a decode and lists each change with its time.[^sdr][^mst]
+
+Further groups write markers and decode commands while a table load or a decode is in progress, reset the MDEC in a decode that is waiting for words, and time DMA0 for tables and DMA0 and DMA1 for mono decodes. The last group decodes a whole frame stream sent by DMA0, reads every output word with the CPU and sends each strip to VRAM by DMA2.[^swc][^rsd][^dtb][^pio]
+
+See also:
+
+- [MDEC Output](/tests/mdecout/)
+- [MDEC Hand-Made Streams](/tests/mdec2/)
+- [MDEC Start and Interrupt Entry Timing](/tests/mdec-start-interrupt-entry/)
+- [MDEC Reset and Store Timing](/tests/sxmdrst/)
+- [MDEC Block Timing](/tests/mdec-block-timing/)
+
+## Results
+
+### Short Decodes
+
+Each row first ran a decode of 32 words in which words 0 to 29 each hold one block, and it gave 240 words out at 4 bit and 480 at 8 bit. At 15 bit it gave 640 words and at 24 bit 960. A decode command for N words of the block stream then gave one 8x8 block less for each step of N, so 30 minus N blocks came out at 4 and 8 bit. At 15 and 24 bit the blocks fell from 19 at N 1 to 16 at N 4 and stayed at 16, and the CPU reads gave up at N 4 and 5.[^sdr]
+
+Table: Words out of a decode command for N words
+
+| Depth | N 1 | N 2 | N 3 | N 4 | N 5 | N 6 |
+| --- | --- | --- | --- | --- | --- | --- |
+| 4 bit | 232 | 224 | 216 | 208 | 200 | 192 |
+| 8 bit | 464 | 448 | 432 | 416 | 400 | 384 |
+| 15 bit | 608 | 576 | 544 | 512 | 512 | 512 |
+| 24 bit | 912 | 864 | 816 | 768 | 768 | 768 |
+
+The 8-bit decode for 1 word, run twice with no decode before it, gave 384 words (24 blocks) with CRC 53A9BC68h both times. The 8-bit decode for 6 words after the 32-word decode gave the same 384 words and CRC.[^sdr]
+
+The first 8-bit decode after power on, for 1 word, gave 16 words (one block) with CRC 7DDB182Eh. After a reset, a decode for 6 words gave 16 words with CRC 2302868Ch, and a decode for 1 word that followed with no reset gave CRC A6C7671Fh. A decode for 1 word after a further reset gave CRC 2302868Ch again.[^mpo]
+
+### Block Field
+
+A decode command for 256 words was followed by 32 words, and the status was then polled. Bits 18 to 16 of the status are the block field. The field read 4 straight after word 32, changed to 5 at 857 to 862 cycles after it, to 0 at 1,359 to 1,364 and to 1 at 1,871 to 1,884. The two runs at each depth gave the same changes to within 10 cycles.[^mst]
+
+Table: Status changes after word 32 in the first run
+
+| 15 bit | Cycles | 24 bit | Cycles |
+| --- | --- | --- | --- |
+| E60500DFh | 862 | E40500DFh | 857 |
+| E60000DFh | 1,364 | E40000DFh | 1,359 |
+| 660000DFh | 1,509 | 640000DFh | 1,470 |
+| 360000DFh | 1,552 | 340000DFh | 1,547 |
+| 360100DFh | 1,884 | 3C0000DFh | 1,726 |
+| 3E0100DFh | 1,910 | 3C0100DFh | 1,871 |
+
+### Commands While Busy
+
+After a full luminance quant table of 16 words or a full scale table of 32 words, each of the markers 0000A001h to 0000A004h showed in status bits 0 to 15 as soon as it was written. After a scale table one word short, the first marker was taken as the last table word and did not show, and the other three did. A decode command written in the same state was taken as the last table word as well. The FE00FE00h word after it was then taken as a command, and the status read 8784FE00h.[^swc]
+
+During an 8-bit decode for 4 words with only 2 sent, no marker showed, and the status read A2040000h and then E204FFFFh. During a decode with all of its words in and its output unread, the status stayed 2204FFFFh whatever was written.[^swc]
+
+### Reset in a Stuck Decode
+
+An 8-bit decode for 32 words was given 18 words, and MDEC1 was then written 80000000h after T NOPs. The status read 80040000h at 14 to 105 cycles in most rows. With T 0 and 5 NOPs after the reset, the first run read A2040000h at 13 cycles. With T 10 or more and 5 NOPs after the reset, the second run read 00000000h at 9 to 15 cycles. Every row read 80040000h 2,000 cycles later.[^rsd]
+
+### DMA Timing
+
+A table sent by DMA0 took 62 cycles for 1 word and one cycle more for each further word up to 16, which took 77. A table of 32 words took 93 to 106 cycles in blocks of 16 or 32. After a colour quant table of n words out of 32, status bits 0 to 15 held 31 minus n, and the status read 8004FFFFh once all 32 had been sent. Decode words sent by DMA0 took about the same times as table words up to 32, and 64 words took 379 to 400 cycles.[^dtb]
+
+Table: DMA0 cycles for n words in blocks of 16
+
+| n | Colour quant table | Decode words |
+| --- | --- | --- |
+| 1 | 62 | 62 |
+| 2 | 63 | 63 to 67 |
+| 4 | 65 | 65 to 69 |
+| 8 | 69 | 69 to 73 |
+| 16 | 77 | 77 |
+| 32 | 96 | 96 |
+| 64 | | 395 to 400 |
+
+A mono decode of DC-only blocks ended DMA0 at 91 to 109 cycles in every row. DMA1 ended at 947 to 1,007 cycles for 1 block, 3,534 to 3,609 for 6 blocks and 12,780 to 12,825 for 24 blocks, at both 8 and 4 bit. Each further block therefore added about 510 to 520 cycles.[^mbt]
+
+### Frame Read by the CPU
+
+The frame streams of the ps1-tests programs mdec/frame-15bit.exe and frame-24bit.exe were decoded, and the CPU read each output word with the waits of those programs. At both depths the wait after the last word of strip 20 gave up, so 19 of the 20 strips were sent. At 15 bit, row 0 of the picture held decoded pixels up to x 303, and x 304 to 319 kept the 0421h fill written before the decode.[^pio]
+
+## Runs
+
+### 3 October 2026
+
+[00RUN.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup19/00RUN.txt)
+
+```
+===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+7 tests
+A chain program, linked at 80100000
+Saved on the card in slot 2, from image 1
+COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 00000480 BDAM 00000000
+BPCM 00000000 SR 40000000 Cause 00000020 EPC 8001D628 PRId 00000002
+```
+
+[01SDR.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup19/01SDR.txt)
+
+```
+===== 01 SDR F19 MDEC SHORT RING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+Short decodes by CPU, unsigned, the 4bit/8bit block's tables. The ring first: a decode
+of 32 words, words 0-29 one block each (Q 1, DC 16*i-256, FE00h), 30-31 FE00FE00h. Then
+count N of the 4bit/8bit block. Words out, CRC, status; the third 8x8 block in full for
+N 1 and 2, its CRC and first word for N 3-6.
+4 bit count 1 (ring 240 out): 232 out (29 blocks), CRC D0E2516F, 8004FFFF; third block:
+ 55555555 55555555 55555555 55555555 55555555 55555555 55555555 55555555
+4 bit count 2 (ring 240 out): 224 out (28 blocks), CRC 10E79072, 8004FFFF; third block:
+ 55555555 55555555 55555555 55555555 55555555 55555555 55555555 55555555
+4 bit count 3 (ring 240 out): 216 out (27 blocks), CRC 6983FF00, 8004FFFF; third block CRC 44D7FFCF first 55555555
+4 bit count 4 (ring 240 out): 208 out (26 blocks), CRC 4CA3E2FD, 8004FFFF; third block CRC 70636611 first 66666666
+4 bit count 5 (ring 240 out): 200 out (25 blocks), CRC AED9F193, 8004FFFF; third block CRC 70636611 first 66666666
+4 bit count 6 (ring 240 out): 192 out (24 blocks), CRC 787D1CC0, 8004FFFF; third block CRC 70636611 first 66666666
+8 bit count 1 (ring 480 out): 464 out (29 blocks), CRC 42B5EF7B, 8204FFFF; third block:
+ 4C4C4C4C 4C4C4C4C 4C4C4C4C 4C4C4C4C 4C4C4C4C 4C4C4C4C 4C4C4C4C 4C4C4C4C
+ 4C4C4C4C 4C4C4C4C 4C4C4C4C 4C4C4C4C 4C4C4C4C 4C4C4C4C 4C4C4C4C 4C4C4C4C
+8 bit count 2 (ring 480 out): 448 out (28 blocks), CRC D7A6DBBF, 8204FFFF; third block:
+ 50505050 50505050 50505050 50505050 50505050 50505050 50505050 50505050
+ 50505050 50505050 50505050 50505050 50505050 50505050 50505050 50505050
+8 bit count 3 (ring 480 out): 432 out (27 blocks), CRC 04B35639, 8204FFFF; third block CRC 94B9CB14 first 54545454
+8 bit count 4 (ring 480 out): 416 out (26 blocks), CRC 328E3446, 8204FFFF; third block CRC F22AAB7B first 58585858
+8 bit count 5 (ring 480 out): 400 out (25 blocks), CRC 6D80EE53, 8204FFFF; third block CRC D05B8B5E first 5C5C5C5C
+8 bit count 6 (ring 480 out): 384 out (24 blocks), CRC 53A9BC68, 8204FFFF; third block CRC F7F46CCC first 60606060
+15 bit count 1 (ring 640 out): 608 out (19 blocks), CRC 359D1086, 8603FFFF; third block:
+ 005F005F 005F005F 005F005F 007D007D 005F005F 005F005F 005F005F 007D007D
+ 00BA00BA 00D900D9 00F700F7 01140114 00BA00BA 00D900D9 00F700F7 01140114
+ 018C018C 01AB01AB 01C901C9 01E601E6 018C018C 01AB01AB 01C901C9 01E601E6
+ 02220222 02410241 02600260 02800280 02220222 02410241 02600260 02800280
+15 bit count 2 (ring 640 out): 576 out (18 blocks), CRC 2F22221C, 8602FFFF; third block:
+ 01C901C9 01510151 00BC00BC 005F005F 01C901C9 01510151 00BC00BC 005F005F
+ 02610261 01C901C9 01330133 00DA00DA 02610261 01C901C9 01330133 00DA00DA
+ 02E002E0 02600260 01CA01CA 01700170 02E002E0 02600260 01CA01CA 01700170
+ 03200320 02C002C0 02240224 01CA01CA 03200320 02C002C0 02240224 01CA01CA
+15 bit count 3 (ring 640 out): 544 out (17 blocks), CRC 48E3A981, 8601FFFF; third block CRC 3C4C2F23 first 058E058E
+15 bit count 4 (ring 640 out): 512 out (16 blocks), CRC 77CB826C, A600FFFF, gave up; third block CRC C82B9A98 first 0A630A63
+15 bit count 5 (ring 640 out): 512 out (16 blocks), CRC 0F0E7F1A, A605FFFF, gave up; third block CRC D514CA84 first 12821282
+15 bit count 6 (ring 640 out): 512 out (16 blocks), CRC 857AA885, 8604FFFF; third block CRC 128D165E first 15B015B0
+24 bit count 1 (ring 960 out): 912 out (19 blocks), CRC 17046533, 8403FFFF; third block:
+ FF000CFF 0CFF000C 000CFF00 FF000FFF 1AEB000F 001AEB00 FF000CFF 0CFF000C
+ 000CFF00 FF000FFF 1AEB000F 001AEB00 CD002ACD 2EC4002A 002EC400 B50036B5
+ 41A00036 0041A000 CD002ACD 2EC4002A 002EC400 B50036B5 41A00036 0041A000
+ 61006161 65580061 00655800 49006D49 7834006D 00783400 61006161 65580061
+ 00655800 49006D49 7834006D 00783400 13008813 8C0B0088 008C0B00 00009400
+ 9F000094 009F0000 13008813 8C0B0088 008C0B00 00009400 9F000094 009F0000
+24 bit count 2 (ring 960 out): 864 out (18 blocks), CRC E9CA28EE, 8402FFFF; third block:
+ 4A00714A 51890071 00518900 DD0026DD 0FFF0026 000FFF00 4A00714A 51890071
+ 00518900 DD0026DD 0FFF0026 000FFF00 05009405 74440094 00744400 9A00489A
+ 2FCC0048 002FCC00 05009405 74440094 00744400 9A00489A 2FCC0048 002FCC00
+ 0000BA00 9A0000BA 009A0000 4E006F4E 5581006F 00558100 0000BA00 9A0000BA
+ 009A0000 4E006F4E 5581006F 00558100 0000C500 B30000C5 00B30000 1D00881D
+ 6D510088 006D5100 0000C500 B30000C5 00B30000 1D00881D 6D510088 006D5100
+24 bit count 3 (ring 960 out): 816 out (17 blocks), CRC D3F9C7F9, 8401FFFF; third block CRC 16408253 first 72076172
+24 bit count 4 (ring 960 out): 768 out (16 blocks), CRC F2A0313F, A400FFFF, gave up; third block CRC B3AC504A first 17129417
+24 bit count 5 (ring 960 out): 768 out (16 blocks), CRC DAC09728, A405FFFF, gave up; third block CRC 0EE0F5D7 first 0D1D9E0D
+24 bit count 6 (ring 960 out): 768 out (16 blocks), CRC 1157F003, 8404FFFF; third block CRC F26CFAE0 first 80286880
+12SMS's row again (the tables the last words in, 8 bit count 1; 992 out on chain f):
+8 bit count 1, no ring: 384 out (24 blocks), CRC 53A9BC68, 8204FFFF; third block:
+ 60606060 60606060 60606060 60606060 60606060 60606060 60606060 60606060
+ 60606060 60606060 60606060 60606060 60606060 60606060 60606060 60606060
+8 bit count 1, no ring: 384 out (24 blocks), CRC 53A9BC68, 8204FFFF; third block:
+ 60606060 60606060 60606060 60606060 60606060 60606060 60606060 60606060
+ 60606060 60606060 60606060 60606060 60606060 60606060 60606060 60606060
+Done.
+```
+
+[02MST.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup19/02MST.txt)
+
+```
+===== 02 MST F19 MDEC BLOCK FIELD | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+01TMS's stream: the step stream's tables, MDEC1 60000000h, timer 2 zeroed, the decode
+command for 256 words, words 1-32 with no reads, the status after each (status@timer 2).
+Then the status polled for 6000 cycles after word 32 and each change listed (@cycles
+after word 32). Bits 18-16 are the block field (i-o-ports.txt:31).
+15 bit run 1: command B60400FF@13; words where bits 16-31 changed: w32 E60400DF@1039
+ after w32, 6 changes: E60500DF@862 E60000DF@1364 660000DF@1509 360000DF@1552 360100DF@1884 3E0100DF@1910
+15 bit run 2: command B60400FF@13; words where bits 16-31 changed: w32 E60400DF@1029
+ after w32, 6 changes: E60500DF@857 E60000DF@1359 660000DF@1504 360000DF@1547 360100DF@1879 3E0100DF@1905
+24 bit run 1: command B40400FF@13; words where bits 16-31 changed: w32 E40400DF@1014
+ after w32, 6 changes: E40500DF@857 E40000DF@1359 640000DF@1470 340000DF@1547 3C0000DF@1726 3C0100DF@1871
+24 bit run 2: command B40400FF@13; words where bits 16-31 changed: w32 E40400DF@1029
+ after w32, 6 changes: E40500DF@857 E40000DF@1359 640000DF@1470 340000DF@1547 3C0000DF@1726 3C0100DF@1871
+Done.
+```
+
+[03SWC.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup19/03SWC.txt)
+
+```
+===== 03 SWC F19 MDEC BUSY CMDS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+Commands written while busy. Each row: a reset, 2000 cycles, a busy state, its status;
+then four MDEC(0) markers 0000A001h-A004h (bits 0-15 show in the status when taken as a
+command, commands.txt:33-37), or a decode command for C words (8 bit) and C FE00FE00h;
+the status after each store, then 2000 cycles later.
+A full luminance quant table (16 words):
+ 8004FFFF, markers: 8004A001 8004A002 8004A003 8004A004; later 8004A004
+ 8004FFFF, decode for 1: A2040000 E204FFFF; later 2204FFFF
+ 8004FFFF, decode for 2: A2040001 A2040000 E204FFFF; later 2204FFFF
+ 8004FFFF, decode for 4: A2040003 A2040002 A2040001 A2040000 E204FFFF; later 8204FFFF
+A full scale table (32 words):
+ 8004FFFF, markers: 8004A001 8004A002 8004A003 8004A004; later 8004A004
+ 8004FFFF, decode for 1: A2040000 E204FFFF; later 8204FFFF
+ 8004FFFF, decode for 2: A2040001 A2040000 E204FFFF; later 8204FFFF
+ 8004FFFF, decode for 4: A2040003 A2040002 A2040001 A2040000 E204FFFF; later 8204FFFF
+A scale table short by 1 (31 words):
+ A0040000, markers: A004FFFF 8004A002 8004A003 8004A004; later 8004A004
+ A0040000, decode for 1: 8004FFFF 8784FE00; later 8784FE00
+ A0040000, decode for 2: 8004FFFF 8784FE00 8784FE00; later 8784FE00
+ A0040000, decode for 4: 8004FFFF 8784FE00 8784FE00 8784FE00 8784FE00; later 8784FE00
+An 8 bit decode for 4 words given 2:
+ A2040001, markers: A2040000 E204FFFF E204FFFF E204FFFF; later 2204FFFF
+ A2040001, decode for 1: A2040000 E204FFFF; later 2204FFFF
+ A2040001, decode for 2: A2040000 E204FFFF E204FFFF; later 2204FFFF
+ A2040001, decode for 4: A2040000 E204FFFF E204FFFF E204FFFF E204FFFF; later 2204FFFF
+An 8 bit decode of the block, all 32 words in, output unread:
+ 2204FFFF, markers: 2204FFFF 2204FFFF 2204FFFF 2204FFFF; later 2204FFFF
+ 2204FFFF, decode for 1: 2204FFFF 2204FFFF; later 2204FFFF
+ 2204FFFF, decode for 2: 2204FFFF 2204FFFF 2204FFFF; later 2204FFFF
+ 2204FFFF, decode for 4: 2204FFFF 2204FFFF 2204FFFF 2204FFFF 2204FFFF; later 2204FFFF
+Done.
+```
+
+[04RSD.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup19/04RSD.txt)
+
+```
+===== 04 RSD F19 MDEC STUCK RESET | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+A reset in a stuck decode: an 8 bit decode for 32 words given 18 FE00FE00h; T NOPs after
+the 18th, timer 2 zeroed and MDEC1 80000000h; N NOPs, then MDEC1 and timer 2. Run 1
+straight after FlushCache, run 2 the same code again (status@timer 2); then the
+status 2000 cycles on. 12FMR.txt:7-8 read A0040000 after such a reset.
+T 0 N 5: before A204000E; A2040000@13, 80040000@20; later 80040000
+T 0 N 10: before A204000E; 80040000@20, 80040000@29; later 80040000
+T 0 N 20: before A204000E; 80040000@46, 80040000@38; later 80040000
+T 0 N 40: before A204000E; 80040000@91, 80040000@58; later 80040000
+T 10 N 5: before A204000E; 80040000@20, 00000000@15; later 80040000
+T 10 N 10: before A204000E; 80040000@37, 80040000@20; later 80040000
+T 10 N 20: before A204000E; 80040000@56, 80040000@30; later 80040000
+T 10 N 40: before A204000E; 80040000@101, 80040000@50; later 80040000
+T 50 N 5: before A204000E; 80040000@20, 00000000@9; later 80040000
+T 50 N 10: before A204000E; 80040000@37, 80040000@14; later 80040000
+T 50 N 20: before A204000E; 80040000@56, 80040000@24; later 80040000
+T 50 N 40: before A204000E; 80040000@105, 80040000@44; later 80040000
+T 500 N 5: before A204000E; 80040000@20, 00000000@9; later 80040000
+T 500 N 10: before A204000E; 80040000@29, 80040000@14; later 80040000
+T 500 N 20: before A204000E; 80040000@55, 80040000@24; later 80040000
+T 500 N 40: before A204000E; 80040000@101, 80040000@44; later 80040000
+Done.
+```
+
+[05DTB.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup19/05DTB.txt)
+
+```
+===== 05 DTB F19 MDEC DMA0 TABLE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+DMA0 for a table: a reset, 2000 cycles, MDEC1 60000000h, the command by CPU, then DMA0
+of n words in blocks of 16 or 32 (one block of n below that), timed as dmatime.c's
+run_timed (11DMD.txt:4 90-91, 12FMR.txt:11 77): system clocks, three runs, then the
+status after the last run. Kinds: quant colour 32 words, quant luma 16, scale 32, an
+8 bit decode for n FE00FE00h.
+quant colour n 1: bs 16 62/62/62 (B004001E); bs 32 62/62/62 (B004001E);
+quant colour n 2: bs 16 63/63/63 (B004001D); bs 32 63/63/69 (B004001D);
+quant colour n 4: bs 16 65/65/65 (B004001B); bs 32 65/65/65 (B004001B);
+quant colour n 8: bs 16 69/69/69 (B0040017); bs 32 69/69/69 (B0040017);
+quant colour n 16: bs 16 77/77/77 (B004000F); bs 32 77/77/77 (B004000F);
+quant colour n 32: bs 16 96/96/96 (8004FFFF); bs 32 93/98/103 (8004FFFF);
+quant luma n 16: bs 16 77/77/77 (8004FFFF); bs 32 77/77/77 (8004FFFF);
+scale n 32: bs 16 106/96/96 (8004FFFF); bs 32 93/103/93 (8004FFFF);
+decode pad n 1: bs 16 62/62/62 (E204FFFF); bs 32 62/62/62 (E204FFFF);
+decode pad n 2: bs 16 63/63/67 (E204FFFF); bs 32 63/69/63 (E204FFFF);
+decode pad n 4: bs 16 65/65/69 (E204FFFF); bs 32 65/75/65 (E204FFFF);
+decode pad n 8: bs 16 69/69/73 (E204FFFF); bs 32 69/79/69 (E204FFFF);
+decode pad n 16: bs 16 77/77/77 (E204FFFF); bs 32 77/81/81 (E204FFFF);
+decode pad n 32: bs 16 96/96/96 (E204FFFF); bs 32 103/93/93 (E204FFFF);
+decode pad n 64: bs 16 395/400/400 (E204FFFF); bs 32 379/379/379 (E204FFFF);
+Done.
+```
+
+[06MBT.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup19/06MBT.txt)
+
+```
+===== 06 MBT F19 MDEC MONO TIME | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+Mono decode time by DMA, as 11DMD (DC-only blocks, Q 1, DC 20h, quant 01h, scale zero),
+the tables by CPU 2000 cycles after the reset. DMA0 done / DMA1 done in system clocks
+from DMA0's start, three runs; then the output sum and the status (last run).
+8 bit, 1 blocks: 91/988 99/957 99/1007; sum 08080800, 8204FFFF
+8 bit, 6 blocks: 109/3587 99/3534 99/3577; sum 30303000, 8204FFFF
+8 bit, 24 blocks: 99/12795 99/12788 99/12803; sum C0C0C000, 8204FFFF
+4 bit, 1 blocks: 99/947 109/953 99/1000; sum 44444440, 8004FFFF
+4 bit, 6 blocks: 99/3601 99/3599 109/3609; sum 99999980, 8004FFFF
+4 bit, 24 blocks: 99/12825 99/12780 104/12825; sum 66666600, 8004FFFF
+Done.
+```
+
+[07PIO.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup19/07PIO.txt)
+
+```
+===== 07 PIO F19 MDEC FRAME PIO | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+ps1-tests mdec/frame-15bit.exe and frame-24bit.exe (PIO): the whole frame stream by
+DMA0, every word read by the CPU with the EXE's waits (each gives up after 200000 polls
+here), each strip to VRAM by DMA2 at y 256, VRAM first filled with 0421h.
+The stream unpacked: CRC A4FD5107 (as packed).
+15 bit, decode command 380037A0, BCR0 01BD0020; table waits that gave up: 0
+Strip 20 (from 1) word 1920 (from 1): the wait after it gave up.
+At the end: status 8604FFFF, CHCR0 00000201, MADR0 stream+14240 words, BCR0 00000020; after a reset 80040000
+Strip CRCs (19 sent):
+ EB387DFB 6315AB4B 54B785A9 4C73EB70 D4BAAD0A 83887C0F 2B314B1B 65E29633
+ 1681BD1E 3FAAEF4B 5F65ED36 99CD59D1 CD54DE05 1F8F81DC 10B2D94C FD8C29A1
+ 9CF8B587 E0746E0F 0C6D7E67
+VRAM rows 256-271 (picture rows 0-15), 320 halfwords each, CRC:
+ FC74407F 8FEA38DB FBC738D4 AF1C6B3D 7251DA77 9D28A8F3 97B6E9C6 C13C93C7
+ 11F09209 5F2FD591 7E7B9D65 256C944E 8E3C15A9 A71FDFAC 3A8CF576 DA535A7B
+Row 0 from x 300:
+ 18C5 18C5 18C5 18C5 0421 0421 0421 0421 0421 0421 0421 0421 0421 0421 0421 0421
+ 0421 0421 0421 0421 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
+ 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
+ 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
+Row 0 from x 8:
+ 358B 318B 318B 316A 2D6A 2D6A 2D6A 2D6A 2D6A 2D69 2D49 2D49 2D49 2D49 2D49 2D4A
+ 2D49 2D6A 2D6A 2D6A 2D6A 2D6A 316A 318A 318A 318A 358B 35AB 39AB 39AB 39AB 39AB
+ 39CB 39CB 39CB 39AB 39CB 3DCC 39AB 39AB 39AB 398A 358A 358A 358A 358A 358A 358A
+ 358A 358A 358A 398A 39AB 3DAB 3DCB 41CC 41EC 41EC 41EC 41EC 41EC 41EC 41EC 3DCB
+24 bit, decode command 300037A0, BCR0 01BD0020; table waits that gave up: 0
+Strip 20 (from 1) word 2880 (from 1): the wait after it gave up.
+At the end: status 8404FFFF, CHCR0 00000201, MADR0 stream+14240 words, BCR0 00000020; after a reset 34421824
+Strip CRCs (19 sent):
+ 6DF66759 20D13BF8 EA2F6D05 97650F33 F5A7F6F4 5D67C025 9E262AEE E067BD4F
+ FA3E065A DCFD78AD 34762319 710B6A58 8EDF0831 B39F5266 F153C6B0 B94EAB15
+ 56B9C520 1D73C627 80368FB5
+VRAM rows 256-271 (picture rows 0-15), 480 halfwords each, CRC:
+ AFC84DD2 2E062E76 AC3B3932 76E042C5 BD963469 4E0C69DE C868BBCD 3FB1072F
+ 2AFB5BE0 C41C7909 22B32FF3 3E8EF964 D46A1807 A9FDFAB8 56F860E8 EF627695
+Row 0 from x 300:
+ 685D 646E 756F 7067 6277 726B 6861 5F6E 6C66 625B 5A68 6761 6158 5468 645D 5950
+ 4F60 5F58 5750 4E5F 5D55 514A 4859 574F 6158 5468 645D 5A51 4F61 5F58 564F 4D5E
+ 5C54 514A 4859 574F 4A43 4350 504A 4B44 4451 514B 4A43 4150 4E48 4A43 4750 544E
+ 4A43 4350 504A 4B44 4551 524C 4A43 4250 4F49 4A43 4750 544E 4844 444B 4B48 4743
+Row 0 from x 8:
+ 6461 635B 5B66 6663 625A 5B65 6663 6159 5764 625F 5F57 5A62 6562 635B 5A66 6562
+ 564D 4C5B 5A55 534A 4958 5752 514A 4A57 5751 534B 4C56 5754 574E 4B5C 5954 5249
+ 4757 5550 5049 4A56 5751 534B 4B56 5653 5C4F 5162 645E 6154 5767 6A64 6859 5B6D
+ 6F6A 6958 5670 6E67 5D50 5363 6660 6356 5869 6B65 695A 5C6E 706B 6B5A 5872 7069
+Done.
+```
+
+### 5 October 2026
+
+[00RUN.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup19m/00RUN.txt)
+
+```
+===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+1 tests
+A chain program, linked at 80100000
+Saved on the card in slot 2, from image 1
+COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 00000480 BDAM 00000000
+BPCM 00000000 SR 40000000 Cause 00000020 EPC 8001F1E0 PRId 00000002
+```
+
+[01MPO.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup19m/01MPO.txt)
+
+```
+===== 01 MPO F19 MDEC RING AT POWER ON | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+The MDEC from power on (row 80): the 4bit/8bit block's tables, then the decodes below.
+First after power on, 8 bit count 1: 16 out (1 blocks), CRC 7DDB182E, 8204FFFF; each block's first word:
+ 90A0ADB0
+Then, after a reset, 8 bit count 6: 16 out (1 blocks), CRC 2302868C, 8204FFFF; each block's first word:
+ E1B98665
+Then, no reset between, 8 bit count 1: 16 out (1 blocks), CRC A6C7671F, 8204FFFF; each block's first word:
+ 17120E0C
+Then, after a reset, 8 bit count 1: 16 out (1 blocks), CRC 2302868C, 8204FFFF; each block's first word:
+ E1B98665
+Done.
+```
+
+## References
+
+[^sdr]: SCPH-5501 output: [followup19/01SDR.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup19/01SDR.txt)
+[^mst]: SCPH-5501 output: [followup19/02MST.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup19/02MST.txt)
+[^swc]: SCPH-5501 output: [followup19/03SWC.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup19/03SWC.txt)
+[^rsd]: SCPH-5501 output: [followup19/04RSD.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup19/04RSD.txt)
+[^dtb]: SCPH-5501 output: [followup19/05DTB.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup19/05DTB.txt)
+[^mbt]: SCPH-5501 output: [followup19/06MBT.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup19/06MBT.txt)
+[^pio]: SCPH-5501 output: [followup19/07PIO.txt](/tests/raw/20261003T0000Z-5501a-card-o/followup19/07PIO.txt)
+[^mpo]: SCPH-5501 output: [followup19m/01MPO.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup19m/01MPO.txt)