MDEC Output: Difference between revisions
| Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | ||
| Line 14: | Line 14: | ||
| The program also writes the control and command registers, loads tables with short and long word counts, reads the data port when it is empty, decodes by DMA0 and DMA1 at several block sizes, and resets the MDEC part way through a decode. The steps that may hang run last, in the separate images mdecout_dbs64, mdecout_dbsback and mdecout_rst.[^run] | The program also writes the control and command registers, loads tables with short and long word counts, reads the data port when it is empty, decodes by DMA0 and DMA1 at several block sizes, and resets the MDEC part way through a decode. The steps that may hang run last, in the separate images mdecout_dbs64, mdecout_dbsback and mdecout_rst.[^run] | ||
| + | See also: | ||
| + | |||
| + | - [MDEC Status and Decode Timing](/tests/mdec-status-decode-timing/) | ||
| + | - [MDEC Block Timing](/tests/mdec-block-timing/) | ||
| + | |||
| ## Results | ## Results | ||
| Line 26: | Line 31: | ||
| ### Table Loads | ### Table Loads | ||
| − | MDEC(2) with bit 0 clear takes 16 words (the luminance table only) and with bit 0 set 32 words. MDEC(3) takes 32 words whatever its bits 0 to 15 hold. The low 16 bits of the status count down from the number of words minus 1 to 0 and then read FFFFh.[^h-tbl] | + | MDEC(2) with bit 0 clear takes 16 words (the luminance table only) and with bit 0 set 32 words. MDEC(3) takes 32 words whatever its bits 0 to 15 hold. The low 16 bits of the status count down from the number of words minus 1 to 0 and then read FFFFh.[^h-tbl] A table load cut short by a word does not end the load: the next word written, even a command, is taken as table data.[^h-tbl] |
| − | A table load cut short by a word does not end the load: the next word written, even a command, is taken as table data.[^h-tbl] | ||
| − | |||
| ### Decoding | ### Decoding | ||
| − | The step stream decoded by CPU gave 512 words at 15 bit and 768 at 24 bit. Every repeat of the test gave the same CRC. Written one word at a time with reads between, the stream gave the same 512 words and CRC.[^h-s15][^h-ear] | + | The step stream decoded by CPU gave 512 words at 15 bit and 768 at 24 bit. Every repeat of the test gave the same CRC. Written one word at a time with reads between, the stream gave the same 512 words and CRC.[^h-s15][^h-ear] Command bit 25 (bit 15 output) left 4-bit and 8-bit output unchanged, and the status showed it in bit 23.[^h-blk] |
| − | Command bit 25 (bit 15 output) left 4-bit and 8-bit output unchanged, and the status showed it in bit 23.[^h-blk] | ||
| − | |||
| A decode command whose word count cuts the stream gave fewer words than the stream holds. A count of 33 or 233 left the MDEC waiting for more input.[^h-odd] | A decode command whose word count cuts the stream gave fewer words than the stream holds. A count of 33 or 233 left the MDEC waiting for more input.[^h-odd] | ||