psx.wiki

Memory Control and Bus Timing: Difference between revisions

Revision as of 04:48, 23 October 2026
RemmyLee
(Main page: drop the Hardware Tests lede)		Revision as of 05:11, 23 October 2026
RemmyLee
(Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published)
Line 1:Line 1:
+---
+title: Memory Control and Bus Timing
+type: test
+summary: Measures the memory control registers, bus access times by delay setting, window sizes, RAM_SIZE and cache control.
+category: Hardware tests
+info: Machine = SCPH-5501
+info: Program = memctl
+---
+
+## Overview
+
+The program tests the [memory control](/hardware/memory-control/) registers at 1F801000h to 1F801023h, RAM_SIZE at 1F801060h and the cache control register at FFFE0130h. It reads every register at each width, writes the reserved bits, and times reads and writes of the BIOS ROM, the SPU, the CD-ROM and the [expansion port](/hardware/expansion-port/) for every read delay, write delay and COM_DELAY setting.[^run]
+
+A timing row is the number of system clock cycles for 100 turns of a loop around one instruction. A row with no load gives the cost of the loop. The groups that write undocumented bits save the card before each risky step, and the steps that may hang the console run last as separate images (memctl_end, memctl_end1 and memctl_end2).[^run]
+
+## Results
+
+### Register Values
+
+Table: Register values read at power-on settings
+
+| Register | Address | Value |
+| --- | --- | --- |
+| EXP1 base | 1F801000h | 1F000000h |
+| EXP2 base | 1F801004h | 1F802000h |
+| EXP1 delay/size | 1F801008h | 0013243Fh |
+| EXP3 delay/size | 1F80100Ch | 00003022h |
+| BIOS delay/size | 1F801010h | 0013243Fh |
+| SPU delay | 1F801014h | 200931E1h |
+| CDROM delay | 1F801018h | 00020843h |
+| EXP2 delay/size | 1F80101Ch | 00070777h |
+| COM_DELAY | 1F801020h | 00031125h |
+| RAM_SIZE | 1F801060h | 00000B88h |
+| Cache control | FFFE0130h | 0001E988h |
+
+RAM_SIZE is the one register that reads differently through KUSEG and KSEG0 or KSEG1. A word read of RAM_SIZE returned 00000B88h through KUSEG and 3C080B88h through KSEG0 or KSEG1. Three word reads in a row returned 0C040B88h twice and then 3C040B88h.[^h-rdb]
+
+### Reserved Bits
+
+In each delay/size register, bits 14 and 15, bits 24 to 27 and bit 29 keep the value written. Bits 21 to 23, 28 and 30 read 0. Bit 31 kept its value only in the EXP1 register. The EXP1 and EXP2 base registers keep their low bits.[^h-rsv][^h-rsx]
+
+Cache control keeps bits 12, 17 and 18 to 31, and bits 6 and 10 read 0.[^h-bcc]
+
+### Read Delay
+
+Each step of read delay adds one cycle to each bus access, so a word read from an 8-bit device costs 4 cycles more for each step.[^h-brt][^h-srt][^h-crt][^h-xrt]
+
+Table: 100 reads by read delay
+
+| Read | Read delay 0 | Read delay 1 | Each further step |
+| --- | --- | --- | --- |
+| BIOS lw | 1744 | 2141 | about +400 |
+| BIOS lhu | 1152 | 1352 | +200 |
+| SPU lw | 1444 | 1641 | about +200 |
+| CD-ROM lw | 1844 | 1844 | about +400 |
+| EXP1 lbu | 844 | 941 | about +100 |
+
+The read delay also decides whether the data is right. A BIOS word read with read delay 0 returned FFFFFFFFh and with read delay 1 951214FFh, and from read delay 2 up it returned the right value 19951204h. An SPU word read returned FFFFFFFFh with read delay 0 to 10 and the right value 00000000h from 11 up.[^h-brt][^h-srt]
+
+### COM_DELAY
+
+COM0 adds to SPU access times only from 7 up. SPU halfword reads took 2252 to 2266 cycles per 100 for COM0 0 to 6 and 99 more for each step above. COM0 on the BIOS (bit 8 set) and COM2 on the BIOS behaved the same way from 6 up.[^h-cma][^h-cmb]
+
+### Write Delay
+
+Table: 100 stores by write delay
+
+| Store | Write delay 0 | Write delay 1 | Each further step |
+| --- | --- | --- | --- |
+| SPU sh | 730 | 828 | about +98 |
+| SPU sw | 1323 | 1512 | about +196 |
+| CD-ROM sb | 455 | 461 | about +98 |
+| POST sb | 933 | 1031 | about +100 |
+
+A word store to the 16-bit SPU costs two accesses, so each step of write delay adds two cycles to it.[^h-wrt]
+
+### Scratchpad and RAM
+
+100 scratchpad loads or stores took 442 to 468 cycles against 353 for the empty loop. Each access therefore costs about one cycle. 100 RAM loads took 959 cycles, about 6 cycles each, and 100 RAM stores 462. The scratchpad reads the same through KUSEG and KSEG0, and 1F800100h and 9F800100h read the same word.[^h-scr]
+
+### Narrow Stores
+
+A halfword or byte store to a memory control register writes the whole register with the store's data register. A byte store at +1 shifts the data left by 8 bits. Stores at +2 and +3 shift it by 16 and 24 bits. A halfword store at +2 to cache control left it unchanged.[^h-pwr]
+
+### Window Sizes
+
+The size field of a delay/size register sets the window. A byte load one byte past the window raised exception 7 (bus error), and enlarging the window by one step made the same load succeed. With size 0 the first byte of a window is still readable. SPU and CD-ROM loads succeed with size 0.[^h-win]
+
+### RAM_SIZE
+
+RAM_SIZE keeps every bit written to it. Bits 7 and 8 made no difference to RAM loads from cached code. From uncached code, clearing bit 7 made 100 RAM loads take 2701 cycles against 2922.[^g-ram]
+
+Table: The word at 2F408h read through each 2 MB mirror
+
+| RAM_SIZE | +0 | +2 MB | +4 MB | +6 MB | +8 MB |
+| --- | --- | --- | --- | --- | --- |
+| 0B88h | the word | the word | the word | the word | 00000001h |
+| 0888h | the word | 00000001h | 00000001h | 00000001h | 00000001h |
+| 0C88h | the word | FFFFFFFFh | 00000001h | 00000001h | 00000001h |
+| 0F88h | the word | the word | the word | the word | FFFFFFFFh |
+
+### Cache Control
+
+Bit 16 (LDSCH) made RAM loads slower: 100 loads took 1063 cycles against 954, and 1164 with the loaded value used at once. The other bits tested (12 to 15, 17 and the block size) changed RAM and scratchpad load times by 30 cycles per 100 or less.[^h-bcc]
+
+With bit 3 cleared and bit 7 set, the scratchpad works as a data cache. A KSEG0 word load filled the scratchpad word at slot (address >> 2) AND FFh with the loaded value. A KSEG1 load and a KSEG0 store left the scratchpad unchanged.[^h-bcc]
+
+### Risky Steps
+
+A byte load from EXP3 with bit 31 of its delay register set returned FFh and did not hang. With RAM_SIZE 0288h a word at A002138Ch read the same as the word 2 MB above it. A word store to the scratchpad through KSEG1 (BF800100h) raised no exception.[^h-end]
+
+## Runs
+
+### 27 September 2026 card-c
+
+Raw output: [s004/00RUN.txt](/tests/raw/20260927T0000Z-5501a-card-c/memctl/s004/00RUN.txt) · [s004/01RDB.txt](/tests/raw/20260927T0000Z-5501a-card-c/memctl/s004/01RDB.txt) · [s004/02RSV.txt](/tests/raw/20260927T0000Z-5501a-card-c/memctl/s004/02RSV.txt) · [s004/03BRT.txt](/tests/raw/20260927T0000Z-5501a-card-c/memctl/s004/03BRT.txt) · [s004/04SRT.txt](/tests/raw/20260927T0000Z-5501a-card-c/memctl/s004/04SRT.txt) · [s004/05CRT.txt](/tests/raw/20260927T0000Z-5501a-card-c/memctl/s004/05CRT.txt) · [s004/06XRT.txt](/tests/raw/20260927T0000Z-5501a-card-c/memctl/s004/06XRT.txt) · [s004/07CMA.txt](/tests/raw/20260927T0000Z-5501a-card-c/memctl/s004/07CMA.txt) · [s004/08CMB.txt](/tests/raw/20260927T0000Z-5501a-card-c/memctl/s004/08CMB.txt) · [s004/09WRT.txt](/tests/raw/20260927T0000Z-5501a-card-c/memctl/s004/09WRT.txt) · [s004/10SCR.txt](/tests/raw/20260927T0000Z-5501a-card-c/memctl/s004/10SCR.txt) · [s004/11PWR.txt](/tests/raw/20260927T0000Z-5501a-card-c/memctl/s004/11PWR.txt) · [s004/12WIN.txt](/tests/raw/20260927T0000Z-5501a-card-c/memctl/s004/12WIN.txt) · [s004/13RSX.txt](/tests/raw/20260927T0000Z-5501a-card-c/memctl/s004/13RSX.txt) · [s004/14RAM.txt](/tests/raw/20260927T0000Z-5501a-card-c/memctl/s004/14RAM.txt) · [s005/15BCC.txt](/tests/raw/20260927T0000Z-5501a-card-c/memctl/s005/15BCC.txt) · [s005/16END.txt](/tests/raw/20260927T0000Z-5501a-card-c/memctl/s005/16END.txt)
+
+s004/00RUN.txt:
+
+```
+===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+16 tests
+A chain program, linked at 80010000
+Saved on the card in slot 2, from image 1
+COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 00000480 BDAM 00000000
+BPCM 00000000 SR 00000000 Cause 00000020 EPC 80111B44 PRId 00000002
+```
+
+s004/01RDB.txt:
+
+```
+===== 01 RDB MEMCTL READ BACK | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Memory control read back, every register at each width:
+EXP1 base 1F801000: lw 1F000000, KSEG0 1F000000, KSEG1 1F000000, lhu 0000 1F00, lbu 00 00 00 1F
+EXP2 base 1F801004: lw 1F802000, KSEG0 1F802000, KSEG1 1F802000, lhu 2000 1F80, lbu 00 20 80 1F
+EXP1 delay 1F801008: lw 0013243F, KSEG0 0013243F, KSEG1 0013243F, lhu 243F 0013, lbu 3F 24 13 00
+EXP3 delay 1F80100C: lw 00003022, KSEG0 00003022, KSEG1 00003022, lhu 3022 0000, lbu 22 30 00 00
+BIOS delay 1F801010: lw 0013243F, KSEG0 0013243F, KSEG1 0013243F, lhu 243F 0013, lbu 3F 24 13 00
+SPU delay 1F801014: lw 200931E1, KSEG0 200931E1, KSEG1 200931E1, lhu 31E1 2009, lbu E1 31 09 20
+CDROM delay 1F801018: lw 00020843, KSEG0 00020843, KSEG1 00020843, lhu 0843 0002, lbu 43 08 02 00
+EXP2 delay 1F80101C: lw 00070777, KSEG0 00070777, KSEG1 00070777, lhu 0777 0007, lbu 77 07 07 00
+COM_DELAY 1F801020: lw 00031125, KSEG0 00031125, KSEG1 00031125, lhu 1125 0003, lbu 25 11 03 00
+RAM_SIZE 1F801060: lw 00000B88, KSEG0 03E00B88, KSEG1 03E00B88, lhu 0B88 0000, lbu 88 0B 00 00
+cache control FFFE0130: lw 0001E988, lhu E988 0001, lbu 88 00 00 00
+RAM_SIZE three times: 8E070B88 34630B88 34630B88
+RAM_SIZE after a BIOS lw: 3C040B88
+CDROM 1F801800: lw 18181818, lhu 1818, lbu 18
+SPU 1F801C00: lw 00000000, lhu 0000 0000
+Done.
+```
+
+s004/02RSV.txt:
+
+```
+===== 02 RSV RESERVED BITS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Reserved bits, written and read back (the register put back at once):
+EXP1 base 1F0000FF: wrote 1F0000FF, read 1F0000FF, put back 1F000000, read 1F000000
+EXP1 base 1F000001: wrote 1F000001, read 1F000001, put back 1F000000, read 1F000000
+EXP1 base 1F07FFFF: wrote 1F07FFFF, read 1F07FFFF, put back 1F000000, read 1F000000
+EXP2 base 1F802001: wrote 1F802001, read 1F802001, put back 1F802000, read 1F802000
+EXP2 base 1F802080: wrote 1F802080, read 1F802080, put back 1F802000, read 1F802000
+EXP1 delay bits 14-15: wrote 0013E43F, read 0013E43F, put back 0013243F, read 0013243F
+EXP1 delay bits 21-23: wrote 00F3243F, read 0013243F, put back 0013243F, read 0013243F
+EXP1 delay bits 24-27: wrote 0F13243F, read 0F13243F, put back 0013243F, read 0013243F
+EXP1 delay bit 29: wrote 2013243F, read 2013243F, put back 0013243F, read 0013243F
+EXP1 delay low 16 all set: wrote 0013FFFF, read 0013FFFF, put back 0013243F, read 0013243F
+EXP3 delay bits 14-15: wrote 0000F022, read 0000F022, put back 00003022, read 00003022
+EXP3 delay bits 21-23: wrote 00E03022, read 00003022, put back 00003022, read 00003022
+EXP3 delay bits 24-27: wrote 0F003022, read 0F003022, put back 00003022, read 00003022
+EXP3 delay bit 29: wrote 20003022, read 20003022, put back 00003022, read 00003022
+EXP3 delay low 16 all set: wrote 0000FFFF, read 0000FFFF, put back 00003022, read 00003022
+EXP3 delay all zero: wrote 00000000, read 00000000, put back 00003022, read 00003022
+COM_DELAY bits 16-17 cleared: wrote 00001125, read 00001125, put back 00031125, read 00031125
+COM_DELAY bits 16-31 set: wrote FFFF1125, read 00031125, put back 00031125, read 00031125
+COM_DELAY bit 18 set: wrote 00071125, read 00031125, put back 00031125, read 00031125
+Done.
+```
+
+s004/03BRT.txt:
+
+```
+===== 03 BRT BIOS READ TIMING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+BIOS reads at BFC00100, BIOS delay 0013243F:
+no load: 360
+BIOS lw, read delay 0: 1755, value FFFFFFFF
+BIOS lw, read delay 1: 2154, value 951214FF
+BIOS lw, read delay 2: 2548, value 19951204
+BIOS lw, read delay 3: 2948, value 19951204
+BIOS lw, read delay 4: 3348, value 19951204
+BIOS lw, read delay 5: 3748, value 19951204
+BIOS lw, read delay 6: 4148, value 19951204
+BIOS lw, read delay 7: 4553, value 19951204
+BIOS lw, read delay 8: 4953, value 19951204
+BIOS lw, read delay 9: 5348, value 19951204
+BIOS lw, read delay 10: 5748, value 19951204
+BIOS lw, read delay 11: 6148, value 19951204
+BIOS lw, read delay 12: 6548, value 19951204
+BIOS lw, read delay 13: 6948, value 19951204
+BIOS lw, read delay 14: 7348, value 19951204
+BIOS lw, read delay 15: 7752, value 19951204
+BIOS lhu, read delay 0: 1145, value 0000FFFF
+BIOS lhu, read delay 1: 1348, value 000016FF
+BIOS lhu, read delay 2: 1554, value 00001204
+BIOS lhu, read delay 3: 1748, value 00001204
+BIOS lhu, read delay 4: 1950, value 00001204
+BIOS lhu, read delay 5: 2145, value 00001204
+BIOS lhu, read delay 6: 2345, value 00001204
+BIOS lhu, read delay 7: 2545, value 00001204
+BIOS lhu, read delay 8: 2745, value 00001204
+BIOS lhu, read delay 9: 2947, value 00001204
+BIOS lhu, read delay 10: 3145, value 00001204
+BIOS lhu, read delay 11: 3355, value 00001204
+BIOS lhu, read delay 12: 3545, value 00001204
+BIOS lhu, read delay 13: 3749, value 00001204
+BIOS lhu, read delay 14: 3945, value 00001204
+BIOS lhu, read delay 15: 4145, value 00001204
+BIOS lbu, read delay 0: 855, value 000000FF
+BIOS lbu, read delay 1: 960, value 000000FF
+BIOS lbu, read delay 2: 1055, value 00000004
+BIOS lbu, read delay 3: 1155, value 00000004
+BIOS lbu, read delay 4: 1257, value 00000004
+BIOS lbu, read delay 5: 1357, value 00000004
+BIOS lbu, read delay 6: 1455, value 00000004
+BIOS lbu, read delay 7: 1555, value 00000004
+BIOS lbu, read delay 8: 1655, value 00000004
+BIOS lbu, read delay 9: 1755, value 00000004
+BIOS lbu, read delay 10: 1855, value 00000004
+BIOS lbu, read delay 11: 1955, value 00000004
+BIOS lbu, read delay 12: 2065, value 00000004
+BIOS lbu, read delay 13: 2155, value 00000004
+BIOS lbu, read delay 14: 2261, value 00000004
+BIOS lbu, read delay 15: 2355, value 00000004
+BIOS lw, as set (0013243F): 2955, value 19951204
+BIOS lhu, as set (0013243F): 1745, value 00001204
+BIOS lbu, as set (0013243F): 1159, value 00000004
+BIOS lw, bit 8 flipped (0013253F): 4448, value 19951204
+BIOS lhu, bit 8 flipped (0013253F): 2251, value 00001204
+BIOS lbu, bit 8 flipped (0013253F): 1160, value 00000004
+BIOS lw, bit 9 flipped (0013263F): 2954, value 19951204
+BIOS lhu, bit 9 flipped (0013263F): 1745, value 00001204
+BIOS lbu, bit 9 flipped (0013263F): 1158, value 00000004
+BIOS lw, bit 10 flipped (0013203F): 2648, value 19951204
+BIOS lhu, bit 10 flipped (0013203F): 1645, value 00001204
+BIOS lbu, bit 10 flipped (0013203F): 1155, value 00000004
+BIOS lw, bit 11 flipped (00132C3F): 2948, value 19951204
+BIOS lhu, bit 11 flipped (00132C3F): 1745, value 00001204
+BIOS lbu, bit 11 flipped (00132C3F): 1159, value 00000004
+BIOS lw, bit 12 flipped (0013343F): 1748, value FF95FF04
+BIOS lhu, bit 12 flipped (0013343F): 1145, value 0000FF04
+BIOS lbu, bit 12 flipped (0013343F): 1155, value 00000004
+BIOS lw, bit 13 flipped (0013043F): 2955, value 04040404
+BIOS lhu, bit 13 flipped (0013043F): 1745, value 00000404
+BIOS lbu, bit 13 flipped (0013043F): 1155, value 00000004
+BIOS lw, write delay 0: 2948, value 19951204
+BIOS lw, write delay 1: 2948, value 19951204
+BIOS lw, write delay 2: 2948, value 19951204
+BIOS lw, write delay 3: 2948, value 19951204
+BIOS lw, write delay 4: 2953, value 19951204
+BIOS lw, write delay 5: 2948, value 19951204
+BIOS lw, write delay 6: 2953, value 19951204
+BIOS lw, write delay 7: 2948, value 19951204
+BIOS lw, write delay 8: 2948, value 19951204
+BIOS lw, write delay 9: 2948, value 19951204
+BIOS lw, write delay 10: 2948, value 19951204
+BIOS lw, write delay 11: 2954, value 19951204
+BIOS lw, write delay 12: 2954, value 19951204
+BIOS lw, write delay 13: 2948, value 19951204
+BIOS lw, write delay 14: 2948, value 19951204
+BIOS lw, write delay 15: 2948, value 19951204
+Done.
+```
+
+s004/04SRT.txt:
+
+```
+===== 04 SRT SPU READ TIMING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+SPU reads at 1F801C00, SPU delay 200931E1:
+SPU lw, read delay 0: 1465, value FFFFFFFF
+SPU lw, read delay 1: 1648, value FFFFFFFF
+SPU lw, read delay 2: 1848, value FFFFFFFF
+SPU lw, read delay 3: 2048, value FFFFFFFF
+SPU lw, read delay 4: 2252, value FFFFFFFF
+SPU lw, read delay 5: 2448, value FFFFFFFF
+SPU lw, read delay 6: 2653, value FFFFFFFF
+SPU lw, read delay 7: 2853, value FFFFFFFF
+SPU lw, read delay 8: 3048, value FFFFFFFF
+SPU lw, read delay 9: 3252, value FFFFFFFF
+SPU lw, read delay 10: 3448, value FFFFFFFF
+SPU lw, read delay 11: 3648, value 00000000
+SPU lw, read delay 12: 3848, value 00000000
+SPU lw, read delay 13: 4048, value 00000000
+SPU lw, read delay 14: 4248, value 00000000
+SPU lw, read delay 15: 4457, value 00000000
+SPU lhu, read delay 0: 845, value 0000FFFF
+SPU lhu, read delay 1: 950, value 0000FFFF
+SPU lhu, read delay 2: 1045, value 0000FFFF
+SPU lhu, read delay 3: 1147, value 0000FFFF
+SPU lhu, read delay 4: 1245, value 0000FFFF
+SPU lhu, read delay 5: 1345, value 0000FFFF
+SPU lhu, read delay 6: 1447, value 0000FFFF
+SPU lhu, read delay 7: 1554, value 0000FFFF
+SPU lhu, read delay 8: 1645, value 0000FFFF
+SPU lhu, read delay 9: 1745, value 0000FFFF
+SPU lhu, read delay 10: 1845, value 0000FFFF
+SPU lhu, read delay 11: 1945, value 00000000
+SPU lhu, read delay 12: 2045, value 00000000
+SPU lhu, read delay 13: 2145, value 00000000
+SPU lhu, read delay 14: 2245, value 00000000
+SPU lhu, read delay 15: 2345, value 00000000
+SPU lbu, read delay 0: 855, value 000000FF
+SPU lbu, read delay 1: 955, value 000000FF
+SPU lbu, read delay 2: 1055, value 000000FF
+SPU lbu, read delay 3: 1159, value 000000FF
+SPU lbu, read delay 4: 1255, value 000000FF
+SPU lbu, read delay 5: 1355, value 000000FF
+SPU lbu, read delay 6: 1455, value 000000FF
+SPU lbu, read delay 7: 1555, value 000000FF
+SPU lbu, read delay 8: 1655, value 000000FF
+SPU lbu, read delay 9: 1755, value 000000FF
+SPU lbu, read delay 10: 1855, value 000000FF
+SPU lbu, read delay 11: 1955, value 00000000
+SPU lbu, read delay 12: 2055, value 00000000
+SPU lbu, read delay 13: 2155, value 00000000
+SPU lbu, read delay 14: 2256, value 00000000
+SPU lbu, read delay 15: 2355, value 00000000
+SPU lw, as set (200931E1): 4255, value 00000000
+SPU lhu, as set (200931E1): 2245, value 00000000
+SPU lbu, as set (200931E1): 2255, value 00000000
+SPU lw, bit 8 flipped (200930E1): 3850, value 00000000
+SPU lhu, bit 8 flipped (200930E1): 2245, value 00000000
+SPU lbu, bit 8 flipped (200930E1): 2255, value 00000000
+SPU lw, bit 9 flipped (200933E1): 4248, value 00000000
+SPU lhu, bit 9 flipped (200933E1): 2245, value 00000000
+SPU lbu, bit 9 flipped (200933E1): 2255, value 00000000
+SPU lw, bit 10 flipped (200935E1): 4452, value 00000000
+SPU lhu, bit 10 flipped (200935E1): 2251, value 00000000
+SPU lbu, bit 10 flipped (200935E1): 2255, value 00000000
+SPU lw, bit 11 flipped (200939E1): 4248, value 00000000
+SPU lhu, bit 11 flipped (200939E1): 2245, value 00000000
+SPU lbu, bit 11 flipped (200939E1): 2255, value 00000000
+SPU lw, bit 12 flipped (200921E1): 8248, value 00000000
+SPU lhu, bit 12 flipped (200921E1): 4251, value 00000000
+SPU lbu, bit 12 flipped (200921E1): 2258, value 00000000
+SPU lw, bit 13 flipped (200911E1): 4255, value 00000000
+SPU lhu, bit 13 flipped (200911E1): 2245, value 00000000
+SPU lbu, bit 13 flipped (200911E1): 2255, value 00000000
+SPU lw, bit 29 flipped (000931E1): 4248, value 00000000
+SPU lhu, bit 29 flipped (000931E1): 2251, value 00000000
+SPU lbu, bit 29 flipped (000931E1): 2255, value 00000000
+SPU lhu, bits 24-27 = F: 2245, value 00000000
+SPU lhu, bits 24-27 = 2 (220931E1h): 2232, value 00000000
+Done.
+```
+
+s004/05CRT.txt:
+
+```
+===== 05 CRT CDROM READ TIMING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+CD-ROM reads at 1F801800, CDROM delay 00020843:
+CDROM lw, read delay 0: 1865, value 18181818
+CDROM lw, read delay 1: 1848, value 18181818
+CDROM lw, read delay 2: 2248, value 18181818
+CDROM lw, read delay 3: 2648, value 18181818
+CDROM lw, read delay 4: 3048, value 18181818
+CDROM lw, read delay 5: 3448, value 18181818
+CDROM lw, read delay 6: 3848, value 18181818
+CDROM lw, read delay 7: 4248, value 18181818
+CDROM lw, read delay 8: 4648, value 18181818
+CDROM lw, read delay 9: 5048, value 18181818
+CDROM lw, read delay 10: 5448, value 18181818
+CDROM lw, read delay 11: 5848, value 18181818
+CDROM lw, read delay 12: 6248, value 18181818
+CDROM lw, read delay 13: 6648, value 18181818
+CDROM lw, read delay 14: 7048, value 18181818
+CDROM lw, read delay 15: 7448, value 18181818
+CDROM lhu, read delay 0: 1245, value 00001818
+CDROM lhu, read delay 1: 1245, value 00001818
+CDROM lhu, read delay 2: 1448, value 00001818
+CDROM lhu, read delay 3: 1645, value 00001818
+CDROM lhu, read delay 4: 1845, value 00001818
+CDROM lhu, read delay 5: 2045, value 00001818
+CDROM lhu, read delay 6: 2245, value 00001818
+CDROM lhu, read delay 7: 2445, value 00001818
+CDROM lhu, read delay 8: 2645, value 00001818
+CDROM lhu, read delay 9: 2845, value 00001818
+CDROM lhu, read delay 10: 3045, value 00001818
+CDROM lhu, read delay 11: 3245, value 00001818
+CDROM lhu, read delay 12: 3445, value 00001818
+CDROM lhu, read delay 13: 3645, value 00001818
+CDROM lhu, read delay 14: 3845, value 00001818
+CDROM lhu, read delay 15: 4045, value 00001818
+CDROM lbu, read delay 0: 955, value 00000018
+CDROM lbu, read delay 1: 955, value 00000018
+CDROM lbu, read delay 2: 1055, value 00000018
+CDROM lbu, read delay 3: 1155, value 00000018
+CDROM lbu, read delay 4: 1255, value 00000018
+CDROM lbu, read delay 5: 1357, value 00000018
+CDROM lbu, read delay 6: 1455, value 00000018
+CDROM lbu, read delay 7: 1555, value 00000018
+CDROM lbu, read delay 8: 1661, value 00000018
+CDROM lbu, read delay 9: 1755, value 00000018
+CDROM lbu, read delay 10: 1860, value 00000018
+CDROM lbu, read delay 11: 1955, value 00000018
+CDROM lbu, read delay 12: 2055, value 00000018
+CDROM lbu, read delay 13: 2155, value 00000018
+CDROM lbu, read delay 14: 2255, value 00000018
+CDROM lbu, read delay 15: 2355, value 00000018
+CDROM lw, as set (00020843): 3055, value 18181818
+CDROM lhu, as set (00020843): 1850, value 00001818
+CDROM lbu, as set (00020843): 1255, value 00000018
+CDROM lw, bit 8 flipped (00020943): 4252, value 18181818
+CDROM lhu, bit 8 flipped (00020943): 2245, value 00001818
+CDROM lbu, bit 8 flipped (00020943): 1261, value 00000018
+CDROM lw, bit 9 flipped (00020A43): 3048, value 18181818
+CDROM lhu, bit 9 flipped (00020A43): 1845, value 00001818
+CDROM lbu, bit 9 flipped (00020A43): 1258, value 00000018
+CDROM lw, bit 10 flipped (00020C43): 3358, value 18181818
+CDROM lhu, bit 10 flipped (00020C43): 1945, value 00001818
+CDROM lbu, bit 10 flipped (00020C43): 1255, value 00000018
+CDROM lw, bit 11 flipped (00020043): 3048, value 18181818
+CDROM lhu, bit 11 flipped (00020043): 1849, value 00001818
+CDROM lbu, bit 11 flipped (00020043): 1255, value 00000018
+CDROM lw, bit 12 flipped (00021843): 1855, value FF18FF18
+CDROM lhu, bit 12 flipped (00021843): 1245, value 0000FF18
+CDROM lbu, bit 12 flipped (00021843): 1255, value 00000018
+Done.
+```
+
+s004/06XRT.txt:
+
+```
+===== 06 XRT EXP READ TIMING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Expansion reads, EXP1 0013243F EXP2 00070777 EXP3 00003022:
+EXP1 lbu, read delay 0: 867, value 000000FF
+EXP1 lbu, read delay 1: 955, value 000000FF
+EXP1 lbu, read delay 2: 1055, value 000000FF
+EXP1 lbu, read delay 3: 1155, value 000000FF
+EXP1 lbu, read delay 4: 1255, value 000000FF
+EXP1 lbu, read delay 5: 1360, value 000000FF
+EXP1 lbu, read delay 6: 1455, value 000000FF
+EXP1 lbu, read delay 7: 1555, value 000000FF
+EXP1 lbu, read delay 8: 1655, value 000000FF
+EXP1 lbu, read delay 9: 1760, value 000000FF
+EXP1 lbu, read delay 10: 1855, value 000000FF
+EXP1 lbu, read delay 11: 1955, value 000000FF
+EXP1 lbu, read delay 12: 2055, value 000000FF
+EXP1 lbu, read delay 13: 2157, value 000000FF
+EXP1 lbu, read delay 14: 2257, value 000000FF
+EXP1 lbu, read delay 15: 2355, value 000000FF
+EXP2 lbu, read delay 0: 855, value 000000FF
+EXP2 lbu, read delay 1: 955, value 000000FF
+EXP2 lbu, read delay 2: 1055, value 000000FF
+EXP2 lbu, read delay 3: 1157, value 000000FF
+EXP2 lbu, read delay 4: 1260, value 000000FF
+EXP2 lbu, read delay 5: 1355, value 000000FF
+EXP2 lbu, read delay 6: 1460, value 000000FF
+EXP2 lbu, read delay 7: 1557, value 000000FF
+EXP2 lbu, read delay 8: 1655, value 000000FF
+EXP2 lbu, read delay 9: 1755, value 000000FF
+EXP2 lbu, read delay 10: 1855, value 000000FF
+EXP2 lbu, read delay 11: 1955, value 000000FF
+EXP2 lbu, read delay 12: 2055, value 000000FF
+EXP2 lbu, read delay 13: 2155, value 000000FF
+EXP2 lbu, read delay 14: 2255, value 000000FF
+EXP2 lbu, read delay 15: 2355, value 000000FF
+EXP2 lw, read delay 0: 3255, value FFFFFFFF
+EXP2 lw, read delay 1: 3648, value FFFFFFFF
+EXP2 lw, read delay 2: 4048, value FFFFFFFF
+EXP2 lw, read delay 3: 4448, value FFFFFFFF
+EXP2 lw, read delay 4: 4848, value FFFFFFFF
+EXP2 lw, read delay 5: 5248, value FFFFFFFF
+EXP2 lw, read delay 6: 5659, value FFFFFFFF
+EXP2 lw, read delay 7: 6048, value FFFFFFFF
+EXP2 lw, read delay 8: 6448, value FFFFFFFF
+EXP2 lw, read delay 9: 6848, value FFFFFFFF
+EXP2 lw, read delay 10: 7248, value FFFFFFFF
+EXP2 lw, read delay 11: 7655, value FFFFFFFF
+EXP2 lw, read delay 12: 8048, value FFFFFFFF
+EXP2 lw, read delay 13: 8448, value FFFFFFFF
+EXP2 lw, read delay 14: 8853, value FFFFFFFF
+EXP2 lw, read delay 15: 9253, value FFFFFFFF
+EXP3 lbu, read delay 0: 855, value 000000FF
+EXP3 lbu, read delay 1: 955, value 000000FF
+EXP3 lbu, read delay 2: 1055, value 000000FF
+EXP3 lbu, read delay 3: 1160, value 000000FF
+EXP3 lbu, read delay 4: 1260, value 000000FF
+EXP3 lbu, read delay 5: 1355, value 000000FF
+EXP3 lbu, read delay 6: 1460, value 000000FF
+EXP3 lbu, read delay 7: 1557, value 000000FF
+EXP3 lbu, read delay 8: 1655, value 000000FF
+EXP3 lbu, read delay 9: 1755, value 000000FF
+EXP3 lbu, read delay 10: 1855, value 000000FF
+EXP3 lbu, read delay 11: 1955, value 000000FF
+EXP3 lbu, read delay 12: 2055, value 000000FF
+EXP3 lbu, read delay 13: 2155, value 000000FF
+EXP3 lbu, read delay 14: 2255, value 000000FF
+EXP3 lbu, read delay 15: 2355, value 000000FF
+EXP3 lw, read delay 0: 1048, value FFFFFFFF
+EXP3 lw, read delay 1: 1255, value FFFFFFFF
+EXP3 lw, read delay 2: 1448, value FFFFFFFF
+EXP3 lw, read delay 3: 1648, value FFFFFFFF
+EXP3 lw, read delay 4: 1848, value FFFFFFFF
+EXP3 lw, read delay 5: 2048, value FFFFFFFF
+EXP3 lw, read delay 6: 2248, value FFFFFFFF
+EXP3 lw, read delay 7: 2448, value FFFFFFFF
+EXP3 lw, read delay 8: 2648, value FFFFFFFF
+EXP3 lw, read delay 9: 2848, value FFFFFFFF
+EXP3 lw, read delay 10: 3048, value FFFFFFFF
+EXP3 lw, read delay 11: 3248, value FFFFFFFF
+EXP3 lw, read delay 12: 3453, value FFFFFFFF
+EXP3 lw, read delay 13: 3650, value FFFFFFFF
+EXP3 lw, read delay 14: 3848, value FFFFFFFF
+EXP3 lw, read delay 15: 4048, value FFFFFFFF
+Done.
+```
+
+s004/07CMA.txt:
+
+```
+===== 07 CMA COM0 COM1 SWEEP | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+COM_DELAY 00031125; COM0 with SPU (bit 8 set) and BIOS (bit 8 set here):
+SPU lhu, COM0 0: 2255
+SPU lhu, COM0 1: 2250
+SPU lhu, COM0 2: 2245
+SPU lhu, COM0 3: 2245
+SPU lhu, COM0 4: 2245
+SPU lhu, COM0 5: 2247
+SPU lhu, COM0 6: 2245
+SPU lhu, COM0 7: 2344
+SPU lhu, COM0 8: 2448
+SPU lhu, COM0 9: 2547
+SPU lhu, COM0 10: 2641
+SPU lhu, COM0 11: 2744
+SPU lhu, COM0 12: 2839
+SPU lhu, COM0 13: 2938
+SPU lhu, COM0 14: 3037
+SPU lhu, COM0 15: 3141
+SPU lw, COM0 0: 3855
+SPU lw, COM0 1: 3848
+SPU lw, COM0 2: 3948
+SPU lw, COM0 3: 4054
+SPU lw, COM0 4: 4148
+SPU lw, COM0 5: 4248
+SPU lw, COM0 6: 4348
+SPU lw, COM0 7: 4549
+SPU lw, COM0 8: 4746
+SPU lw, COM0 9: 4945
+SPU lw, COM0 10: 5144
+SPU lw, COM0 11: 5343
+SPU lw, COM0 12: 5542
+SPU lw, COM0 13: 5741
+SPU lw, COM0 14: 5945
+SPU lw, COM0 15: 6139
+BIOS+bit8 lbu, COM0 0: 1160
+BIOS+bit8 lbu, COM0 1: 1155
+BIOS+bit8 lbu, COM0 2: 1161
+BIOS+bit8 lbu, COM0 3: 1155
+BIOS+bit8 lbu, COM0 4: 1155
+BIOS+bit8 lbu, COM0 5: 1159
+BIOS+bit8 lbu, COM0 6: 1253
+BIOS+bit8 lbu, COM0 7: 1351
+BIOS+bit8 lbu, COM0 8: 1449
+BIOS+bit8 lbu, COM0 9: 1547
+BIOS+bit8 lbu, COM0 10: 1645
+BIOS+bit8 lbu, COM0 11: 1743
+BIOS+bit8 lbu, COM0 12: 1841
+BIOS+bit8 lbu, COM0 13: 1940
+BIOS+bit8 lbu, COM0 14: 2044
+BIOS+bit8 lbu, COM0 15: 2138
+BIOS+bit8 lw, COM0 0: 2948
+BIOS+bit8 lw, COM0 1: 3248
+BIOS+bit8 lw, COM0 2: 3548
+BIOS+bit8 lw, COM0 3: 3848
+BIOS+bit8 lw, COM0 4: 4148
+BIOS+bit8 lw, COM0 5: 4448
+BIOS+bit8 lw, COM0 6: 4847
+BIOS+bit8 lw, COM0 7: 5246
+BIOS+bit8 lw, COM0 8: 5645
+BIOS+bit8 lw, COM0 9: 6044
+BIOS+bit8 lw, COM0 10: 6443
+BIOS+bit8 lw, COM0 11: 6848
+BIOS+bit8 lw, COM0 12: 7241
+BIOS+bit8 lw, COM0 13: 7640
+BIOS+bit8 lw, COM0 14: 8043
+BIOS+bit8 lw, COM0 15: 8438
+COM1 with EXP2 (delay 00070777, bit 9 set):
+EXP2 lbu, COM1 0: 1555
+EXP2 lbu, COM1 1: 1555
+EXP2 lbu, COM1 2: 1555
+EXP2 lbu, COM1 3: 1555
+EXP2 lbu, COM1 4: 1555
+EXP2 lbu, COM1 5: 1555
+EXP2 lbu, COM1 6: 1555
+EXP2 lbu, COM1 7: 1555
+EXP2 lbu, COM1 8: 1555
+EXP2 lbu, COM1 9: 1555
+EXP2 lbu, COM1 10: 1555
+EXP2 lbu, COM1 11: 1563
+EXP2 lbu, COM1 12: 1555
+EXP2 lbu, COM1 13: 1555
+EXP2 lbu, COM1 14: 1555
+EXP2 lbu, COM1 15: 1555
+Bits 16-17:
+BIOS lw, COM bits 16-17 = 0: 2948
+SPU lhu, COM bits 16-17 = 0: 2245
+CDROM lbu, COM bits 16-17 = 0: 1255
+EXP2 lbu, COM bits 16-17 = 0: 1557
+BIOS lw, COM bits 16-17 = 1: 2951
+SPU lhu, COM bits 16-17 = 1: 2245
+CDROM lbu, COM bits 16-17 = 1: 1255
+EXP2 lbu, COM bits 16-17 = 1: 1555
+BIOS lw, COM bits 16-17 = 2: 2951
+SPU lhu, COM bits 16-17 = 2: 2245
+CDROM lbu, COM bits 16-17 = 2: 1255
+EXP2 lbu, COM bits 16-17 = 2: 1555
+BIOS lw, COM bits 16-17 = 3: 2951
+SPU lhu, COM bits 16-17 = 3: 2245
+CDROM lbu, COM bits 16-17 = 3: 1255
+EXP2 lbu, COM bits 16-17 = 3: 1560
+Done.
+```
+
+s004/08CMB.txt:
+
+```
+===== 08 CMB COM2 COM3 SWEEP | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+COM2 with BIOS (bit 10 set) and CDROM (bit 10 set here):
+BIOS lbu, COM2 0: 1165
+BIOS lbu, COM2 1: 1155
+BIOS lbu, COM2 2: 1160
+BIOS lbu, COM2 3: 1161
+BIOS lbu, COM2 4: 1160
+BIOS lbu, COM2 5: 1161
+BIOS lbu, COM2 6: 1258
+BIOS lbu, COM2 7: 1357
+BIOS lbu, COM2 8: 1449
+BIOS lbu, COM2 9: 1547
+BIOS lbu, COM2 10: 1645
+BIOS lbu, COM2 11: 1743
+BIOS lbu, COM2 12: 1841
+BIOS lbu, COM2 13: 1940
+BIOS lbu, COM2 14: 2039
+BIOS lbu, COM2 15: 2138
+BIOS lw, COM2 0: 2655
+BIOS lw, COM2 1: 2948
+BIOS lw, COM2 2: 3248
+BIOS lw, COM2 3: 3548
+BIOS lw, COM2 4: 3858
+BIOS lw, COM2 5: 4148
+BIOS lw, COM2 6: 4547
+BIOS lw, COM2 7: 4946
+BIOS lw, COM2 8: 5345
+BIOS lw, COM2 9: 5744
+BIOS lw, COM2 10: 6143
+BIOS lw, COM2 11: 6547
+BIOS lw, COM2 12: 6941
+BIOS lw, COM2 13: 7340
+BIOS lw, COM2 14: 7744
+BIOS lw, COM2 15: 8138
+CDROM+bit10 lbu, COM2 0: 1260
+CDROM+bit10 lbu, COM2 1: 1255
+CDROM+bit10 lbu, COM2 2: 1255
+CDROM+bit10 lbu, COM2 3: 1255
+CDROM+bit10 lbu, COM2 4: 1255
+CDROM+bit10 lbu, COM2 5: 1255
+CDROM+bit10 lbu, COM2 6: 1357
+CDROM+bit10 lbu, COM2 7: 1451
+CDROM+bit10 lbu, COM2 8: 1549
+CDROM+bit10 lbu, COM2 9: 1647
+CDROM+bit10 lbu, COM2 10: 1745
+CDROM+bit10 lbu, COM2 11: 1843
+CDROM+bit10 lbu, COM2 12: 1945
+CDROM+bit10 lbu, COM2 13: 2046
+CDROM+bit10 lbu, COM2 14: 2139
+CDROM+bit10 lbu, COM2 15: 2238
+COM3 with CDROM (bit 11 set) and BIOS (bit 11 set here):
+CDROM lbu, COM3 0: 1255
+CDROM lbu, COM3 1: 1261
+CDROM lbu, COM3 2: 1255
+CDROM lbu, COM3 3: 1255
+CDROM lbu, COM3 4: 1255
+CDROM lbu, COM3 5: 1355
+CDROM lbu, COM3 6: 1458
+CDROM lbu, COM3 7: 1555
+CDROM lbu, COM3 8: 1655
+CDROM lbu, COM3 9: 1755
+CDROM lbu, COM3 10: 1855
+CDROM lbu, COM3 11: 1960
+CDROM lbu, COM3 12: 2055
+CDROM lbu, COM3 13: 2155
+CDROM lbu, COM3 14: 2255
+CDROM lbu, COM3 15: 2355
+CDROM lw, COM3 0: 3055
+CDROM lw, COM3 1: 3048
+CDROM lw, COM3 2: 3050
+CDROM lw, COM3 3: 3051
+CDROM lw, COM3 4: 3048
+CDROM lw, COM3 5: 3448
+CDROM lw, COM3 6: 3854
+CDROM lw, COM3 7: 4253
+CDROM lw, COM3 8: 4648
+CDROM lw, COM3 9: 5048
+CDROM lw, COM3 10: 5448
+CDROM lw, COM3 11: 5848
+CDROM lw, COM3 12: 6248
+CDROM lw, COM3 13: 6648
+CDROM lw, COM3 14: 7048
+CDROM lw, COM3 15: 7448
+BIOS+bit11 lbu, COM3 0: 1155
+BIOS+bit11 lbu, COM3 1: 1155
+BIOS+bit11 lbu, COM3 2: 1155
+BIOS+bit11 lbu, COM3 3: 1158
+BIOS+bit11 lbu, COM3 4: 1255
+BIOS+bit11 lbu, COM3 5: 1359
+BIOS+bit11 lbu, COM3 6: 1455
+BIOS+bit11 lbu, COM3 7: 1555
+BIOS+bit11 lbu, COM3 8: 1655
+BIOS+bit11 lbu, COM3 9: 1755
+BIOS+bit11 lbu, COM3 10: 1855
+BIOS+bit11 lbu, COM3 11: 1960
+BIOS+bit11 lbu, COM3 12: 2059
+BIOS+bit11 lbu, COM3 13: 2155
+BIOS+bit11 lbu, COM3 14: 2258
+BIOS+bit11 lbu, COM3 15: 2355
+Done.
+```
+
+s004/09WRT.txt:
+
+```
+===== 09 WRT WRITE TIMING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Stores by write delay; SPU word 00000000, CD index 0:
+SPU sh, as set: 827
+CDROM sb, as set: 633
+POST sb, as set: 1590
+SPU sh, write delay 0: 721
+SPU sh, write delay 1: 819
+SPU sh, write delay 2: 917
+SPU sh, write delay 3: 1015
+SPU sh, write delay 4: 1102
+SPU sh, write delay 5: 1199
+SPU sh, write delay 6: 1296
+SPU sh, write delay 7: 1393
+SPU sh, write delay 8: 1490
+SPU sh, write delay 9: 1587
+SPU sh, write delay 10: 1684
+SPU sh, write delay 11: 1781
+SPU sh, write delay 12: 1878
+SPU sh, write delay 13: 1975
+SPU sh, write delay 14: 2072
+SPU sh, write delay 15: 2169
+SPU sw, write delay 0: 1299
+SPU sw, write delay 1: 1493
+SPU sw, write delay 2: 1687
+SPU sw, write delay 3: 1881
+SPU sw, write delay 4: 2075
+SPU sw, write delay 5: 2269
+SPU sw, write delay 6: 2463
+SPU sw, write delay 7: 2660
+SPU sw, write delay 8: 2851
+SPU sw, write delay 9: 3045
+SPU sw, write delay 10: 3242
+SPU sw, write delay 11: 3433
+SPU sw, write delay 12: 3630
+SPU sw, write delay 13: 3821
+SPU sw, write delay 14: 4015
+SPU sw, write delay 15: 4209
+CDROM sb, write delay 0: 453
+CDROM sb, write delay 1: 453
+CDROM sb, write delay 2: 541
+CDROM sb, write delay 3: 639
+CDROM sb, write delay 4: 730
+CDROM sb, write delay 5: 827
+CDROM sb, write delay 6: 924
+CDROM sb, write delay 7: 1022
+CDROM sb, write delay 8: 1120
+CDROM sb, write delay 9: 1206
+CDROM sb, write delay 10: 1303
+CDROM sb, write delay 11: 1400
+CDROM sb, write delay 12: 1497
+CDROM sb, write delay 13: 1594
+CDROM sb, write delay 14: 1691
+CDROM sb, write delay 15: 1791
+POST sb, write delay 0: 920
+POST sb, write delay 1: 1018
+POST sb, write delay 2: 1116
+POST sb, write delay 3: 1202
+POST sb, write delay 4: 1299
+POST sb, write delay 5: 1396
+POST sb, write delay 6: 1493
+POST sb, write delay 7: 1590
+POST sb, write delay 8: 1687
+POST sb, write delay 9: 1784
+POST sb, write delay 10: 1881
+POST sb, write delay 11: 1978
+POST sb, write delay 12: 2075
+POST sb, write delay 13: 2172
+POST sb, write delay 14: 2269
+POST sb, write delay 15: 2366
+POST sb, COM1 0: 1396
+POST sb, COM1 1: 1493
+POST sb, COM1 2: 1590
+POST sb, COM1 3: 1687
+POST sb, COM1 4: 1784
+POST sb, COM1 5: 1881
+POST sb, COM1 6: 1978
+POST sb, COM1 7: 2075
+POST sb, COM1 8: 2172
+POST sb, COM1 9: 2269
+POST sb, COM1 10: 2372
+POST sb, COM1 11: 2463
+POST sb, COM1 12: 2560
+POST sb, COM1 13: 2663
+POST sb, COM1 14: 2754
+POST sb, COM1 15: 2851
+SPU sh, bit 9 (hold) set: 1015
+CDROM sb, bit 9 (hold) set: 818
+POST sb, bit 9 (hold) cleared: 1396
+SPU word after: 00000000; CD index after: 0
+SPU word put back: 00000000; CD index: 0
+Done.
+```
+
+s004/10SCR.txt:
+
+```
+===== 10 SCR SCRATCHPAD | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Scratchpad and RAM loads and stores (100 each):
+no load: 360
+scratchpad KUSEG lw: 462
+scratchpad KUSEG lhu: 444
+scratchpad KUSEG lbu: 458
+scratchpad KUSEG lw, use: 546
+scratchpad KUSEG sw: 453
+scratchpad KUSEG sh: 446
+scratchpad KUSEG sb: 453
+scratchpad KSEG0 lw: 440
+scratchpad KSEG0 lw, use: 546
+scratchpad KSEG0 sw: 453
+scratchpad last word lw: 440
+RAM KSEG0 lw: 951
+RAM KSEG0 lw, use: 958
+RAM KSEG0 sw: 455
+RAM KSEG1 lw: 946
+Code from KSEG1 (uncached):
+uncached, no load: 1902
+uncached, scratchpad lw: 2513
+uncached, scratchpad sw: 2513
+uncached, RAM lw: 2917
+scratchpad 1F800100 5C4A0100, 9F800100 5C4A0100, 1F8003FC 5C4A03FC, 9F8003FC 5C4A03FC
+Done.
+```
+
+s004/11PWR.txt:
+
+```
+===== 11 PWR NARROW WRITES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Narrow stores, EXP3 delay 00003022, COM_DELAY 00031125, BCC 0001E988:
+EXP3 delay sh +0: rt 05003022, read 05003022, put back 00003022
+EXP3 delay sb +0: rt 05003022, read 05003022, put back 00003022
+EXP3 delay sh +2: rt 00003022, read 20020000, put back 00003022
+EXP3 delay sb +1: rt 00003022, read 00102200, put back 00003022
+EXP3 delay sb +2: rt 00003022, read 20020000, put back 00003022
+EXP3 delay sb +3: rt 00003022, read 22000000, put back 00003022
+COM_DELAY sh +0: rt FFFF1125, read 00031125, put back 00031125
+COM_DELAY sb +1: rt 00031125, read 00012500, put back 00031125
+RAM_SIZE sh +0: rt ABCD0B88, read ABCD0B88, put back 00000B88
+BCC sh +0: rt 0005E988, read 0005E988, put back 0001E988
+BCC sb +0: rt 0005E988, read 0005E988, put back 0001E988
+BCC sh +2: rt 0005E988, read 0001E988, put back 0001E988
+BCC sb +1: rt 0005E988, read 0001E988, put back 0001E988
+Done.
+```
+
+s004/12WIN.txt:
+
+```
+===== 12 WIN WINDOW SIZE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Window sizes and bit 28:
+EXP3 lbu 1FA00000, size 0: none, reg 000000FF, register after 00003022
+EXP3 lbu 1FA00001, size 0: exception 7, reg 5A5A5A5A, register after 00003022
+EXP3 lbu 1FA00002, size 0: exception 7, reg 5A5A5A5A, register after 00003022
+EXP3 lhu 1FA00002, size 0: exception 7, reg 5A5A5A5A, register after 00003022
+EXP3 delay bit 28 written 1: wrote 10003022, read 00003022, put back 00003022, read 00003022
+EXP3 lbu 1FA00001, size 1: none, reg 000000FF, register after 00013022
+EXP3 lbu 1FA00002, size 1: exception 7, reg 5A5A5A5A, register after 00013022
+EXP3 lbu 1FBFFFFF, size 15h: none, reg 000000FF, register after 00153022
+EXP2 lbu 1F80207F, size 7: none, reg 000000FF, register after 00070777
+EXP2 lbu 1F802080, size 7: exception 7, reg 5A5A5A5A, register after 00070777
+EXP2 lbu 1F802080, size 0Dh: none, reg 000000FF, register after 000D0777
+EXP2 lbu 1F803FFF, size 0Dh: none, reg 000000FF, register after 000D0777
+EXP2 lbu 1F802001, size 0: exception 7, reg 5A5A5A5A, register after 00000777
+EXP1 lbu 1F07FFFF, size 13h: none, reg 000000FF, register after 0013243F
+EXP1 lbu 1F080000, size 13h: exception 7, reg 5A5A5A5A, register after 0013243F
+EXP1 lbu 1F080000, size 14h: none, reg 000000FF, register after 0014243F
+EXP1 lbu 1F000001, size 0: exception 7, reg 5A5A5A5A, register after 0000243F
+SPU lhu 1F801C02, size 0: none, reg 00000000, register after 200031E1
+SPU lhu 1F801D80, size 0: none, reg 00000000, register after 200031E1
+CDROM lbu 1F801803, size 0: none, reg 000000FF, register after 00000843
+BIOS lw BFC80100, size 13h: exception 7, reg 5A5A5A5A, register after 0013243F
+BIOS lw BFC80100, size 14h: none, reg 19951204, register after 0014243F
+BIOS lw BFF80100, size 16h: none, reg 19951204, register after 0016243F
+BIOS lw BFE00100, size 16h: none, reg 19951204, register after 0016243F
+After: EXP1 0013243F EXP2 00070777 EXP3 00003022 BIOS 0013243F SPU 200931E1 CDROM 00020843
+KSEG2 lw FFFE0000: none, reg 00000000, register after 0001E988
+KSEG2 lw FFFE0100: none, reg 00000000, register after 0001E988
+KSEG2 lw FFFE0134: none, reg 00000000, register after 0001E988
+KSEG2 lw FFFE013C: none, reg 00000000, register after 0001E988
+KSEG2 lw FFFE0140: exception 7, reg 5A5A5A5A, register after 0001E988
+Done.
+```
+
+s004/13RSX.txt:
+
+```
+===== 13 RSX RESERVED BITS LIVE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Reserved bits of the registers in use:
+EXP1 delay bit 28: wrote 1013243F, read 0013243F, put back 0013243F, read 0013243F
+EXP1 delay bit 30: wrote 4013243F, read 0013243F, put back 0013243F, read 0013243F
+EXP1 delay bit 31: wrote 8013243F, read 8013243F, put back 0013243F, read 0013243F
+EXP3 delay bit 28: wrote 10003022, read 00003022, put back 00003022, read 00003022
+EXP3 delay bit 30: wrote 40003022, read 00003022, put back 00003022, read 00003022
+EXP3 delay bit 31: wrote 80003022, read 00003022, put back 00003022, read 00003022
+EXP2 delay bits 14-15: wrote 0007C777, read 0007C777, put back 00070777, read 00070777
+EXP2 delay bits 21-23: wrote 00E70777, read 00070777, put back 00070777, read 00070777
+EXP2 delay bits 24-27: wrote 0F070777, read 0F070777, put back 00070777, read 00070777
+EXP2 delay bit 29 flipped: wrote 20070777, read 20070777, put back 00070777, read 00070777
+EXP2 delay bit 28: wrote 10070777, read 00070777, put back 00070777, read 00070777
+EXP2 delay bit 30: wrote 40070777, read 00070777, put back 00070777, read 00070777
+EXP2 delay bit 31: wrote 80070777, read 00070777, put back 00070777, read 00070777
+CDROM delay bits 14-15: wrote 0002C843, read 0002C843, put back 00020843, read 00020843
+CDROM delay bits 21-23: wrote 00E20843, read 00020843, put back 00020843, read 00020843
+CDROM delay bits 24-27: wrote 0F020843, read 0F020843, put back 00020843, read 00020843
+CDROM delay bit 29 flipped: wrote 20020843, read 20020843, put back 00020843, read 00020843
+CDROM delay bit 28: wrote 10020843, read 00020843, put back 00020843, read 00020843
+CDROM delay bit 30: wrote 40020843, read 00020843, put back 00020843, read 00020843
+CDROM delay bit 31: wrote 80020843, read 00020843, put back 00020843, read 00020843
+SPU delay bits 14-15: wrote 2009F1E1, read 2009F1E1, put back 200931E1, read 200931E1
+SPU delay bits 21-23: wrote 20E931E1, read 200931E1, put back 200931E1, read 200931E1
+SPU delay bits 24-27: wrote 2F0931E1, read 2F0931E1, put back 200931E1, read 200931E1
+SPU delay bit 29 flipped: wrote 000931E1, read 000931E1, put back 200931E1, read 200931E1
+SPU delay bit 28: wrote 300931E1, read 200931E1, put back 200931E1, read 200931E1
+SPU delay bit 30: wrote 600931E1, read 200931E1, put back 200931E1, read 200931E1
+SPU delay bit 31: wrote A00931E1, read 200931E1, put back 200931E1, read 200931E1
+BIOS delay bits 14-15: wrote 0013E43F, read 0013E43F, put back 0013243F, read 0013243F
+BIOS delay bits 21-23: wrote 00F3243F, read 0013243F, put back 0013243F, read 0013243F
+BIOS delay bits 24-27: wrote 0F13243F, read 0F13243F, put back 0013243F, read 0013243F
+BIOS delay bit 29 flipped: wrote 2013243F, read 2013243F, put back 0013243F, read 0013243F
+BIOS delay bit 28: wrote 1013243F, read 0013243F, put back 0013243F, read 0013243F
+BIOS delay bit 30: wrote 4013243F, read 0013243F, put back 0013243F, read 0013243F
+BIOS delay bit 31: wrote 8013243F, read 0013243F, put back 0013243F, read 0013243F
+EXP1 base FF000000: wrote FF000000, read 1F000000, put back 1F000000, read 1F000000
+EXP1 base 00000000: wrote 00000000, read 1F000000, put back 1F000000, read 1F000000
+Done.
+```
+
+s004/14RAM.txt:
+
+```
+===== 14 RAM RAM SIZE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+RAM_SIZE read back:
+RAM_SIZE 0B8F (bits 0-2): wrote 00000B8F, read 00000B8F, put back 00000B88, read 00000B88
+RAM_SIZE 0BF8 (bits 4-6): wrote 00000BF8, read 00000BF8, put back 00000B88, read 00000B88
+RAM_SIZE FB88 (bits 12-15): wrote 0000FB88, read 0000FB88, put back 00000B88, read 00000B88
+RAM_SIZE FFFF0B88 (bits 16-31): wrote FFFF0B88, read FFFF0B88, put back 00000B88, read 00000B88
+RAM_SIZE 0888: wrote 00000888, read 00000888, put back 00000B88, read 00000B88
+Bit 7, "delay on simultaneous code and data fetch from RAM", and bit 8, by timing:
+cached code, RAM lw, 0B88: 979
+cached code, RAM lw, 0B08: 958
+cached code, RAM lw, 0A88: 952
+cached code, RAM lw, 0888: 949
+uncached code, no load, 0B88: 1903
+uncached code, no load, 0B08: 1895
+uncached code, RAM lw, 0B88: 2918
+uncached code, RAM lw, 0B08: 2700
+uncached code, RAM lw, 0A88: 2923
+uncached code, RAM lw, 0888: 2928
+uncached code, RAM lw use, 0B88: 3733
+uncached code, RAM lw use, 0B08: 3642
+uncached code, RAM sw, 0B88: 3029
+uncached code, RAM sw, 0B08: 2809
+uncached code, BIOS lw, 0B88: 4725
+uncached code, BIOS lw, 0B08: 4698
+Mirrors by setting (the word at the first address holds C0FFnnnn):
+RAM_SIZE 0B88, lw 0002F1D0: none, reg C0FF0B88
+RAM_SIZE 0B88, lw 0022F1D0: none, reg C0FF0B88
+RAM_SIZE 0B88, lw 0042F1D0: none, reg C0FF0B88
+RAM_SIZE 0B88, lw 0062F1D0: none, reg C0FF0B88
+RAM_SIZE 0B88, lw 0082F1D0: none, reg 00000001
+RAM_SIZE 0B88, lw 00C2F1D0: exception 7, reg 5A5A5A5A
+RAM_SIZE 0888, lw 0002F1D0: none, reg C0FF0888
+RAM_SIZE 0888, lw 0022F1D0: none, reg 00000001
+RAM_SIZE 0888, lw 0042F1D0: exception 7, reg 5A5A5A5A
+RAM_SIZE 0888, lw 0062F1D0: none, reg 00000001
+RAM_SIZE 0888, lw 0082F1D0: exception 7, reg 5A5A5A5A
+RAM_SIZE 0888, lw 00C2F1D0: none, reg 00000001
+RAM_SIZE 0C88, lw 0002F1D0: none, reg C0FF0C88
+RAM_SIZE 0C88, lw 0022F1D0: none, reg FFFFFFFF
+RAM_SIZE 0C88, lw 0042F1D0: exception 7, reg 5A5A5A5A
+RAM_SIZE 0C88, lw 0062F1D0: exception 7, reg 5A5A5A5A
+RAM_SIZE 0C88, lw 0082F1D0: exception 7, reg 5A5A5A5A
+RAM_SIZE 0C88, lw 00C2F1D0: exception 7, reg 5A5A5A5A
+RAM_SIZE 0F88, lw 0002F1D0: none, reg C0FF0F88
+RAM_SIZE 0F88, lw 0022F1D0: none, reg C0FF0F88
+RAM_SIZE 0F88, lw 0042F1D0: none, reg C0FF0F88
+RAM_SIZE 0F88, lw 0062F1D0: none, reg C0FF0F88
+RAM_SIZE 0F88, lw 0082F1D0: none, reg FFFFFFFF
+RAM_SIZE 0F88, lw 00C2F1D0: none, reg FFFFFFFF
+RAM_SIZE 0888, sw past 2MB: exception yes 7, word now 11111111
+Done.
+```
+
+s005/15BCC.txt:
+
+```
+===== 15 BCC CACHE CONTROL | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Cache control 0001E988, read back:
+BCC bits 18-31: wrote FFFDE988, read FFFDE988, put back 0001E988, read 0001E988
+BCC bit 6: wrote 0001E9C8, read 0001E988, put back 0001E988, read 0001E988
+BCC bit 17: wrote 0003E988, read 0003E988, put back 0001E988, read 0001E988
+BCC bit 12: wrote 0001F988, read 0001F988, put back 0001E988, read 0001E988
+BCC bit 10 (IS0): wrote 0001ED88, read 0001E988, put back 0001E988, read 0001E988
+Loads by BCC bit (100 each):
+RAM lw, as set: 979
+scratchpad lw, as set: 440
+RAM lw use, as set: 963
+RAM lw, bit 16 LDSCH (0000E988): 1086
+scratchpad lw, bit 16 LDSCH: 449
+RAM lw use, bit 16 LDSCH: 1164
+RAM lw, bit 14 NOPAD (0001A988): 978
+scratchpad lw, bit 14 NOPAD: 454
+RAM lw use, bit 14 NOPAD: 962
+RAM lw, bit 13 RDPRI (0001C988): 980
+scratchpad lw, bit 13 RDPRI: 449
+RAM lw use, bit 13 RDPRI: 953
+RAM lw, bit 15 BGNT (00016988): 976
+scratchpad lw, bit 15 BGNT: 449
+RAM lw use, bit 15 BGNT: 962
+RAM lw, bit 12 INTP (0001F988): 981
+scratchpad lw, bit 12 INTP: 449
+RAM lw use, bit 12 INTP: 962
+RAM lw, bit 17 NOSTR (0003E988): 990
+scratchpad lw, bit 17 NOSTR: 457
+RAM lw use, bit 17 NOSTR: 974
+RAM lw, DBLKSZ 1 (0001E998): 976
+scratchpad lw, DBLKSZ 1: 449
+RAM lw use, DBLKSZ 1: 962
+RAM lw, DBLKSZ 2 (0001E9A8): 973
+scratchpad lw, DBLKSZ 2: 449
+RAM lw use, DBLKSZ 2: 961
+RAM lw, DBLKSZ 3 (0001E9B8): 976
+scratchpad lw, DBLKSZ 3: 449
+RAM lw use, DBLKSZ 3: 962
+D-cache mode (bit 3 cleared, bit 7 set), one access; slot = (address >> 2) & FFh:
+KSEG0 lw: loaded 0DA7A000, scratchpad 1F8001E0 now 0DA7A000, RAM word 0DA7A000, BCC 0001E988
+KSEG0 lbu +1: loaded 000000A0, scratchpad 1F8001E0 now 0DA7A000, RAM word 0DA7A000, BCC 0001E988
+KSEG1 lw: loaded 0DA7A000, scratchpad 1F8001E0 now DEAD01E0, RAM word 0DA7A000, BCC 0001E988
+KSEG0 sw: loaded 00000000, scratchpad 1F8001E0 now DEAD01E0, RAM word 5EED0000, BCC 0001E988
+Done.
+```
+
+s005/16END.txt:
+
+```
+===== 16 END HANG RISKS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+The steps that may hang the console:
+EXP3 delay bit 31 set, lbu 1FA00000: FF, delay put back 00003022
+RAM_SIZE 0288, lw A0021498 and +2MB: 4D42C0DE 4D42C0DE
+BCC bit 7 cleared, lw 1F800100:
+```
+
+### 27 September 2026 card-g
+
+Raw output: [00RUN.txt](/tests/raw/20260927T0000Z-5501a-card-g/memctl_safe/00RUN.txt) · [01RDB.txt](/tests/raw/20260927T0000Z-5501a-card-g/memctl_safe/01RDB.txt) · [02RSV.txt](/tests/raw/20260927T0000Z-5501a-card-g/memctl_safe/02RSV.txt) · [03BRT.txt](/tests/raw/20260927T0000Z-5501a-card-g/memctl_safe/03BRT.txt) · [04SRT.txt](/tests/raw/20260927T0000Z-5501a-card-g/memctl_safe/04SRT.txt) · [05CRT.txt](/tests/raw/20260927T0000Z-5501a-card-g/memctl_safe/05CRT.txt) · [06XRT.txt](/tests/raw/20260927T0000Z-5501a-card-g/memctl_safe/06XRT.txt) · [07CMA.txt](/tests/raw/20260927T0000Z-5501a-card-g/memctl_safe/07CMA.txt) · [08CMB.txt](/tests/raw/20260927T0000Z-5501a-card-g/memctl_safe/08CMB.txt) · [09WRT.txt](/tests/raw/20260927T0000Z-5501a-card-g/memctl_safe/09WRT.txt) · [10SCR.txt](/tests/raw/20260927T0000Z-5501a-card-g/memctl_safe/10SCR.txt) · [11PWR.txt](/tests/raw/20260927T0000Z-5501a-card-g/memctl_safe/11PWR.txt) · [12WIN.txt](/tests/raw/20260927T0000Z-5501a-card-g/memctl_safe/12WIN.txt) · [13RSX.txt](/tests/raw/20260927T0000Z-5501a-card-g/memctl_safe/13RSX.txt) · [14RAM.txt](/tests/raw/20260927T0000Z-5501a-card-g/memctl_safe/14RAM.txt)
+
+00RUN.txt:
+
+```
+===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+15 tests
+A chain program, linked at 80010000
+Saved on the card in slot 2, from image 1
+COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 1F801DAA BDAM 00000000
+BPCM 00000000 SR 70000000 Cause 00000020 EPC 80111D24 PRId 00000002
+```
+
+01RDB.txt:
+
+```
+===== 01 RDB MEMCTL READ BACK | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 1F801DAA
+
+Memory control read back, every register at each width:
+EXP1 base 1F801000: lw 1F000000, KSEG0 1F000000, KSEG1 1F000000, lhu 0000 1F00, lbu 00 00 00 1F
+EXP2 base 1F801004: lw 1F802000, KSEG0 1F802000, KSEG1 1F802000, lhu 2000 1F80, lbu 00 20 80 1F
+EXP1 delay 1F801008: lw 0013243F, KSEG0 0013243F, KSEG1 0013243F, lhu 243F 0013, lbu 3F 24 13 00
+EXP3 delay 1F80100C: lw 00003022, KSEG0 00003022, KSEG1 00003022, lhu 3022 0000, lbu 22 30 00 00
+BIOS delay 1F801010: lw 0013243F, KSEG0 0013243F, KSEG1 0013243F, lhu 243F 0013, lbu 3F 24 13 00
+SPU delay 1F801014: lw 220931E1, KSEG0 220931E1, KSEG1 220931E1, lhu 31E1 2209, lbu E1 31 09 22
+CDROM delay 1F801018: lw 00020943, KSEG0 00020943, KSEG1 00020943, lhu 0943 0002, lbu 43 09 02 00
+EXP2 delay 1F80101C: lw 00070777, KSEG0 00070777, KSEG1 00070777, lhu 0777 0007, lbu 77 07 07 00
+COM_DELAY 1F801020: lw 00001325, KSEG0 00001325, KSEG1 00001325, lhu 1325 0000, lbu 25 13 00 00
+RAM_SIZE 1F801060: lw 00000B88, KSEG0 3C080B88, KSEG1 3C080B88, lhu 0B88 0000, lbu 88 0B 00 00
+cache control FFFE0130: lw 0001E988, lhu E988 0001, lbu 88 00 00 00
+RAM_SIZE three times: 0C000B88 0C000B88 3C040B88
+RAM_SIZE after a BIOS lw: 24840B88
+CDROM 1F801800: lw 19191919, lhu 1919, lbu 19
+SPU 1F801C00: lw 00000000, lhu 0000 0000
+Done.
+```
+
+02RSV.txt:
+
+```
+===== 02 RSV RESERVED BITS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 1F801DAA
+
+Reserved bits, written and read back (the register put back at once):
+EXP1 base 1F0000FF: wrote 1F0000FF, read 1F0000FF, put back 1F000000, read 1F000000
+EXP1 base 1F000001: wrote 1F000001, read 1F000001, put back 1F000000, read 1F000000
+EXP1 base 1F07FFFF: wrote 1F07FFFF, read 1F07FFFF, put back 1F000000, read 1F000000
+EXP2 base 1F802001: wrote 1F802001, read 1F802001, put back 1F802000, read 1F802000
+EXP2 base 1F802080: wrote 1F802080, read 1F802080, put back 1F802000, read 1F802000
+EXP1 delay bits 14-15: wrote 0013E43F, read 0013E43F, put back 0013243F, read 0013243F
+EXP1 delay bits 21-23: wrote 00F3243F, read 0013243F, put back 0013243F, read 0013243F
+EXP1 delay bits 24-27: wrote 0F13243F, read 0F13243F, put back 0013243F, read 0013243F
+EXP1 delay bit 29: wrote 2013243F, read 2013243F, put back 0013243F, read 0013243F
+EXP1 delay low 16 all set: wrote 0013FFFF, read 0013FFFF, put back 0013243F, read 0013243F
+EXP3 delay bits 14-15: wrote 0000F022, read 0000F022, put back 00003022, read 00003022
+EXP3 delay bits 21-23: wrote 00E03022, read 00003022, put back 00003022, read 00003022
+EXP3 delay bits 24-27: wrote 0F003022, read 0F003022, put back 00003022, read 00003022
+EXP3 delay bit 29: wrote 20003022, read 20003022, put back 00003022, read 00003022
+EXP3 delay low 16 all set: wrote 0000FFFF, read 0000FFFF, put back 00003022, read 00003022
+EXP3 delay all zero: wrote 00000000, read 00000000, put back 00003022, read 00003022
+COM_DELAY bits 16-17 cleared: wrote 00001325, read 00001325, put back 00001325, read 00001325
+COM_DELAY bits 16-31 set: wrote FFFF1325, read 00031325, put back 00001325, read 00001325
+COM_DELAY bit 18 set: wrote 00041325, read 00001325, put back 00001325, read 00001325
+Done.
+```
+
+03BRT.txt:
+
+```
+===== 03 BRT BIOS READ TIMING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 1F801DAA
+
+BIOS reads at BFC00100, BIOS delay 0013243F:
+no load: 353
+BIOS lw, read delay 0: 2339, value FFFFFFFF
+BIOS lw, read delay 1: 2739, value 959F1FFF
+BIOS lw, read delay 2: 3139, value 19951204
+BIOS lw, read delay 3: 3539, value 19951204
+BIOS lw, read delay 4: 3939, value 19951204
+BIOS lw, read delay 5: 4339, value 19951204
+BIOS lw, read delay 6: 4739, value 19951204
+BIOS lw, read delay 7: 5146, value 19951204
+BIOS lw, read delay 8: 5544, value 19951204
+BIOS lw, read delay 9: 5939, value 19951204
+BIOS lw, read delay 10: 6339, value 19951204
+BIOS lw, read delay 11: 6743, value 19951204
+BIOS lw, read delay 12: 7139, value 19951204
+BIOS lw, read delay 13: 7539, value 19951204
+BIOS lw, read delay 14: 7939, value 19951204
+BIOS lw, read delay 15: 8343, value 19951204
+BIOS lhu, read delay 0: 1352, value 0000FFFF
+BIOS lhu, read delay 1: 1537, value 00001EFF
+BIOS lhu, read delay 2: 1737, value 00001204
+BIOS lhu, read delay 3: 1937, value 00001204
+BIOS lhu, read delay 4: 2137, value 00001204
+BIOS lhu, read delay 5: 2337, value 00001204
+BIOS lhu, read delay 6: 2537, value 00001204
+BIOS lhu, read delay 7: 2737, value 00001204
+BIOS lhu, read delay 8: 2937, value 00001204
+BIOS lhu, read delay 9: 3137, value 00001204
+BIOS lhu, read delay 10: 3337, value 00001204
+BIOS lhu, read delay 11: 3537, value 00001204
+BIOS lhu, read delay 12: 3737, value 00001204
+BIOS lhu, read delay 13: 3937, value 00001204
+BIOS lhu, read delay 14: 4137, value 00001204
+BIOS lhu, read delay 15: 4337, value 00001204
+BIOS lbu, read delay 0: 844, value 000000FF
+BIOS lbu, read delay 1: 941, value 000000FF
+BIOS lbu, read delay 2: 1041, value 00000004
+BIOS lbu, read delay 3: 1144, value 00000004
+BIOS lbu, read delay 4: 1241, value 00000004
+BIOS lbu, read delay 5: 1341, value 00000004
+BIOS lbu, read delay 6: 1441, value 00000004
+BIOS lbu, read delay 7: 1541, value 00000004
+BIOS lbu, read delay 8: 1641, value 00000004
+BIOS lbu, read delay 9: 1741, value 00000004
+BIOS lbu, read delay 10: 1841, value 00000004
+BIOS lbu, read delay 11: 1941, value 00000004
+BIOS lbu, read delay 12: 2041, value 00000004
+BIOS lbu, read delay 13: 2146, value 00000004
+BIOS lbu, read delay 14: 2241, value 00000004
+BIOS lbu, read delay 15: 2346, value 00000004
+BIOS lw, as set (0013243F): 3544, value 19951204
+BIOS lhu, as set (0013243F): 1966, value 00001204
+BIOS lbu, as set (0013243F): 1141, value 00000004
+BIOS lw, bit 8 flipped (0013253F): 5242, value 19951204
+BIOS lhu, bit 8 flipped (0013253F): 2635, value 00001204
+BIOS lbu, bit 8 flipped (0013253F): 1339, value 00000004
+BIOS lw, bit 9 flipped (0013263F): 3544, value 19951204
+BIOS lhu, bit 9 flipped (0013263F): 1952, value 00001204
+BIOS lbu, bit 9 flipped (0013263F): 1144, value 00000004
+BIOS lw, bit 10 flipped (0013203F): 2648, value 19951204
+BIOS lhu, bit 10 flipped (0013203F): 1642, value 00001204
+BIOS lbu, bit 10 flipped (0013203F): 1141, value 00000004
+BIOS lw, bit 11 flipped (00132C3F): 3546, value 19951204
+BIOS lhu, bit 11 flipped (00132C3F): 1937, value 00001204
+BIOS lbu, bit 11 flipped (00132C3F): 1141, value 00000004
+BIOS lw, bit 12 flipped (0013343F): 1944, value FF95FF04
+BIOS lhu, bit 12 flipped (0013343F): 1137, value 0000FF04
+BIOS lbu, bit 12 flipped (0013343F): 1141, value 00000004
+BIOS lw, bit 13 flipped (0013043F): 3548, value 04040404
+BIOS lhu, bit 13 flipped (0013043F): 1937, value 00000404
+BIOS lbu, bit 13 flipped (0013043F): 1141, value 00000004
+BIOS lw, write delay 0: 3544, value 19951204
+BIOS lw, write delay 1: 3539, value 19951204
+BIOS lw, write delay 2: 3539, value 19951204
+BIOS lw, write delay 3: 3560, value 19951204
+BIOS lw, write delay 4: 3539, value 19951204
+BIOS lw, write delay 5: 3542, value 19951204
+BIOS lw, write delay 6: 3539, value 19951204
+BIOS lw, write delay 7: 3539, value 19951204
+BIOS lw, write delay 8: 3542, value 19951204
+BIOS lw, write delay 9: 3539, value 19951204
+BIOS lw, write delay 10: 3539, value 19951204
+BIOS lw, write delay 11: 3539, value 19951204
+BIOS lw, write delay 12: 3539, value 19951204
+BIOS lw, write delay 13: 3539, value 19951204
+BIOS lw, write delay 14: 3539, value 19951204
+BIOS lw, write delay 15: 3539, value 19951204
+Done.
+```
+
+04SRT.txt:
+
+```
+===== 04 SRT SPU READ TIMING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 1F801DAA
+
+SPU reads at 1F801C00, SPU delay 220931E1:
+SPU lw, read delay 0: 1449, value FFFFFFFF
+SPU lw, read delay 1: 1644, value FFFFFFFF
+SPU lw, read delay 2: 1839, value FFFFFFFF
+SPU lw, read delay 3: 2039, value FFFFFFFF
+SPU lw, read delay 4: 2239, value FFFFFFFF
+SPU lw, read delay 5: 2439, value FFFFFFFF
+SPU lw, read delay 6: 2639, value FFFFFFFF
+SPU lw, read delay 7: 2839, value FFFFFFFF
+SPU lw, read delay 8: 3039, value FFFFFFFF
+SPU lw, read delay 9: 3254, value FFFFFFFF
+SPU lw, read delay 10: 3439, value FFFFFFFF
+SPU lw, read delay 11: 3639, value 00000000
+SPU lw, read delay 12: 3839, value 00000000
+SPU lw, read delay 13: 4039, value 00000000
+SPU lw, read delay 14: 4239, value 00000000
+SPU lw, read delay 15: 4439, value 00000000
+SPU lhu, read delay 0: 852, value 0000FFFF
+SPU lhu, read delay 1: 937, value 0000FFFF
+SPU lhu, read delay 2: 1052, value 0000FFFF
+SPU lhu, read delay 3: 1137, value 0000FFFF
+SPU lhu, read delay 4: 1237, value 0000FFFF
+SPU lhu, read delay 5: 1337, value 0000FFFF
+SPU lhu, read delay 6: 1437, value 0000FFFF
+SPU lhu, read delay 7: 1537, value 0000FFFF
+SPU lhu, read delay 8: 1637, value 0000FFFF
+SPU lhu, read delay 9: 1737, value 0000FFFF
+SPU lhu, read delay 10: 1837, value 0000FFFF
+SPU lhu, read delay 11: 1937, value 00000000
+SPU lhu, read delay 12: 2037, value 00000000
+SPU lhu, read delay 13: 2137, value 00000000
+SPU lhu, read delay 14: 2237, value 00000000
+SPU lhu, read delay 15: 2337, value 00000000
+SPU lbu, read delay 0: 844, value 000000FF
+SPU lbu, read delay 1: 941, value 000000FF
+SPU lbu, read delay 2: 1041, value 000000FF
+SPU lbu, read delay 3: 1141, value 000000FF
+SPU lbu, read delay 4: 1241, value 000000FF
+SPU lbu, read delay 5: 1341, value 000000FF
+SPU lbu, read delay 6: 1444, value 000000FF
+SPU lbu, read delay 7: 1541, value 000000FF
+SPU lbu, read delay 8: 1641, value 000000FF
+SPU lbu, read delay 9: 1741, value 000000FF
+SPU lbu, read delay 10: 1841, value 000000FF
+SPU lbu, read delay 11: 1941, value 00000000
+SPU lbu, read delay 12: 2041, value 00000000
+SPU lbu, read delay 13: 2141, value 00000000
+SPU lbu, read delay 14: 2241, value 00000000
+SPU lbu, read delay 15: 2341, value 00000000
+SPU lw, as set (220931E1): 4244, value 00000000
+SPU lhu, as set (220931E1): 2252, value 00000000
+SPU lbu, as set (220931E1): 2241, value 00000000
+SPU lw, bit 8 flipped (220930E1): 3844, value 00000000
+SPU lhu, bit 8 flipped (220930E1): 2237, value 00000000
+SPU lbu, bit 8 flipped (220930E1): 2241, value 00000000
+SPU lw, bit 9 flipped (220933E1): 4244, value 00000000
+SPU lhu, bit 9 flipped (220933E1): 2237, value 00000000
+SPU lbu, bit 9 flipped (220933E1): 2241, value 00000000
+SPU lw, bit 10 flipped (220935E1): 4842, value 00000000
+SPU lhu, bit 10 flipped (220935E1): 2455, value 00000000
+SPU lbu, bit 10 flipped (220935E1): 2445, value 00000000
+SPU lw, bit 11 flipped (220939E1): 4244, value 00000000
+SPU lhu, bit 11 flipped (220939E1): 2237, value 00000000
+SPU lbu, bit 11 flipped (220939E1): 2244, value 00000000
+SPU lw, bit 12 flipped (220921E1): 8249, value 00000000
+SPU lhu, bit 12 flipped (220921E1): 4237, value 00000000
+SPU lbu, bit 12 flipped (220921E1): 2241, value 00000000
+SPU lw, bit 13 flipped (220911E1): 4244, value 00000000
+SPU lhu, bit 13 flipped (220911E1): 2237, value 00000000
+SPU lbu, bit 13 flipped (220911E1): 2244, value 00000000
+SPU lw, bit 29 flipped (020931E1): 4246, value 00000000
+SPU lhu, bit 29 flipped (020931E1): 2237, value 00000000
+SPU lbu, bit 29 flipped (020931E1): 2241, value 00000000
+SPU lhu, bits 24-27 = F: 2242, value 00000000
+SPU lhu, bits 24-27 = 2 (220931E1h): 2237, value 00000000
+Done.
+```
+
+05CRT.txt:
+
+```
+===== 05 CRT CDROM READ TIMING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 1F801DAA
+
+CD-ROM reads at 1F801800, CDROM delay 00020943:
+CDROM lw, read delay 0: 3044, value 19191919
+CDROM lw, read delay 1: 3039, value 19191919
+CDROM lw, read delay 2: 3439, value 19191919
+CDROM lw, read delay 3: 3839, value 19191919
+CDROM lw, read delay 4: 4239, value 19191919
+CDROM lw, read delay 5: 4639, value 19191919
+CDROM lw, read delay 6: 5039, value 19191919
+CDROM lw, read delay 7: 5439, value 19191919
+CDROM lw, read delay 8: 5839, value 19191919
+CDROM lw, read delay 9: 6239, value 19191919
+CDROM lw, read delay 10: 6654, value 19191919
+CDROM lw, read delay 11: 7039, value 19191919
+CDROM lw, read delay 12: 7439, value 19191919
+CDROM lw, read delay 13: 7854, value 19191919
+CDROM lw, read delay 14: 8239, value 19191919
+CDROM lw, read delay 15: 8639, value 19191919
+CDROM lhu, read delay 0: 1652, value 00001919
+CDROM lhu, read delay 1: 1637, value 00001919
+CDROM lhu, read delay 2: 1837, value 00001919
+CDROM lhu, read delay 3: 2043, value 00001919
+CDROM lhu, read delay 4: 2237, value 00001919
+CDROM lhu, read delay 5: 2437, value 00001919
+CDROM lhu, read delay 6: 2643, value 00001919
+CDROM lhu, read delay 7: 2837, value 00001919
+CDROM lhu, read delay 8: 3037, value 00001919
+CDROM lhu, read delay 9: 3243, value 00001919
+CDROM lhu, read delay 10: 3437, value 00001919
+CDROM lhu, read delay 11: 3637, value 00001919
+CDROM lhu, read delay 12: 3842, value 00001919
+CDROM lhu, read delay 13: 4037, value 00001919
+CDROM lhu, read delay 14: 4242, value 00001919
+CDROM lhu, read delay 15: 4437, value 00001919
+CDROM lbu, read delay 0: 944, value 00000019
+CDROM lbu, read delay 1: 941, value 00000019
+CDROM lbu, read delay 2: 1044, value 00000019
+CDROM lbu, read delay 3: 1141, value 00000019
+CDROM lbu, read delay 4: 1241, value 00000019
+CDROM lbu, read delay 5: 1341, value 00000019
+CDROM lbu, read delay 6: 1441, value 00000019
+CDROM lbu, read delay 7: 1546, value 00000019
+CDROM lbu, read delay 8: 1641, value 00000019
+CDROM lbu, read delay 9: 1741, value 00000019
+CDROM lbu, read delay 10: 1841, value 00000019
+CDROM lbu, read delay 11: 1941, value 00000019
+CDROM lbu, read delay 12: 2041, value 00000019
+CDROM lbu, read delay 13: 2141, value 00000019
+CDROM lbu, read delay 14: 2241, value 00000019
+CDROM lbu, read delay 15: 2341, value 00000019
+CDROM lw, as set (00020943): 4244, value 19191919
+CDROM lhu, as set (00020943): 2252, value 00001919
+CDROM lbu, as set (00020943): 1247, value 00000019
+CDROM lw, bit 8 flipped (00020843): 3044, value 19191919
+CDROM lhu, bit 8 flipped (00020843): 1837, value 00001919
+CDROM lbu, bit 8 flipped (00020843): 1244, value 00000019
+CDROM lw, bit 9 flipped (00020B43): 4244, value 19191919
+CDROM lhu, bit 9 flipped (00020B43): 2252, value 00001919
+CDROM lbu, bit 9 flipped (00020B43): 1241, value 00000019
+CDROM lw, bit 10 flipped (00020D43): 5642, value 19191919
+CDROM lhu, bit 10 flipped (00020D43): 2835, value 00001919
+CDROM lbu, bit 10 flipped (00020D43): 1442, value 00000019
+CDROM lw, bit 11 flipped (00020143): 4244, value 19191919
+CDROM lhu, bit 11 flipped (00020143): 2237, value 00001919
+CDROM lbu, bit 11 flipped (00020143): 1241, value 00000019
+CDROM lw, bit 12 flipped (00021943): 2244, value FF19FF19
+CDROM lhu, bit 12 flipped (00021943): 1237, value 0000FF19
+CDROM lbu, bit 12 flipped (00021943): 1241, value 00000019
+Done.
+```
+
+06XRT.txt:
+
+```
+===== 06 XRT EXP READ TIMING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 1F801DAA
+
+Expansion reads, EXP1 0013243F EXP2 00070777 EXP3 00003022:
+EXP1 lbu, read delay 0: 844, value 000000FF
+EXP1 lbu, read delay 1: 941, value 000000FF
+EXP1 lbu, read delay 2: 1041, value 000000FF
+EXP1 lbu, read delay 3: 1141, value 000000FF
+EXP1 lbu, read delay 4: 1241, value 000000FF
+EXP1 lbu, read delay 5: 1341, value 000000FF
+EXP1 lbu, read delay 6: 1456, value 000000FF
+EXP1 lbu, read delay 7: 1541, value 000000FF
+EXP1 lbu, read delay 8: 1641, value 000000FF
+EXP1 lbu, read delay 9: 1741, value 000000FF
+EXP1 lbu, read delay 10: 1841, value 000000FF
+EXP1 lbu, read delay 11: 1941, value 000000FF
+EXP1 lbu, read delay 12: 2041, value 000000FF
+EXP1 lbu, read delay 13: 2141, value 000000FF
+EXP1 lbu, read delay 14: 2241, value 000000FF
+EXP1 lbu, read delay 15: 2341, value 000000FF
+EXP2 lbu, read delay 0: 1039, value 000000FF
+EXP2 lbu, read delay 1: 1142, value 000000FF
+EXP2 lbu, read delay 2: 1239, value 000000FF
+EXP2 lbu, read delay 3: 1339, value 000000FF
+EXP2 lbu, read delay 4: 1439, value 000000FF
+EXP2 lbu, read delay 5: 1539, value 000000FF
+EXP2 lbu, read delay 6: 1639, value 000000FF
+EXP2 lbu, read delay 7: 1739, value 000000FF
+EXP2 lbu, read delay 8: 1839, value 000000FF
+EXP2 lbu, read delay 9: 1939, value 000000FF
+EXP2 lbu, read delay 10: 2039, value 000000FF
+EXP2 lbu, read delay 11: 2139, value 000000FF
+EXP2 lbu, read delay 12: 2239, value 000000FF
+EXP2 lbu, read delay 13: 2339, value 000000FF
+EXP2 lbu, read delay 14: 2439, value 000000FF
+EXP2 lbu, read delay 15: 2541, value 000000FF
+EXP2 lw, read delay 0: 4042, value FFFFFFFF
+EXP2 lw, read delay 1: 4437, value FFFFFFFF
+EXP2 lw, read delay 2: 4842, value FFFFFFFF
+EXP2 lw, read delay 3: 5237, value FFFFFFFF
+EXP2 lw, read delay 4: 5647, value FFFFFFFF
+EXP2 lw, read delay 5: 6052, value FFFFFFFF
+EXP2 lw, read delay 6: 6442, value FFFFFFFF
+EXP2 lw, read delay 7: 6842, value FFFFFFFF
+EXP2 lw, read delay 8: 7237, value FFFFFFFF
+EXP2 lw, read delay 9: 7642, value FFFFFFFF
+EXP2 lw, read delay 10: 8037, value FFFFFFFF
+EXP2 lw, read delay 11: 8437, value FFFFFFFF
+EXP2 lw, read delay 12: 8837, value FFFFFFFF
+EXP2 lw, read delay 13: 9237, value FFFFFFFF
+EXP2 lw, read delay 14: 9637, value FFFFFFFF
+EXP2 lw, read delay 15: 10037, value FFFFFFFF
+EXP3 lbu, read delay 0: 844, value 000000FF
+EXP3 lbu, read delay 1: 941, value 000000FF
+EXP3 lbu, read delay 2: 1041, value 000000FF
+EXP3 lbu, read delay 3: 1141, value 000000FF
+EXP3 lbu, read delay 4: 1241, value 000000FF
+EXP3 lbu, read delay 5: 1341, value 000000FF
+EXP3 lbu, read delay 6: 1444, value 000000FF
+EXP3 lbu, read delay 7: 1541, value 000000FF
+EXP3 lbu, read delay 8: 1641, value 000000FF
+EXP3 lbu, read delay 9: 1741, value 000000FF
+EXP3 lbu, read delay 10: 1841, value 000000FF
+EXP3 lbu, read delay 11: 1941, value 000000FF
+EXP3 lbu, read delay 12: 2041, value 000000FF
+EXP3 lbu, read delay 13: 2141, value 000000FF
+EXP3 lbu, read delay 14: 2241, value 000000FF
+EXP3 lbu, read delay 15: 2341, value 000000FF
+EXP3 lw, read delay 0: 1044, value FFFFFFFF
+EXP3 lw, read delay 1: 1244, value FFFFFFFF
+EXP3 lw, read delay 2: 1439, value FFFFFFFF
+EXP3 lw, read delay 3: 1639, value FFFFFFFF
+EXP3 lw, read delay 4: 1839, value FFFFFFFF
+EXP3 lw, read delay 5: 2039, value FFFFFFFF
+EXP3 lw, read delay 6: 2239, value FFFFFFFF
+EXP3 lw, read delay 7: 2439, value FFFFFFFF
+EXP3 lw, read delay 8: 2644, value FFFFFFFF
+EXP3 lw, read delay 9: 2839, value FFFFFFFF
+EXP3 lw, read delay 10: 3044, value FFFFFFFF
+EXP3 lw, read delay 11: 3239, value FFFFFFFF
+EXP3 lw, read delay 12: 3439, value FFFFFFFF
+EXP3 lw, read delay 13: 3639, value FFFFFFFF
+EXP3 lw, read delay 14: 3839, value FFFFFFFF
+EXP3 lw, read delay 15: 4039, value FFFFFFFF
+Done.
+```
+
+07CMA.txt:
+
+```
+===== 07 CMA COM0 COM1 SWEEP | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 1F801DAA
+
+COM_DELAY 00001325; COM0 with SPU (bit 8 set) and BIOS (bit 8 set here):
+SPU lhu, COM0 0: 2252
+SPU lhu, COM0 1: 2237
+SPU lhu, COM0 2: 2237
+SPU lhu, COM0 3: 2237
+SPU lhu, COM0 4: 2237
+SPU lhu, COM0 5: 2237
+SPU lhu, COM0 6: 2237
+SPU lhu, COM0 7: 2336
+SPU lhu, COM0 8: 2438
+SPU lhu, COM0 9: 2534
+SPU lhu, COM0 10: 2633
+SPU lhu, COM0 11: 2732
+SPU lhu, COM0 12: 2831
+SPU lhu, COM0 13: 2930
+SPU lhu, COM0 14: 3029
+SPU lhu, COM0 15: 3133
+SPU lw, COM0 0: 3844
+SPU lw, COM0 1: 3844
+SPU lw, COM0 2: 3939
+SPU lw, COM0 3: 4039
+SPU lw, COM0 4: 4139
+SPU lw, COM0 5: 4239
+SPU lw, COM0 6: 4339
+SPU lw, COM0 7: 4538
+SPU lw, COM0 8: 4737
+SPU lw, COM0 9: 4936
+SPU lw, COM0 10: 5140
+SPU lw, COM0 11: 5337
+SPU lw, COM0 12: 5533
+SPU lw, COM0 13: 5732
+SPU lw, COM0 14: 5933
+SPU lw, COM0 15: 6130
+BIOS+bit8 lbu, COM0 0: 1144
+BIOS+bit8 lbu, COM0 1: 1141
+BIOS+bit8 lbu, COM0 2: 1141
+BIOS+bit8 lbu, COM0 3: 1144
+BIOS+bit8 lbu, COM0 4: 1240
+BIOS+bit8 lbu, COM0 5: 1339
+BIOS+bit8 lbu, COM0 6: 1438
+BIOS+bit8 lbu, COM0 7: 1537
+BIOS+bit8 lbu, COM0 8: 1636
+BIOS+bit8 lbu, COM0 9: 1741
+BIOS+bit8 lbu, COM0 10: 1834
+BIOS+bit8 lbu, COM0 11: 1937
+BIOS+bit8 lbu, COM0 12: 2032
+BIOS+bit8 lbu, COM0 13: 2131
+BIOS+bit8 lbu, COM0 14: 2230
+BIOS+bit8 lbu, COM0 15: 2329
+BIOS+bit8 lw, COM0 0: 3539
+BIOS+bit8 lw, COM0 1: 3839
+BIOS+bit8 lw, COM0 2: 4139
+BIOS+bit8 lw, COM0 3: 4454
+BIOS+bit8 lw, COM0 4: 4838
+BIOS+bit8 lw, COM0 5: 5237
+BIOS+bit8 lw, COM0 6: 5641
+BIOS+bit8 lw, COM0 7: 6035
+BIOS+bit8 lw, COM0 8: 6434
+BIOS+bit8 lw, COM0 9: 6833
+BIOS+bit8 lw, COM0 10: 7232
+BIOS+bit8 lw, COM0 11: 7631
+BIOS+bit8 lw, COM0 12: 8030
+BIOS+bit8 lw, COM0 13: 8429
+BIOS+bit8 lw, COM0 14: 8828
+BIOS+bit8 lw, COM0 15: 9227
+COM1 with EXP2 (delay 00070777, bit 9 set):
+EXP2 lbu, COM1 0: 1742
+EXP2 lbu, COM1 1: 1739
+EXP2 lbu, COM1 2: 1739
+EXP2 lbu, COM1 3: 1739
+EXP2 lbu, COM1 4: 1739
+EXP2 lbu, COM1 5: 1739
+EXP2 lbu, COM1 6: 1739
+EXP2 lbu, COM1 7: 1739
+EXP2 lbu, COM1 8: 1739
+EXP2 lbu, COM1 9: 1739
+EXP2 lbu, COM1 10: 1739
+EXP2 lbu, COM1 11: 1739
+EXP2 lbu, COM1 12: 1739
+EXP2 lbu, COM1 13: 1739
+EXP2 lbu, COM1 14: 1739
+EXP2 lbu, COM1 15: 1739
+Bits 16-17:
+BIOS lw, COM bits 16-17 = 0: 3544
+SPU lhu, COM bits 16-17 = 0: 2252
+CDROM lbu, COM bits 16-17 = 0: 1239
+EXP2 lbu, COM bits 16-17 = 0: 1734
+BIOS lw, COM bits 16-17 = 1: 3545
+SPU lhu, COM bits 16-17 = 1: 2229
+CDROM lbu, COM bits 16-17 = 1: 1236
+EXP2 lbu, COM bits 16-17 = 1: 1734
+BIOS lw, COM bits 16-17 = 2: 3539
+SPU lhu, COM bits 16-17 = 2: 2229
+CDROM lbu, COM bits 16-17 = 2: 1236
+EXP2 lbu, COM bits 16-17 = 2: 1739
+BIOS lw, COM bits 16-17 = 3: 3545
+SPU lhu, COM bits 16-17 = 3: 2229
+CDROM lbu, COM bits 16-17 = 3: 1236
+EXP2 lbu, COM bits 16-17 = 3: 1734
+Done.
+```
+
+08CMB.txt:
+
+```
+===== 08 CMB COM2 COM3 SWEEP | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 1F801DAA
+
+COM2 with BIOS (bit 10 set) and CDROM (bit 10 set here):
+BIOS lbu, COM2 0: 1144
+BIOS lbu, COM2 1: 1141
+BIOS lbu, COM2 2: 1141
+BIOS lbu, COM2 3: 1145
+BIOS lbu, COM2 4: 1141
+BIOS lbu, COM2 5: 1141
+BIOS lbu, COM2 6: 1240
+BIOS lbu, COM2 7: 1339
+BIOS lbu, COM2 8: 1442
+BIOS lbu, COM2 9: 1537
+BIOS lbu, COM2 10: 1636
+BIOS lbu, COM2 11: 1735
+BIOS lbu, COM2 12: 1834
+BIOS lbu, COM2 13: 1938
+BIOS lbu, COM2 14: 2032
+BIOS lbu, COM2 15: 2131
+BIOS lw, COM2 0: 2644
+BIOS lw, COM2 1: 2944
+BIOS lw, COM2 2: 3239
+BIOS lw, COM2 3: 3539
+BIOS lw, COM2 4: 3839
+BIOS lw, COM2 5: 4139
+BIOS lw, COM2 6: 4538
+BIOS lw, COM2 7: 4938
+BIOS lw, COM2 8: 5341
+BIOS lw, COM2 9: 5735
+BIOS lw, COM2 10: 6149
+BIOS lw, COM2 11: 6538
+BIOS lw, COM2 12: 6932
+BIOS lw, COM2 13: 7346
+BIOS lw, COM2 14: 7730
+BIOS lw, COM2 15: 8129
+CDROM+bit10 lbu, COM2 0: 1244
+CDROM+bit10 lbu, COM2 1: 1241
+CDROM+bit10 lbu, COM2 2: 1340
+CDROM+bit10 lbu, COM2 3: 1441
+CDROM+bit10 lbu, COM2 4: 1538
+CDROM+bit10 lbu, COM2 5: 1637
+CDROM+bit10 lbu, COM2 6: 1736
+CDROM+bit10 lbu, COM2 7: 1835
+CDROM+bit10 lbu, COM2 8: 1937
+CDROM+bit10 lbu, COM2 9: 2033
+CDROM+bit10 lbu, COM2 10: 2132
+CDROM+bit10 lbu, COM2 11: 2231
+CDROM+bit10 lbu, COM2 12: 2330
+CDROM+bit10 lbu, COM2 13: 2429
+CDROM+bit10 lbu, COM2 14: 2528
+CDROM+bit10 lbu, COM2 15: 2629
+COM3 with CDROM (bit 11 set) and BIOS (bit 11 set here):
+CDROM lbu, COM3 0: 1244
+CDROM lbu, COM3 1: 1241
+CDROM lbu, COM3 2: 1241
+CDROM lbu, COM3 3: 1241
+CDROM lbu, COM3 4: 1244
+CDROM lbu, COM3 5: 1341
+CDROM lbu, COM3 6: 1441
+CDROM lbu, COM3 7: 1541
+CDROM lbu, COM3 8: 1644
+CDROM lbu, COM3 9: 1744
+CDROM lbu, COM3 10: 1841
+CDROM lbu, COM3 11: 1941
+CDROM lbu, COM3 12: 2041
+CDROM lbu, COM3 13: 2141
+CDROM lbu, COM3 14: 2241
+CDROM lbu, COM3 15: 2341
+CDROM lw, COM3 0: 4244
+CDROM lw, COM3 1: 4239
+CDROM lw, COM3 2: 4239
+CDROM lw, COM3 3: 4239
+CDROM lw, COM3 4: 4259
+CDROM lw, COM3 5: 4639
+CDROM lw, COM3 6: 5039
+CDROM lw, COM3 7: 5439
+CDROM lw, COM3 8: 5854
+CDROM lw, COM3 9: 6239
+CDROM lw, COM3 10: 6639
+CDROM lw, COM3 11: 7039
+CDROM lw, COM3 12: 7439
+CDROM lw, COM3 13: 7839
+CDROM lw, COM3 14: 8245
+CDROM lw, COM3 15: 8639
+BIOS+bit11 lbu, COM3 0: 1144
+BIOS+bit11 lbu, COM3 1: 1141
+BIOS+bit11 lbu, COM3 2: 1141
+BIOS+bit11 lbu, COM3 3: 1141
+BIOS+bit11 lbu, COM3 4: 1241
+BIOS+bit11 lbu, COM3 5: 1341
+BIOS+bit11 lbu, COM3 6: 1441
+BIOS+bit11 lbu, COM3 7: 1544
+BIOS+bit11 lbu, COM3 8: 1641
+BIOS+bit11 lbu, COM3 9: 1741
+BIOS+bit11 lbu, COM3 10: 1843
+BIOS+bit11 lbu, COM3 11: 1941
+BIOS+bit11 lbu, COM3 12: 2041
+BIOS+bit11 lbu, COM3 13: 2141
+BIOS+bit11 lbu, COM3 14: 2241
+BIOS+bit11 lbu, COM3 15: 2341
+Done.
+```
+
+09WRT.txt:
+
+```
+===== 09 WRT WRITE TIMING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 1F801DAA
+
+Stores by write delay; SPU word 00000000, CD index 1:
+SPU sh, as set: 832
+CDROM sb, as set: 1031
+POST sb, as set: 1600
+SPU sh, write delay 0: 730
+SPU sh, write delay 1: 828
+SPU sh, write delay 2: 931
+SPU sh, write delay 3: 1024
+SPU sh, write delay 4: 1127
+SPU sh, write delay 5: 1201
+SPU sh, write delay 6: 1305
+SPU sh, write delay 7: 1402
+SPU sh, write delay 8: 1514
+SPU sh, write delay 9: 1596
+SPU sh, write delay 10: 1693
+SPU sh, write delay 11: 1790
+SPU sh, write delay 12: 1887
+SPU sh, write delay 13: 1984
+SPU sh, write delay 14: 2081
+SPU sh, write delay 15: 2178
+SPU sw, write delay 0: 1317
+SPU sw, write delay 1: 1516
+SPU sw, write delay 2: 1708
+SPU sw, write delay 3: 1904
+SPU sw, write delay 4: 2105
+SPU sw, write delay 5: 2296
+SPU sw, write delay 6: 2495
+SPU sw, write delay 7: 2688
+SPU sw, write delay 8: 2884
+SPU sw, write delay 9: 3080
+SPU sw, write delay 10: 3276
+SPU sw, write delay 11: 3472
+SPU sw, write delay 12: 3668
+SPU sw, write delay 13: 3864
+SPU sw, write delay 14: 4060
+SPU sw, write delay 15: 4256
+CDROM sb, write delay 0: 840
+CDROM sb, write delay 1: 838
+CDROM sb, write delay 2: 933
+CDROM sb, write delay 3: 1031
+CDROM sb, write delay 4: 1129
+CDROM sb, write delay 5: 1208
+CDROM sb, write delay 6: 1312
+CDROM sb, write delay 7: 1409
+CDROM sb, write delay 8: 1507
+CDROM sb, write delay 9: 1605
+CDROM sb, write delay 10: 1703
+CDROM sb, write delay 11: 1801
+CDROM sb, write delay 12: 1899
+CDROM sb, write delay 13: 1997
+CDROM sb, write delay 14: 2101
+CDROM sb, write delay 15: 2193
+POST sb, write delay 0: 933
+POST sb, write delay 1: 1037
+POST sb, write delay 2: 1134
+POST sb, write delay 3: 1213
+POST sb, write delay 4: 1318
+POST sb, write delay 5: 1409
+POST sb, write delay 6: 1513
+POST sb, write delay 7: 1609
+POST sb, write delay 8: 1703
+POST sb, write delay 9: 1801
+POST sb, write delay 10: 1899
+POST sb, write delay 11: 1997
+POST sb, write delay 12: 2095
+POST sb, write delay 13: 2193
+POST sb, write delay 14: 2291
+POST sb, write delay 15: 2389
+POST sb, COM1 0: 1402
+POST sb, COM1 1: 1510
+POST sb, COM1 2: 1605
+POST sb, COM1 3: 1703
+POST sb, COM1 4: 1801
+POST sb, COM1 5: 1899
+POST sb, COM1 6: 1997
+POST sb, COM1 7: 2095
+POST sb, COM1 8: 2193
+POST sb, COM1 9: 2291
+POST sb, COM1 10: 2389
+POST sb, COM1 11: 2487
+POST sb, COM1 12: 2585
+POST sb, COM1 13: 2683
+POST sb, COM1 14: 2781
+POST sb, COM1 15: 2879
+SPU sh, bit 9 (hold) set: 1024
+CDROM sb, bit 9 (hold) set: 1211
+POST sb, bit 9 (hold) cleared: 1404
+SPU word after: 00000000; CD index after: 1
+SPU word put back: 00000000; CD index: 1
+Done.
+```
+
+10SCR.txt:
+
+```
+===== 10 SCR SCRATCHPAD | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 1F801DAA
+
+Scratchpad and RAM loads and stores (100 each):
+no load: 353
+scratchpad KUSEG lw: 442
+scratchpad KUSEG lhu: 454
+scratchpad KUSEG lbu: 442
+scratchpad KUSEG lw, use: 552
+scratchpad KUSEG sw: 459
+scratchpad KUSEG sh: 451
+scratchpad KUSEG sb: 454
+scratchpad KSEG0 lw: 442
+scratchpad KSEG0 lw, use: 545
+scratchpad KSEG0 sw: 454
+scratchpad last word lw: 442
+RAM KSEG0 lw: 949
+RAM KSEG0 lw, use: 957
+RAM KSEG0 sw: 463
+RAM KSEG1 lw: 952
+Code from KSEG1 (uncached):
+uncached, no load: 1906
+uncached, scratchpad lw: 2516
+uncached, scratchpad sw: 2516
+uncached, RAM lw: 2918
+scratchpad 1F800100 5C4A0100, 9F800100 5C4A0100, 1F8003FC 5C4A03FC, 9F8003FC 5C4A03FC
+Done.
+```
+
+11PWR.txt:
+
+```
+===== 11 PWR NARROW WRITES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 1F801DAA
+
+Narrow stores, EXP3 delay 00003022, COM_DELAY 00001325, BCC 0001E988:
+EXP3 delay sh +0: rt 05003022, read 05003022, put back 00003022
+EXP3 delay sb +0: rt 05003022, read 05003022, put back 00003022
+EXP3 delay sh +2: rt 00003022, read 20020000, put back 00003022
+EXP3 delay sb +1: rt 00003022, read 00102200, put back 00003022
+EXP3 delay sb +2: rt 00003022, read 20020000, put back 00003022
+EXP3 delay sb +3: rt 00003022, read 22000000, put back 00003022
+COM_DELAY sh +0: rt FFFC1325, read 00001325, put back 00001325
+COM_DELAY sb +1: rt 00001325, read 00032500, put back 00001325
+RAM_SIZE sh +0: rt ABCD0B88, read ABCD0B88, put back 00000B88
+BCC sh +0: rt 0005E988, read 0005E988, put back 0001E988
+BCC sb +0: rt 0005E988, read 0005E988, put back 0001E988
+BCC sh +2: rt 0005E988, read 0001E988, put back 0001E988
+BCC sb +1: rt 0005E988, read 0001E988, put back 0001E988
+Done.
+```
+
+12WIN.txt:
+
+```
+===== 12 WIN WINDOW SIZE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 1F801DAA
+
+Window sizes and bit 28:
+EXP3 lbu 1FA00000, size 0: none, reg 000000FF, register after 00003022
+EXP3 lbu 1FA00001, size 0: exception 7, reg 5A5A5A5A, register after 00003022
+EXP3 lbu 1FA00002, size 0: exception 7, reg 5A5A5A5A, register after 00003022
+EXP3 lhu 1FA00002, size 0: exception 7, reg 5A5A5A5A, register after 00003022
+EXP3 delay bit 28 written 1: wrote 10003022, read 00003022, put back 00003022, read 00003022
+EXP3 lbu 1FA00001, size 1: none, reg 000000FF, register after 00013022
+EXP3 lbu 1FA00002, size 1: exception 7, reg 5A5A5A5A, register after 00013022
+EXP3 lbu 1FBFFFFF, size 15h: none, reg 000000FF, register after 00153022
+EXP2 lbu 1F80207F, size 7: none, reg 000000FF, register after 00070777
+EXP2 lbu 1F802080, size 7: exception 7, reg 5A5A5A5A, register after 00070777
+EXP2 lbu 1F802080, size 0Dh: none, reg 000000FF, register after 000D0777
+EXP2 lbu 1F803FFF, size 0Dh: none, reg 000000FF, register after 000D0777
+EXP2 lbu 1F802001, size 0: exception 7, reg 5A5A5A5A, register after 00000777
+EXP1 lbu 1F07FFFF, size 13h: none, reg 000000FF, register after 0013243F
+EXP1 lbu 1F080000, size 13h: exception 7, reg 5A5A5A5A, register after 0013243F
+EXP1 lbu 1F080000, size 14h: none, reg 000000FF, register after 0014243F
+EXP1 lbu 1F000001, size 0: exception 7, reg 5A5A5A5A, register after 0000243F
+SPU lhu 1F801C02, size 0: none, reg 00000000, register after 220031E1
+SPU lhu 1F801D80, size 0: none, reg 00000000, register after 220031E1
+CDROM lbu 1F801803, size 0: none, reg 000000E0, register after 00000943
+BIOS lw BFC80100, size 13h: none, reg 00000001, register after 0013243F
+BIOS lw BFC80100, size 14h: none, reg 19951204, register after 0014243F
+BIOS lw BFF80100, size 16h: none, reg 19951204, register after 0016243F
+BIOS lw BFE00100, size 16h: none, reg 19951204, register after 0016243F
+After: EXP1 0013243F EXP2 00070777 EXP3 00003022 BIOS 0013243F SPU 220931E1 CDROM 00020943
+KSEG2 lw FFFE0000: none, reg 00000000, register after 0001E988
+KSEG2 lw FFFE0100: none, reg 00000000, register after 0001E988
+KSEG2 lw FFFE0134: none, reg 00000000, register after 0001E988
+KSEG2 lw FFFE013C: none, reg 00000000, register after 0001E988
+KSEG2 lw FFFE0140: none, reg 00000001, register after 0001E988
+Done.
+```
+
+13RSX.txt:
+
+```
+===== 13 RSX RESERVED BITS LIVE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 1F801DAA
+
+Reserved bits of the registers in use:
+EXP1 delay bit 28: wrote 1013243F, read 0013243F, put back 0013243F, read 0013243F
+EXP1 delay bit 30: wrote 4013243F, read 0013243F, put back 0013243F, read 0013243F
+EXP1 delay bit 31: wrote 8013243F, read 8013243F, put back 0013243F, read 0013243F
+EXP3 delay bit 28: wrote 10003022, read 00003022, put back 00003022, read 00003022
+EXP3 delay bit 30: wrote 40003022, read 00003022, put back 00003022, read 00003022
+EXP3 delay bit 31: wrote 80003022, read 00003022, put back 00003022, read 00003022
+EXP2 delay bits 14-15: wrote 0007C777, read 0007C777, put back 00070777, read 00070777
+EXP2 delay bits 21-23: wrote 00E70777, read 00070777, put back 00070777, read 00070777
+EXP2 delay bits 24-27: wrote 0F070777, read 0F070777, put back 00070777, read 00070777
+EXP2 delay bit 29 flipped: wrote 20070777, read 20070777, put back 00070777, read 00070777
+EXP2 delay bit 28: wrote 10070777, read 00070777, put back 00070777, read 00070777
+EXP2 delay bit 30: wrote 40070777, read 00070777, put back 00070777, read 00070777
+EXP2 delay bit 31: wrote 80070777, read 00070777, put back 00070777, read 00070777
+CDROM delay bits 14-15: wrote 0002C943, read 0002C943, put back 00020943, read 00020943
+CDROM delay bits 21-23: wrote 00E20943, read 00020943, put back 00020943, read 00020943
+CDROM delay bits 24-27: wrote 0F020943, read 0F020943, put back 00020943, read 00020943
+CDROM delay bit 29 flipped: wrote 20020943, read 20020943, put back 00020943, read 00020943
+CDROM delay bit 28: wrote 10020943, read 00020943, put back 00020943, read 00020943
+CDROM delay bit 30: wrote 40020943, read 00020943, put back 00020943, read 00020943
+CDROM delay bit 31: wrote 80020943, read 00020943, put back 00020943, read 00020943
+SPU delay bits 14-15: wrote 2209F1E1, read 2209F1E1, put back 220931E1, read 220931E1
+SPU delay bits 21-23: wrote 22E931E1, read 220931E1, put back 220931E1, read 220931E1
+SPU delay bits 24-27: wrote 2F0931E1, read 2F0931E1, put back 220931E1, read 220931E1
+SPU delay bit 29 flipped: wrote 020931E1, read 020931E1, put back 220931E1, read 220931E1
+SPU delay bit 28: wrote 320931E1, read 220931E1, put back 220931E1, read 220931E1
+SPU delay bit 30: wrote 620931E1, read 220931E1, put back 220931E1, read 220931E1
+SPU delay bit 31: wrote A20931E1, read 220931E1, put back 220931E1, read 220931E1
+BIOS delay bits 14-15: wrote 0013E43F, read 0013E43F, put back 0013243F, read 0013243F
+BIOS delay bits 21-23: wrote 00F3243F, read 0013243F, put back 0013243F, read 0013243F
+BIOS delay bits 24-27: wrote 0F13243F, read 0F13243F, put back 0013243F, read 0013243F
+BIOS delay bit 29 flipped: wrote 2013243F, read 2013243F, put back 0013243F, read 0013243F
+BIOS delay bit 28: wrote 1013243F, read 0013243F, put back 0013243F, read 0013243F
+BIOS delay bit 30: wrote 4013243F, read 0013243F, put back 0013243F, read 0013243F
+BIOS delay bit 31: wrote 8013243F, read 0013243F, put back 0013243F, read 0013243F
+EXP1 base FF000000: wrote FF000000, read 1F000000, put back 1F000000, read 1F000000
+EXP1 base 00000000: wrote 00000000, read 1F000000, put back 1F000000, read 1F000000
+Done.
+```
+
+14RAM.txt:
+
+```
+===== 14 RAM RAM SIZE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 1F801DAA
+
+RAM_SIZE read back:
+RAM_SIZE 0B8F (bits 0-2): wrote 00000B8F, read 00000B8F, put back 00000B88, read 00000B88
+RAM_SIZE 0BF8 (bits 4-6): wrote 00000BF8, read 00000BF8, put back 00000B88, read 00000B88
+RAM_SIZE FB88 (bits 12-15): wrote 0000FB88, read 0000FB88, put back 00000B88, read 00000B88
+RAM_SIZE FFFF0B88 (bits 16-31): wrote FFFF0B88, read FFFF0B88, put back 00000B88, read 00000B88
+RAM_SIZE 0888: wrote 00000888, read 00000888, put back 00000B88, read 00000B88
+Bit 7, "delay on simultaneous code and data fetch from RAM", and bit 8, by timing:
+cached code, RAM lw, 0B88: 959
+cached code, RAM lw, 0B08: 954
+cached code, RAM lw, 0A88: 957
+cached code, RAM lw, 0888: 954
+uncached code, no load, 0B88: 1902
+uncached code, no load, 0B08: 1897
+uncached code, RAM lw, 0B88: 2922
+uncached code, RAM lw, 0B08: 2701
+uncached code, RAM lw, 0A88: 2929
+uncached code, RAM lw, 0888: 2922
+uncached code, RAM lw use, 0B88: 3736
+uncached code, RAM lw use, 0B08: 3628
+uncached code, RAM sw, 0B88: 3030
+uncached code, RAM sw, 0B08: 2811
+uncached code, BIOS lw, 0B88: 5310
+uncached code, BIOS lw, 0B08: 5290
+Mirrors by setting (the word at the first address holds C0FFnnnn):
+RAM_SIZE 0B88, lw 0002F408: none, reg C0FF0B88
+RAM_SIZE 0B88, lw 0022F408: none, reg C0FF0B88
+RAM_SIZE 0B88, lw 0042F408: none, reg C0FF0B88
+RAM_SIZE 0B88, lw 0062F408: none, reg C0FF0B88
+RAM_SIZE 0B88, lw 0082F408: none, reg 00000001
+RAM_SIZE 0B88, lw 00C2F408: none, reg 00000001
+RAM_SIZE 0888, lw 0002F408: none, reg C0FF0888
+RAM_SIZE 0888, lw 0022F408: none, reg 00000001
+RAM_SIZE 0888, lw 0042F408: none, reg 00000001
+RAM_SIZE 0888, lw 0062F408: none, reg 00000001
+RAM_SIZE 0888, lw 0082F408: none, reg 00000001
+RAM_SIZE 0888, lw 00C2F408: none, reg 00000001
+RAM_SIZE 0C88, lw 0002F408: none, reg C0FF0C88
+RAM_SIZE 0C88, lw 0022F408: none, reg FFFFFFFF
+RAM_SIZE 0C88, lw 0042F408: none, reg 00000001
+RAM_SIZE 0C88, lw 0062F408: none, reg 00000001
+RAM_SIZE 0C88, lw 0082F408: none, reg 00000001
+RAM_SIZE 0C88, lw 00C2F408: none, reg 00000001
+RAM_SIZE 0F88, lw 0002F408: none, reg C0FF0F88
+RAM_SIZE 0F88, lw 0022F408: none, reg C0FF0F88
+RAM_SIZE 0F88, lw 0042F408: none, reg C0FF0F88
+RAM_SIZE 0F88, lw 0062F408: none, reg C0FF0F88
+RAM_SIZE 0F88, lw 0082F408: none, reg FFFFFFFF
+RAM_SIZE 0F88, lw 00C2F408: none, reg FFFFFFFF
+RAM_SIZE 0888, sw past 2MB:
+```
+
+### 27 September 2026 card-g3
+
+Raw output: [00RUN.txt](/tests/raw/20260927T0000Z-5501a-card-g3/memctl_safe/00RUN.txt) · [01RDB.txt](/tests/raw/20260927T0000Z-5501a-card-g3/memctl_safe/01RDB.txt) · [02RSV.txt](/tests/raw/20260927T0000Z-5501a-card-g3/memctl_safe/02RSV.txt) · [03BRT.txt](/tests/raw/20260927T0000Z-5501a-card-g3/memctl_safe/03BRT.txt) · [04SRT.txt](/tests/raw/20260927T0000Z-5501a-card-g3/memctl_safe/04SRT.txt) · [05CRT.txt](/tests/raw/20260927T0000Z-5501a-card-g3/memctl_safe/05CRT.txt) · [06XRT.txt](/tests/raw/20260927T0000Z-5501a-card-g3/memctl_safe/06XRT.txt) · [07CMA.txt](/tests/raw/20260927T0000Z-5501a-card-g3/memctl_safe/07CMA.txt) · [08CMB.txt](/tests/raw/20260927T0000Z-5501a-card-g3/memctl_safe/08CMB.txt) · [09WRT.txt](/tests/raw/20260927T0000Z-5501a-card-g3/memctl_safe/09WRT.txt) · [10SCR.txt](/tests/raw/20260927T0000Z-5501a-card-g3/memctl_safe/10SCR.txt) · [11PWR.txt](/tests/raw/20260927T0000Z-5501a-card-g3/memctl_safe/11PWR.txt) · [12WIN.txt](/tests/raw/20260927T0000Z-5501a-card-g3/memctl_safe/12WIN.txt) · [13RSX.txt](/tests/raw/20260927T0000Z-5501a-card-g3/memctl_safe/13RSX.txt) · [14BCC.txt](/tests/raw/20260927T0000Z-5501a-card-g3/memctl_safe/14BCC.txt)
+
+00RUN.txt:
+
+```
+===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+14 tests
+A chain program, linked at 80100000
+Saved on the card in slot 2, from image 1
+COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 00000480 BDAM 00000000
+BPCM 00000000 SR 40000000 Cause 00000020 EPC 80021D24 PRId 00000002
+```
+
+01RDB.txt:
+
+```
+===== 01 RDB MEMCTL READ BACK | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Memory control read back, every register at each width:
+EXP1 base 1F801000: lw 1F000000, KSEG0 1F000000, KSEG1 1F000000, lhu 0000 1F00, lbu 00 00 00 1F
+EXP2 base 1F801004: lw 1F802000, KSEG0 1F802000, KSEG1 1F802000, lhu 2000 1F80, lbu 00 20 80 1F
+EXP1 delay 1F801008: lw 0013243F, KSEG0 0013243F, KSEG1 0013243F, lhu 243F 0013, lbu 3F 24 13 00
+EXP3 delay 1F80100C: lw 00003022, KSEG0 00003022, KSEG1 00003022, lhu 3022 0000, lbu 22 30 00 00
+BIOS delay 1F801010: lw 0013243F, KSEG0 0013243F, KSEG1 0013243F, lhu 243F 0013, lbu 3F 24 13 00
+SPU delay 1F801014: lw 200931E1, KSEG0 200931E1, KSEG1 200931E1, lhu 31E1 2009, lbu E1 31 09 20
+CDROM delay 1F801018: lw 00020843, KSEG0 00020843, KSEG1 00020843, lhu 0843 0002, lbu 43 08 02 00
+EXP2 delay 1F80101C: lw 00070777, KSEG0 00070777, KSEG1 00070777, lhu 0777 0007, lbu 77 07 07 00
+COM_DELAY 1F801020: lw 00031125, KSEG0 00031125, KSEG1 00031125, lhu 1125 0003, lbu 25 11 03 00
+RAM_SIZE 1F801060: lw 00000B88, KSEG0 3C080B88, KSEG1 3C080B88, lhu 0B88 0000, lbu 88 0B 00 00
+cache control FFFE0130: lw 0001E988, lhu E988 0001, lbu 88 00 00 00
+RAM_SIZE three times: 0C040B88 0C040B88 3C040B88
+RAM_SIZE after a BIOS lw: 24840B88
+CDROM 1F801800: lw 19191919, lhu 1919, lbu 19
+SPU 1F801C00: lw 00000000, lhu 0000 0000
+Done.
+```
+
+02RSV.txt:
+
+```
+===== 02 RSV RESERVED BITS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Reserved bits, written and read back (the register put back at once):
+EXP1 base 1F0000FF: wrote 1F0000FF, read 1F0000FF, put back 1F000000, read 1F000000
+EXP1 base 1F000001: wrote 1F000001, read 1F000001, put back 1F000000, read 1F000000
+EXP1 base 1F07FFFF: wrote 1F07FFFF, read 1F07FFFF, put back 1F000000, read 1F000000
+EXP2 base 1F802001: wrote 1F802001, read 1F802001, put back 1F802000, read 1F802000
+EXP2 base 1F802080: wrote 1F802080, read 1F802080, put back 1F802000, read 1F802000
+EXP1 delay bits 14-15: wrote 0013E43F, read 0013E43F, put back 0013243F, read 0013243F
+EXP1 delay bits 21-23: wrote 00F3243F, read 0013243F, put back 0013243F, read 0013243F
+EXP1 delay bits 24-27: wrote 0F13243F, read 0F13243F, put back 0013243F, read 0013243F
+EXP1 delay bit 29: wrote 2013243F, read 2013243F, put back 0013243F, read 0013243F
+EXP1 delay low 16 all set: wrote 0013FFFF, read 0013FFFF, put back 0013243F, read 0013243F
+EXP3 delay bits 14-15: wrote 0000F022, read 0000F022, put back 00003022, read 00003022
+EXP3 delay bits 21-23: wrote 00E03022, read 00003022, put back 00003022, read 00003022
+EXP3 delay bits 24-27: wrote 0F003022, read 0F003022, put back 00003022, read 00003022
+EXP3 delay bit 29: wrote 20003022, read 20003022, put back 00003022, read 00003022
+EXP3 delay low 16 all set: wrote 0000FFFF, read 0000FFFF, put back 00003022, read 00003022
+EXP3 delay all zero: wrote 00000000, read 00000000, put back 00003022, read 00003022
+COM_DELAY bits 16-17 cleared: wrote 00001125, read 00001125, put back 00031125, read 00031125
+COM_DELAY bits 16-31 set: wrote FFFF1125, read 00031125, put back 00031125, read 00031125
+COM_DELAY bit 18 set: wrote 00071125, read 00031125, put back 00031125, read 00031125
+Done.
+```
+
+03BRT.txt:
+
+```
+===== 03 BRT BIOS READ TIMING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+BIOS reads at BFC00100, BIOS delay 0013243F:
+no load: 353
+BIOS lw, read delay 0: 1744, value FFFFFFFF
+BIOS lw, read delay 1: 2141, value 951214FF
+BIOS lw, read delay 2: 2541, value 19951204
+BIOS lw, read delay 3: 2941, value 19951204
+BIOS lw, read delay 4: 3341, value 19951204
+BIOS lw, read delay 5: 3744, value 19951204
+BIOS lw, read delay 6: 4144, value 19951204
+BIOS lw, read delay 7: 4541, value 19951204
+BIOS lw, read delay 8: 4941, value 19951204
+BIOS lw, read delay 9: 5341, value 19951204
+BIOS lw, read delay 10: 5741, value 19951204
+BIOS lw, read delay 11: 6141, value 19951204
+BIOS lw, read delay 12: 6541, value 19951204
+BIOS lw, read delay 13: 6941, value 19951204
+BIOS lw, read delay 14: 7345, value 19951204
+BIOS lw, read delay 15: 7741, value 19951204
+BIOS lhu, read delay 0: 1152, value 0000FFFF
+BIOS lhu, read delay 1: 1352, value 000016FF
+BIOS lhu, read delay 2: 1552, value 00001204
+BIOS lhu, read delay 3: 1752, value 00001204
+BIOS lhu, read delay 4: 1952, value 00001204
+BIOS lhu, read delay 5: 2152, value 00001204
+BIOS lhu, read delay 6: 2352, value 00001204
+BIOS lhu, read delay 7: 2552, value 00001204
+BIOS lhu, read delay 8: 2752, value 00001204
+BIOS lhu, read delay 9: 2952, value 00001204
+BIOS lhu, read delay 10: 3152, value 00001204
+BIOS lhu, read delay 11: 3352, value 00001204
+BIOS lhu, read delay 12: 3556, value 00001204
+BIOS lhu, read delay 13: 3756, value 00001204
+BIOS lhu, read delay 14: 3952, value 00001204
+BIOS lhu, read delay 15: 4152, value 00001204
+BIOS lbu, read delay 0: 844, value 000000FF
+BIOS lbu, read delay 1: 947, value 000000FF
+BIOS lbu, read delay 2: 1041, value 00000004
+BIOS lbu, read delay 3: 1141, value 00000004
+BIOS lbu, read delay 4: 1247, value 00000004
+BIOS lbu, read delay 5: 1345, value 00000004
+BIOS lbu, read delay 6: 1441, value 00000004
+BIOS lbu, read delay 7: 1541, value 00000004
+BIOS lbu, read delay 8: 1641, value 00000004
+BIOS lbu, read delay 9: 1745, value 00000004
+BIOS lbu, read delay 10: 1844, value 00000004
+BIOS lbu, read delay 11: 1941, value 00000004
+BIOS lbu, read delay 12: 2045, value 00000004
+BIOS lbu, read delay 13: 2141, value 00000004
+BIOS lbu, read delay 14: 2241, value 00000004
+BIOS lbu, read delay 15: 2341, value 00000004
+BIOS lw, as set (0013243F): 2944, value 19951204
+BIOS lhu, as set (0013243F): 1752, value 00001204
+BIOS lbu, as set (0013243F): 1141, value 00000004
+BIOS lw, bit 8 flipped (0013253F): 4444, value 19951204
+BIOS lhu, bit 8 flipped (0013253F): 2255, value 00001204
+BIOS lbu, bit 8 flipped (0013253F): 1141, value 00000004
+BIOS lw, bit 9 flipped (0013263F): 2959, value 19951204
+BIOS lhu, bit 9 flipped (0013263F): 1755, value 00001204
+BIOS lbu, bit 9 flipped (0013263F): 1144, value 00000004
+BIOS lw, bit 10 flipped (0013203F): 2644, value 19951204
+BIOS lhu, bit 10 flipped (0013203F): 1655, value 00001204
+BIOS lbu, bit 10 flipped (0013203F): 1141, value 00000004
+BIOS lw, bit 11 flipped (00132C3F): 2944, value 19951204
+BIOS lhu, bit 11 flipped (00132C3F): 1755, value 00001204
+BIOS lbu, bit 11 flipped (00132C3F): 1141, value 00000004
+BIOS lw, bit 12 flipped (0013343F): 1744, value FF95FF04
+BIOS lhu, bit 12 flipped (0013343F): 1157, value 0000FF04
+BIOS lbu, bit 12 flipped (0013343F): 1144, value 00000004
+BIOS lw, bit 13 flipped (0013043F): 2944, value 04040404
+BIOS lhu, bit 13 flipped (0013043F): 1752, value 00000404
+BIOS lbu, bit 13 flipped (0013043F): 1141, value 00000004
+BIOS lw, write delay 0: 2944, value 19951204
+BIOS lw, write delay 1: 2941, value 19951204
+BIOS lw, write delay 2: 2941, value 19951204
+BIOS lw, write delay 3: 2944, value 19951204
+BIOS lw, write delay 4: 2941, value 19951204
+BIOS lw, write delay 5: 2941, value 19951204
+BIOS lw, write delay 6: 2944, value 19951204
+BIOS lw, write delay 7: 2941, value 19951204
+BIOS lw, write delay 8: 2941, value 19951204
+BIOS lw, write delay 9: 2944, value 19951204
+BIOS lw, write delay 10: 2941, value 19951204
+BIOS lw, write delay 11: 2941, value 19951204
+BIOS lw, write delay 12: 2941, value 19951204
+BIOS lw, write delay 13: 2941, value 19951204
+BIOS lw, write delay 14: 2941, value 19951204
+BIOS lw, write delay 15: 2941, value 19951204
+Done.
+```
+
+04SRT.txt:
+
+```
+===== 04 SRT SPU READ TIMING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+SPU reads at 1F801C00, SPU delay 200931E1:
+SPU lw, read delay 0: 1444, value FFFFFFFF
+SPU lw, read delay 1: 1641, value FFFFFFFF
+SPU lw, read delay 2: 1841, value FFFFFFFF
+SPU lw, read delay 3: 2044, value FFFFFFFF
+SPU lw, read delay 4: 2241, value FFFFFFFF
+SPU lw, read delay 5: 2441, value FFFFFFFF
+SPU lw, read delay 6: 2641, value FFFFFFFF
+SPU lw, read delay 7: 2844, value FFFFFFFF
+SPU lw, read delay 8: 3044, value FFFFFFFF
+SPU lw, read delay 9: 3241, value FFFFFFFF
+SPU lw, read delay 10: 3441, value FFFFFFFF
+SPU lw, read delay 11: 3654, value 00000000
+SPU lw, read delay 12: 3841, value 00000000
+SPU lw, read delay 13: 4047, value 00000000
+SPU lw, read delay 14: 4245, value 00000000
+SPU lw, read delay 15: 4447, value 00000000
+SPU lhu, read delay 0: 852, value 0000FFFF
+SPU lhu, read delay 1: 952, value 0000FFFF
+SPU lhu, read delay 2: 1052, value 0000FFFF
+SPU lhu, read delay 3: 1152, value 0000FFFF
+SPU lhu, read delay 4: 1252, value 0000FFFF
+SPU lhu, read delay 5: 1358, value 0000FFFF
+SPU lhu, read delay 6: 1452, value 0000FFFF
+SPU lhu, read delay 7: 1557, value 0000FFFF
+SPU lhu, read delay 8: 1652, value 0000FFFF
+SPU lhu, read delay 9: 1752, value 0000FFFF
+SPU lhu, read delay 10: 1853, value 0000FFFF
+SPU lhu, read delay 11: 1952, value 00000000
+SPU lhu, read delay 12: 2052, value 00000000
+SPU lhu, read delay 13: 2152, value 00000000
+SPU lhu, read delay 14: 2252, value 00000000
+SPU lhu, read delay 15: 2352, value 00000000
+SPU lbu, read delay 0: 844, value 000000FF
+SPU lbu, read delay 1: 945, value 000000FF
+SPU lbu, read delay 2: 1041, value 000000FF
+SPU lbu, read delay 3: 1141, value 000000FF
+SPU lbu, read delay 4: 1241, value 000000FF
+SPU lbu, read delay 5: 1341, value 000000FF
+SPU lbu, read delay 6: 1441, value 000000FF
+SPU lbu, read delay 7: 1541, value 000000FF
+SPU lbu, read delay 8: 1641, value 000000FF
+SPU lbu, read delay 9: 1741, value 000000FF
+SPU lbu, read delay 10: 1846, value 000000FF
+SPU lbu, read delay 11: 1941, value 00000000
+SPU lbu, read delay 12: 2044, value 00000000
+SPU lbu, read delay 13: 2146, value 00000000
+SPU lbu, read delay 14: 2241, value 00000000
+SPU lbu, read delay 15: 2341, value 00000000
+SPU lw, as set (200931E1): 4248, value 00000000
+SPU lhu, as set (200931E1): 2252, value 00000000
+SPU lbu, as set (200931E1): 2241, value 00000000
+SPU lw, bit 8 flipped (200930E1): 3844, value 00000000
+SPU lhu, bit 8 flipped (200930E1): 2252, value 00000000
+SPU lbu, bit 8 flipped (200930E1): 2241, value 00000000
+SPU lw, bit 9 flipped (200933E1): 4244, value 00000000
+SPU lhu, bit 9 flipped (200933E1): 2252, value 00000000
+SPU lbu, bit 9 flipped (200933E1): 2241, value 00000000
+SPU lw, bit 10 flipped (200935E1): 4444, value 00000000
+SPU lhu, bit 10 flipped (200935E1): 2257, value 00000000
+SPU lbu, bit 10 flipped (200935E1): 2241, value 00000000
+SPU lw, bit 11 flipped (200939E1): 4244, value 00000000
+SPU lhu, bit 11 flipped (200939E1): 2252, value 00000000
+SPU lbu, bit 11 flipped (200939E1): 2241, value 00000000
+SPU lw, bit 12 flipped (200921E1): 8244, value 00000000
+SPU lhu, bit 12 flipped (200921E1): 4252, value 00000000
+SPU lbu, bit 12 flipped (200921E1): 2244, value 00000000
+SPU lw, bit 13 flipped (200911E1): 4244, value 00000000
+SPU lhu, bit 13 flipped (200911E1): 2252, value 00000000
+SPU lbu, bit 13 flipped (200911E1): 2244, value 00000000
+SPU lw, bit 29 flipped (000931E1): 4244, value 00000000
+SPU lhu, bit 29 flipped (000931E1): 2252, value 00000000
+SPU lbu, bit 29 flipped (000931E1): 2241, value 00000000
+SPU lhu, bits 24-27 = F: 2252, value 00000000
+SPU lhu, bits 24-27 = 2 (220931E1h): 2257, value 00000000
+Done.
+```
+
+05CRT.txt:
+
+```
+===== 05 CRT CDROM READ TIMING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+CD-ROM reads at 1F801800, CDROM delay 00020843:
+CDROM lw, read delay 0: 1844, value 19191919
+CDROM lw, read delay 1: 1844, value 19191919
+CDROM lw, read delay 2: 2241, value 19191919
+CDROM lw, read delay 3: 2641, value 19191919
+CDROM lw, read delay 4: 3044, value 19191919
+CDROM lw, read delay 5: 3441, value 19191919
+CDROM lw, read delay 6: 3844, value 19191919
+CDROM lw, read delay 7: 4244, value 19191919
+CDROM lw, read delay 8: 4641, value 19191919
+CDROM lw, read delay 9: 5041, value 19191919
+CDROM lw, read delay 10: 5441, value 19191919
+CDROM lw, read delay 11: 5841, value 19191919
+CDROM lw, read delay 12: 6241, value 19191919
+CDROM lw, read delay 13: 6641, value 19191919
+CDROM lw, read delay 14: 7041, value 19191919
+CDROM lw, read delay 15: 7441, value 19191919
+CDROM lhu, read delay 0: 1252, value 00001919
+CDROM lhu, read delay 1: 1252, value 00001919
+CDROM lhu, read delay 2: 1452, value 00001919
+CDROM lhu, read delay 3: 1652, value 00001919
+CDROM lhu, read delay 4: 1852, value 00001919
+CDROM lhu, read delay 5: 2052, value 00001919
+CDROM lhu, read delay 6: 2252, value 00001919
+CDROM lhu, read delay 7: 2457, value 00001919
+CDROM lhu, read delay 8: 2652, value 00001919
+CDROM lhu, read delay 9: 2857, value 00001919
+CDROM lhu, read delay 10: 3052, value 00001919
+CDROM lhu, read delay 11: 3252, value 00001919
+CDROM lhu, read delay 12: 3452, value 00001919
+CDROM lhu, read delay 13: 3652, value 00001919
+CDROM lhu, read delay 14: 3852, value 00001919
+CDROM lhu, read delay 15: 4052, value 00001919
+CDROM lbu, read delay 0: 944, value 00000019
+CDROM lbu, read delay 1: 941, value 00000019
+CDROM lbu, read delay 2: 1041, value 00000019
+CDROM lbu, read delay 3: 1141, value 00000019
+CDROM lbu, read delay 4: 1241, value 00000019
+CDROM lbu, read delay 5: 1341, value 00000019
+CDROM lbu, read delay 6: 1441, value 00000019
+CDROM lbu, read delay 7: 1541, value 00000019
+CDROM lbu, read delay 8: 1641, value 00000019
+CDROM lbu, read delay 9: 1741, value 00000019
+CDROM lbu, read delay 10: 1844, value 00000019
+CDROM lbu, read delay 11: 1941, value 00000019
+CDROM lbu, read delay 12: 2041, value 00000019
+CDROM lbu, read delay 13: 2141, value 00000019
+CDROM lbu, read delay 14: 2241, value 00000019
+CDROM lbu, read delay 15: 2341, value 00000019
+CDROM lw, as set (00020843): 3044, value 19191919
+CDROM lhu, as set (00020843): 1857, value 00001919
+CDROM lbu, as set (00020843): 1241, value 00000019
+CDROM lw, bit 8 flipped (00020943): 4244, value 19191919
+CDROM lhu, bit 8 flipped (00020943): 2252, value 00001919
+CDROM lbu, bit 8 flipped (00020943): 1244, value 00000019
+CDROM lw, bit 9 flipped (00020A43): 3044, value 19191919
+CDROM lhu, bit 9 flipped (00020A43): 1857, value 00001919
+CDROM lbu, bit 9 flipped (00020A43): 1241, value 00000019
+CDROM lw, bit 10 flipped (00020C43): 3344, value 19191919
+CDROM lhu, bit 10 flipped (00020C43): 1952, value 00001919
+CDROM lbu, bit 10 flipped (00020C43): 1241, value 00000019
+CDROM lw, bit 11 flipped (00020043): 3059, value 19191919
+CDROM lhu, bit 11 flipped (00020043): 1852, value 00001919
+CDROM lbu, bit 11 flipped (00020043): 1241, value 00000019
+CDROM lw, bit 12 flipped (00021843): 1844, value FF19FF19
+CDROM lhu, bit 12 flipped (00021843): 1252, value 0000FF19
+CDROM lbu, bit 12 flipped (00021843): 1244, value 00000019
+Done.
+```
+
+06XRT.txt:
+
+```
+===== 06 XRT EXP READ TIMING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Expansion reads, EXP1 0013243F EXP2 00070777 EXP3 00003022:
+EXP1 lbu, read delay 0: 844, value 000000FF
+EXP1 lbu, read delay 1: 941, value 000000FF
+EXP1 lbu, read delay 2: 1041, value 000000FF
+EXP1 lbu, read delay 3: 1141, value 000000FF
+EXP1 lbu, read delay 4: 1245, value 000000FF
+EXP1 lbu, read delay 5: 1341, value 000000FF
+EXP1 lbu, read delay 6: 1443, value 000000FF
+EXP1 lbu, read delay 7: 1547, value 000000FF
+EXP1 lbu, read delay 8: 1641, value 000000FF
+EXP1 lbu, read delay 9: 1741, value 000000FF
+EXP1 lbu, read delay 10: 1841, value 000000FF
+EXP1 lbu, read delay 11: 1941, value 000000FF
+EXP1 lbu, read delay 12: 2041, value 000000FF
+EXP1 lbu, read delay 13: 2141, value 000000FF
+EXP1 lbu, read delay 14: 2241, value 000000FF
+EXP1 lbu, read delay 15: 2341, value 000000FF
+EXP2 lbu, read delay 0: 846, value 000000FF
+EXP2 lbu, read delay 1: 941, value 000000FF
+EXP2 lbu, read delay 2: 1043, value 000000FF
+EXP2 lbu, read delay 3: 1141, value 000000FF
+EXP2 lbu, read delay 4: 1244, value 000000FF
+EXP2 lbu, read delay 5: 1341, value 000000FF
+EXP2 lbu, read delay 6: 1443, value 000000FF
+EXP2 lbu, read delay 7: 1547, value 000000FF
+EXP2 lbu, read delay 8: 1641, value 000000FF
+EXP2 lbu, read delay 9: 1741, value 000000FF
+EXP2 lbu, read delay 10: 1841, value 000000FF
+EXP2 lbu, read delay 11: 1941, value 000000FF
+EXP2 lbu, read delay 12: 2041, value 000000FF
+EXP2 lbu, read delay 13: 2141, value 000000FF
+EXP2 lbu, read delay 14: 2241, value 000000FF
+EXP2 lbu, read delay 15: 2341, value 000000FF
+EXP2 lw, read delay 0: 3244, value FFFFFFFF
+EXP2 lw, read delay 1: 3641, value FFFFFFFF
+EXP2 lw, read delay 2: 4041, value FFFFFFFF
+EXP2 lw, read delay 3: 4441, value FFFFFFFF
+EXP2 lw, read delay 4: 4841, value FFFFFFFF
+EXP2 lw, read delay 5: 5241, value FFFFFFFF
+EXP2 lw, read delay 6: 5641, value FFFFFFFF
+EXP2 lw, read delay 7: 6041, value FFFFFFFF
+EXP2 lw, read delay 8: 6441, value FFFFFFFF
+EXP2 lw, read delay 9: 6841, value FFFFFFFF
+EXP2 lw, read delay 10: 7249, value FFFFFFFF
+EXP2 lw, read delay 11: 7641, value FFFFFFFF
+EXP2 lw, read delay 12: 8041, value FFFFFFFF
+EXP2 lw, read delay 13: 8445, value FFFFFFFF
+EXP2 lw, read delay 14: 8857, value FFFFFFFF
+EXP2 lw, read delay 15: 9241, value FFFFFFFF
+EXP3 lbu, read delay 0: 850, value 000000FF
+EXP3 lbu, read delay 1: 941, value 000000FF
+EXP3 lbu, read delay 2: 1043, value 000000FF
+EXP3 lbu, read delay 3: 1141, value 000000FF
+EXP3 lbu, read delay 4: 1241, value 000000FF
+EXP3 lbu, read delay 5: 1341, value 000000FF
+EXP3 lbu, read delay 6: 1441, value 000000FF
+EXP3 lbu, read delay 7: 1541, value 000000FF
+EXP3 lbu, read delay 8: 1641, value 000000FF
+EXP3 lbu, read delay 9: 1741, value 000000FF
+EXP3 lbu, read delay 10: 1841, value 000000FF
+EXP3 lbu, read delay 11: 1941, value 000000FF
+EXP3 lbu, read delay 12: 2041, value 000000FF
+EXP3 lbu, read delay 13: 2141, value 000000FF
+EXP3 lbu, read delay 14: 2241, value 000000FF
+EXP3 lbu, read delay 15: 2341, value 000000FF
+EXP3 lw, read delay 0: 1044, value FFFFFFFF
+EXP3 lw, read delay 1: 1244, value FFFFFFFF
+EXP3 lw, read delay 2: 1441, value FFFFFFFF
+EXP3 lw, read delay 3: 1641, value FFFFFFFF
+EXP3 lw, read delay 4: 1844, value FFFFFFFF
+EXP3 lw, read delay 5: 2041, value FFFFFFFF
+EXP3 lw, read delay 6: 2241, value FFFFFFFF
+EXP3 lw, read delay 7: 2441, value FFFFFFFF
+EXP3 lw, read delay 8: 2641, value FFFFFFFF
+EXP3 lw, read delay 9: 2841, value FFFFFFFF
+EXP3 lw, read delay 10: 3041, value FFFFFFFF
+EXP3 lw, read delay 11: 3241, value FFFFFFFF
+EXP3 lw, read delay 12: 3441, value FFFFFFFF
+EXP3 lw, read delay 13: 3641, value FFFFFFFF
+EXP3 lw, read delay 14: 3841, value FFFFFFFF
+EXP3 lw, read delay 15: 4041, value FFFFFFFF
+Done.
+```
+
+07CMA.txt:
+
+```
+===== 07 CMA COM0 COM1 SWEEP | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+COM_DELAY 00031125; COM0 with SPU (bit 8 set) and BIOS (bit 8 set here):
+SPU lhu, COM0 0: 2252
+SPU lhu, COM0 1: 2252
+SPU lhu, COM0 2: 2252
+SPU lhu, COM0 3: 2252
+SPU lhu, COM0 4: 2252
+SPU lhu, COM0 5: 2255
+SPU lhu, COM0 6: 2252
+SPU lhu, COM0 7: 2351
+SPU lhu, COM0 8: 2450
+SPU lhu, COM0 9: 2549
+SPU lhu, COM0 10: 2648
+SPU lhu, COM0 11: 2747
+SPU lhu, COM0 12: 2846
+SPU lhu, COM0 13: 2945
+SPU lhu, COM0 14: 3044
+SPU lhu, COM0 15: 3143
+SPU lw, COM0 0: 3844
+SPU lw, COM0 1: 3841
+SPU lw, COM0 2: 3941
+SPU lw, COM0 3: 4041
+SPU lw, COM0 4: 4141
+SPU lw, COM0 5: 4241
+SPU lw, COM0 6: 4341
+SPU lw, COM0 7: 4540
+SPU lw, COM0 8: 4739
+SPU lw, COM0 9: 4938
+SPU lw, COM0 10: 5137
+SPU lw, COM0 11: 5336
+SPU lw, COM0 12: 5535
+SPU lw, COM0 13: 5734
+SPU lw, COM0 14: 5936
+SPU lw, COM0 15: 6132
+BIOS+bit8 lbu, COM0 0: 1144
+BIOS+bit8 lbu, COM0 1: 1141
+BIOS+bit8 lbu, COM0 2: 1141
+BIOS+bit8 lbu, COM0 3: 1141
+BIOS+bit8 lbu, COM0 4: 1141
+BIOS+bit8 lbu, COM0 5: 1146
+BIOS+bit8 lbu, COM0 6: 1240
+BIOS+bit8 lbu, COM0 7: 1344
+BIOS+bit8 lbu, COM0 8: 1443
+BIOS+bit8 lbu, COM0 9: 1537
+BIOS+bit8 lbu, COM0 10: 1636
+BIOS+bit8 lbu, COM0 11: 1735
+BIOS+bit8 lbu, COM0 12: 1834
+BIOS+bit8 lbu, COM0 13: 1933
+BIOS+bit8 lbu, COM0 14: 2032
+BIOS+bit8 lbu, COM0 15: 2131
+BIOS+bit8 lw, COM0 0: 2946
+BIOS+bit8 lw, COM0 1: 3241
+BIOS+bit8 lw, COM0 2: 3541
+BIOS+bit8 lw, COM0 3: 3843
+BIOS+bit8 lw, COM0 4: 4141
+BIOS+bit8 lw, COM0 5: 4441
+BIOS+bit8 lw, COM0 6: 4840
+BIOS+bit8 lw, COM0 7: 5239
+BIOS+bit8 lw, COM0 8: 5638
+BIOS+bit8 lw, COM0 9: 6037
+BIOS+bit8 lw, COM0 10: 6436
+BIOS+bit8 lw, COM0 11: 6835
+BIOS+bit8 lw, COM0 12: 7234
+BIOS+bit8 lw, COM0 13: 7636
+BIOS+bit8 lw, COM0 14: 8032
+BIOS+bit8 lw, COM0 15: 8431
+COM1 with EXP2 (delay 00070777, bit 9 set):
+EXP2 lbu, COM1 0: 1544
+EXP2 lbu, COM1 1: 1541
+EXP2 lbu, COM1 2: 1541
+EXP2 lbu, COM1 3: 1541
+EXP2 lbu, COM1 4: 1541
+EXP2 lbu, COM1 5: 1541
+EXP2 lbu, COM1 6: 1541
+EXP2 lbu, COM1 7: 1541
+EXP2 lbu, COM1 8: 1541
+EXP2 lbu, COM1 9: 1541
+EXP2 lbu, COM1 10: 1541
+EXP2 lbu, COM1 11: 1541
+EXP2 lbu, COM1 12: 1541
+EXP2 lbu, COM1 13: 1541
+EXP2 lbu, COM1 14: 1545
+EXP2 lbu, COM1 15: 1541
+Bits 16-17:
+BIOS lw, COM bits 16-17 = 0: 2955
+SPU lhu, COM bits 16-17 = 0: 2252
+CDROM lbu, COM bits 16-17 = 0: 1236
+EXP2 lbu, COM bits 16-17 = 0: 1536
+BIOS lw, COM bits 16-17 = 1: 2941
+SPU lhu, COM bits 16-17 = 1: 2244
+CDROM lbu, COM bits 16-17 = 1: 1236
+EXP2 lbu, COM bits 16-17 = 1: 1536
+BIOS lw, COM bits 16-17 = 2: 2941
+SPU lhu, COM bits 16-17 = 2: 2244
+CDROM lbu, COM bits 16-17 = 2: 1236
+EXP2 lbu, COM bits 16-17 = 2: 1536
+BIOS lw, COM bits 16-17 = 3: 2941
+SPU lhu, COM bits 16-17 = 3: 2252
+CDROM lbu, COM bits 16-17 = 3: 1239
+EXP2 lbu, COM bits 16-17 = 3: 1554
+Done.
+```
+
+08CMB.txt:
+
+```
+===== 08 CMB COM2 COM3 SWEEP | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+COM2 with BIOS (bit 10 set) and CDROM (bit 10 set here):
+BIOS lbu, COM2 0: 1159
+BIOS lbu, COM2 1: 1141
+BIOS lbu, COM2 2: 1141
+BIOS lbu, COM2 3: 1141
+BIOS lbu, COM2 4: 1141
+BIOS lbu, COM2 5: 1141
+BIOS lbu, COM2 6: 1240
+BIOS lbu, COM2 7: 1339
+BIOS lbu, COM2 8: 1440
+BIOS lbu, COM2 9: 1537
+BIOS lbu, COM2 10: 1636
+BIOS lbu, COM2 11: 1735
+BIOS lbu, COM2 12: 1834
+BIOS lbu, COM2 13: 1937
+BIOS lbu, COM2 14: 2032
+BIOS lbu, COM2 15: 2131
+BIOS lw, COM2 0: 2650
+BIOS lw, COM2 1: 2941
+BIOS lw, COM2 2: 3244
+BIOS lw, COM2 3: 3541
+BIOS lw, COM2 4: 3841
+BIOS lw, COM2 5: 4141
+BIOS lw, COM2 6: 4540
+BIOS lw, COM2 7: 4939
+BIOS lw, COM2 8: 5338
+BIOS lw, COM2 9: 5737
+BIOS lw, COM2 10: 6142
+BIOS lw, COM2 11: 6535
+BIOS lw, COM2 12: 6954
+BIOS lw, COM2 13: 7339
+BIOS lw, COM2 14: 7735
+BIOS lw, COM2 15: 8131
+CDROM+bit10 lbu, COM2 0: 1244
+CDROM+bit10 lbu, COM2 1: 1241
+CDROM+bit10 lbu, COM2 2: 1246
+CDROM+bit10 lbu, COM2 3: 1241
+CDROM+bit10 lbu, COM2 4: 1241
+CDROM+bit10 lbu, COM2 5: 1241
+CDROM+bit10 lbu, COM2 6: 1345
+CDROM+bit10 lbu, COM2 7: 1439
+CDROM+bit10 lbu, COM2 8: 1538
+CDROM+bit10 lbu, COM2 9: 1637
+CDROM+bit10 lbu, COM2 10: 1736
+CDROM+bit10 lbu, COM2 11: 1835
+CDROM+bit10 lbu, COM2 12: 1934
+CDROM+bit10 lbu, COM2 13: 2033
+CDROM+bit10 lbu, COM2 14: 2132
+CDROM+bit10 lbu, COM2 15: 2231
+COM3 with CDROM (bit 11 set) and BIOS (bit 11 set here):
+CDROM lbu, COM3 0: 1244
+CDROM lbu, COM3 1: 1241
+CDROM lbu, COM3 2: 1241
+CDROM lbu, COM3 3: 1241
+CDROM lbu, COM3 4: 1241
+CDROM lbu, COM3 5: 1341
+CDROM lbu, COM3 6: 1441
+CDROM lbu, COM3 7: 1541
+CDROM lbu, COM3 8: 1641
+CDROM lbu, COM3 9: 1741
+CDROM lbu, COM3 10: 1841
+CDROM lbu, COM3 11: 1941
+CDROM lbu, COM3 12: 2041
+CDROM lbu, COM3 13: 2141
+CDROM lbu, COM3 14: 2247
+CDROM lbu, COM3 15: 2341
+CDROM lw, COM3 0: 3044
+CDROM lw, COM3 1: 3041
+CDROM lw, COM3 2: 3041
+CDROM lw, COM3 3: 3041
+CDROM lw, COM3 4: 3041
+CDROM lw, COM3 5: 3441
+CDROM lw, COM3 6: 3841
+CDROM lw, COM3 7: 4241
+CDROM lw, COM3 8: 4641
+CDROM lw, COM3 9: 5041
+CDROM lw, COM3 10: 5441
+CDROM lw, COM3 11: 5841
+CDROM lw, COM3 12: 6241
+CDROM lw, COM3 13: 6645
+CDROM lw, COM3 14: 7041
+CDROM lw, COM3 15: 7441
+BIOS+bit11 lbu, COM3 0: 1141
+BIOS+bit11 lbu, COM3 1: 1141
+BIOS+bit11 lbu, COM3 2: 1141
+BIOS+bit11 lbu, COM3 3: 1141
+BIOS+bit11 lbu, COM3 4: 1241
+BIOS+bit11 lbu, COM3 5: 1341
+BIOS+bit11 lbu, COM3 6: 1441
+BIOS+bit11 lbu, COM3 7: 1541
+BIOS+bit11 lbu, COM3 8: 1641
+BIOS+bit11 lbu, COM3 9: 1741
+BIOS+bit11 lbu, COM3 10: 1841
+BIOS+bit11 lbu, COM3 11: 1941
+BIOS+bit11 lbu, COM3 12: 2041
+BIOS+bit11 lbu, COM3 13: 2141
+BIOS+bit11 lbu, COM3 14: 2244
+BIOS+bit11 lbu, COM3 15: 2341
+Done.
+```
+
+09WRT.txt:
+
+```
+===== 09 WRT WRITE TIMING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Stores by write delay; SPU word 00000000, CD index 1:
+SPU sh, as set: 828
+CDROM sb, as set: 646
+POST sb, as set: 1600
+SPU sh, write delay 0: 730
+SPU sh, write delay 1: 828
+SPU sh, write delay 2: 926
+SPU sh, write delay 3: 1024
+SPU sh, write delay 4: 1122
+SPU sh, write delay 5: 1201
+SPU sh, write delay 6: 1305
+SPU sh, write delay 7: 1402
+SPU sh, write delay 8: 1499
+SPU sh, write delay 9: 1596
+SPU sh, write delay 10: 1693
+SPU sh, write delay 11: 1790
+SPU sh, write delay 12: 1887
+SPU sh, write delay 13: 1984
+SPU sh, write delay 14: 2081
+SPU sh, write delay 15: 2178
+SPU sw, write delay 0: 1317
+SPU sw, write delay 1: 1512
+SPU sw, write delay 2: 1708
+SPU sw, write delay 3: 1904
+SPU sw, write delay 4: 2100
+SPU sw, write delay 5: 2296
+SPU sw, write delay 6: 2492
+SPU sw, write delay 7: 2688
+SPU sw, write delay 8: 2884
+SPU sw, write delay 9: 3080
+SPU sw, write delay 10: 3276
+SPU sw, write delay 11: 3475
+SPU sw, write delay 12: 3673
+SPU sw, write delay 13: 3864
+SPU sw, write delay 14: 4060
+SPU sw, write delay 15: 4256
+CDROM sb, write delay 0: 455
+CDROM sb, write delay 1: 455
+CDROM sb, write delay 2: 549
+CDROM sb, write delay 3: 646
+CDROM sb, write delay 4: 743
+CDROM sb, write delay 5: 840
+CDROM sb, write delay 6: 942
+CDROM sb, write delay 7: 1035
+CDROM sb, write delay 8: 1133
+CDROM sb, write delay 9: 1212
+CDROM sb, write delay 10: 1316
+CDROM sb, write delay 11: 1413
+CDROM sb, write delay 12: 1511
+CDROM sb, write delay 13: 1609
+CDROM sb, write delay 14: 1700
+CDROM sb, write delay 15: 1805
+POST sb, write delay 0: 933
+POST sb, write delay 1: 1031
+POST sb, write delay 2: 1129
+POST sb, write delay 3: 1208
+POST sb, write delay 4: 1312
+POST sb, write delay 5: 1409
+POST sb, write delay 6: 1507
+POST sb, write delay 7: 1605
+POST sb, write delay 8: 1703
+POST sb, write delay 9: 1801
+POST sb, write delay 10: 1899
+POST sb, write delay 11: 1997
+POST sb, write delay 12: 2100
+POST sb, write delay 13: 2193
+POST sb, write delay 14: 2291
+POST sb, write delay 15: 2389
+POST sb, COM1 0: 1409
+POST sb, COM1 1: 1507
+POST sb, COM1 2: 1605
+POST sb, COM1 3: 1703
+POST sb, COM1 4: 1801
+POST sb, COM1 5: 1899
+POST sb, COM1 6: 1997
+POST sb, COM1 7: 2095
+POST sb, COM1 8: 2193
+POST sb, COM1 9: 2291
+POST sb, COM1 10: 2389
+POST sb, COM1 11: 2487
+POST sb, COM1 12: 2585
+POST sb, COM1 13: 2683
+POST sb, COM1 14: 2781
+POST sb, COM1 15: 2879
+SPU sh, bit 9 (hold) set: 1024
+CDROM sb, bit 9 (hold) set: 835
+POST sb, bit 9 (hold) cleared: 1404
+SPU word after: 00000000; CD index after: 1
+SPU word put back: 00000000; CD index: 1
+Done.
+```
+
+10SCR.txt:
+
+```
+===== 10 SCR SCRATCHPAD | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Scratchpad and RAM loads and stores (100 each):
+no load: 353
+scratchpad KUSEG lw: 447
+scratchpad KUSEG lhu: 458
+scratchpad KUSEG lbu: 442
+scratchpad KUSEG lw, use: 552
+scratchpad KUSEG sw: 454
+scratchpad KUSEG sh: 451
+scratchpad KUSEG sb: 454
+scratchpad KSEG0 lw: 442
+scratchpad KSEG0 lw, use: 545
+scratchpad KSEG0 sw: 454
+scratchpad last word lw: 442
+RAM KSEG0 lw: 959
+RAM KSEG0 lw, use: 959
+RAM KSEG0 sw: 462
+RAM KSEG1 lw: 954
+Code from KSEG1 (uncached):
+uncached, no load: 1904
+uncached, scratchpad lw: 2514
+uncached, scratchpad sw: 2514
+uncached, RAM lw: 2930
+scratchpad 1F800100 5C4A0100, 9F800100 5C4A0100, 1F8003FC 5C4A03FC, 9F8003FC 5C4A03FC
+Done.
+```
+
+11PWR.txt:
+
+```
+===== 11 PWR NARROW WRITES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Narrow stores, EXP3 delay 00003022, COM_DELAY 00031125, BCC 0001E988:
+EXP3 delay sh +0: rt 05003022, read 05003022, put back 00003022
+EXP3 delay sb +0: rt 05003022, read 05003022, put back 00003022
+EXP3 delay sh +2: rt 00003022, read 20020000, put back 00003022
+EXP3 delay sb +1: rt 00003022, read 00102200, put back 00003022
+EXP3 delay sb +2: rt 00003022, read 20020000, put back 00003022
+EXP3 delay sb +3: rt 00003022, read 22000000, put back 00003022
+COM_DELAY sh +0: rt FFFF1125, read 00031125, put back 00031125
+COM_DELAY sb +1: rt 00031125, read 00012500, put back 00031125
+RAM_SIZE sh +0: rt ABCD0B88, read ABCD0B88, put back 00000B88
+BCC sh +0: rt 0005E988, read 0005E988, put back 0001E988
+BCC sb +0: rt 0005E988, read 0005E988, put back 0001E988
+BCC sh +2: rt 0005E988, read 0001E988, put back 0001E988
+BCC sb +1: rt 0005E988, read 0001E988, put back 0001E988
+Done.
+```
+
+12WIN.txt:
+
+```
+===== 12 WIN WINDOW SIZE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Window sizes and bit 28:
+EXP3 lbu 1FA00000, size 0: none, reg 000000FF, register after 00003022
+EXP3 lbu 1FA00001, size 0: exception 7, reg 5A5A5A5A, register after 00003022
+EXP3 lbu 1FA00002, size 0: exception 7, reg 5A5A5A5A, register after 00003022
+EXP3 lhu 1FA00002, size 0: exception 7, reg 5A5A5A5A, register after 00003022
+EXP3 delay bit 28 written 1: wrote 10003022, read 00003022, put back 00003022, read 00003022
+EXP3 lbu 1FA00001, size 1: none, reg 000000FF, register after 00013022
+EXP3 lbu 1FA00002, size 1: exception 7, reg 5A5A5A5A, register after 00013022
+EXP3 lbu 1FBFFFFF, size 15h: none, reg 000000FF, register after 00153022
+EXP2 lbu 1F80207F, size 7: none, reg 000000FF, register after 00070777
+EXP2 lbu 1F802080, size 7: exception 7, reg 5A5A5A5A, register after 00070777
+EXP2 lbu 1F802080, size 0Dh: none, reg 000000FF, register after 000D0777
+EXP2 lbu 1F803FFF, size 0Dh: none, reg 000000FF, register after 000D0777
+EXP2 lbu 1F802001, size 0: exception 7, reg 5A5A5A5A, register after 00000777
+EXP1 lbu 1F07FFFF, size 13h: none, reg 000000FF, register after 0013243F
+EXP1 lbu 1F080000, size 13h: exception 7, reg 5A5A5A5A, register after 0013243F
+EXP1 lbu 1F080000, size 14h: none, reg 000000FF, register after 0014243F
+EXP1 lbu 1F000001, size 0: exception 7, reg 5A5A5A5A, register after 0000243F
+SPU lhu 1F801C02, size 0: none, reg 00000000, register after 200031E1
+SPU lhu 1F801D80, size 0: none, reg 00000000, register after 200031E1
+CDROM lbu 1F801803, size 0: none, reg 000000E0, register after 00000843
+BIOS lw BFC80100, size 13h: none, reg 00000001, register after 0013243F
+BIOS lw BFC80100, size 14h: none, reg 19951204, register after 0014243F
+BIOS lw BFF80100, size 16h: none, reg 19951204, register after 0016243F
+BIOS lw BFE00100, size 16h: none, reg 19951204, register after 0016243F
+After: EXP1 0013243F EXP2 00070777 EXP3 00003022 BIOS 0013243F SPU 200931E1 CDROM 00020843
+KSEG2 lw FFFE0000: none, reg 00000000, register after 0001E988
+KSEG2 lw FFFE0100: none, reg 00000000, register after 0001E988
+KSEG2 lw FFFE0134: none, reg 00000000, register after 0001E988
+KSEG2 lw FFFE013C: none, reg 00000000, register after 0001E988
+KSEG2 lw FFFE0140: none, reg 00000001, register after 0001E988
+Done.
+```
+
+13RSX.txt:
+
+```
+===== 13 RSX RESERVED BITS LIVE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Reserved bits of the registers in use:
+EXP1 delay bit 28: wrote 1013243F, read 0013243F, put back 0013243F, read 0013243F
+EXP1 delay bit 30: wrote 4013243F, read 0013243F, put back 0013243F, read 0013243F
+EXP1 delay bit 31: wrote 8013243F, read 8013243F, put back 0013243F, read 0013243F
+EXP3 delay bit 28: wrote 10003022, read 00003022, put back 00003022, read 00003022
+EXP3 delay bit 30: wrote 40003022, read 00003022, put back 00003022, read 00003022
+EXP3 delay bit 31: wrote 80003022, read 00003022, put back 00003022, read 00003022
+EXP2 delay bits 14-15: wrote 0007C777, read 0007C777, put back 00070777, read 00070777
+EXP2 delay bits 21-23: wrote 00E70777, read 00070777, put back 00070777, read 00070777
+EXP2 delay bits 24-27: wrote 0F070777, read 0F070777, put back 00070777, read 00070777
+EXP2 delay bit 29 flipped: wrote 20070777, read 20070777, put back 00070777, read 00070777
+EXP2 delay bit 28: wrote 10070777, read 00070777, put back 00070777, read 00070777
+EXP2 delay bit 30: wrote 40070777, read 00070777, put back 00070777, read 00070777
+EXP2 delay bit 31: wrote 80070777, read 00070777, put back 00070777, read 00070777
+CDROM delay bits 14-15: wrote 0002C843, read 0002C843, put back 00020843, read 00020843
+CDROM delay bits 21-23: wrote 00E20843, read 00020843, put back 00020843, read 00020843
+CDROM delay bits 24-27: wrote 0F020843, read 0F020843, put back 00020843, read 00020843
+CDROM delay bit 29 flipped: wrote 20020843, read 20020843, put back 00020843, read 00020843
+CDROM delay bit 28: wrote 10020843, read 00020843, put back 00020843, read 00020843
+CDROM delay bit 30: wrote 40020843, read 00020843, put back 00020843, read 00020843
+CDROM delay bit 31: wrote 80020843, read 00020843, put back 00020843, read 00020843
+SPU delay bits 14-15: wrote 2009F1E1, read 2009F1E1, put back 200931E1, read 200931E1
+SPU delay bits 21-23: wrote 20E931E1, read 200931E1, put back 200931E1, read 200931E1
+SPU delay bits 24-27: wrote 2F0931E1, read 2F0931E1, put back 200931E1, read 200931E1
+SPU delay bit 29 flipped: wrote 000931E1, read 000931E1, put back 200931E1, read 200931E1
+SPU delay bit 28: wrote 300931E1, read 200931E1, put back 200931E1, read 200931E1
+SPU delay bit 30: wrote 600931E1, read 200931E1, put back 200931E1, read 200931E1
+SPU delay bit 31: wrote A00931E1, read 200931E1, put back 200931E1, read 200931E1
+BIOS delay bits 14-15: wrote 0013E43F, read 0013E43F, put back 0013243F, read 0013243F
+BIOS delay bits 21-23: wrote 00F3243F, read 0013243F, put back 0013243F, read 0013243F
+BIOS delay bits 24-27: wrote 0F13243F, read 0F13243F, put back 0013243F, read 0013243F
+BIOS delay bit 29 flipped: wrote 2013243F, read 2013243F, put back 0013243F, read 0013243F
+BIOS delay bit 28: wrote 1013243F, read 0013243F, put back 0013243F, read 0013243F
+BIOS delay bit 30: wrote 4013243F, read 0013243F, put back 0013243F, read 0013243F
+BIOS delay bit 31: wrote 8013243F, read 0013243F, put back 0013243F, read 0013243F
+EXP1 base FF000000: wrote FF000000, read 1F000000, put back 1F000000, read 1F000000
+EXP1 base 00000000: wrote 00000000, read 1F000000, put back 1F000000, read 1F000000
+Done.
+```
+
+14BCC.txt:
+
+```
+===== 14 BCC CACHE CONTROL | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Cache control 0001E988, read back:
+BCC bits 18-31: wrote FFFDE988, read FFFDE988, put back 0001E988, read 0001E988
+BCC bit 6: wrote 0001E9C8, read 0001E988, put back 0001E988, read 0001E988
+BCC bit 17: wrote 0003E988, read 0003E988, put back 0001E988, read 0001E988
+BCC bit 12: wrote 0001F988, read 0001F988, put back 0001E988, read 0001E988
+BCC bit 10 (IS0): wrote 0001ED88, read 0001E988, put back 0001E988, read 0001E988
+Loads by BCC bit (100 each):
+RAM lw, as set: 961
+scratchpad lw, as set: 442
+RAM lw use, as set: 956
+RAM lw, bit 16 LDSCH (0000E988): 1064
+scratchpad lw, bit 16 LDSCH: 442
+RAM lw use, bit 16 LDSCH: 1167
+RAM lw, bit 14 NOPAD (0001A988): 970
+scratchpad lw, bit 14 NOPAD: 453
+RAM lw use, bit 14 NOPAD: 963
+RAM lw, bit 13 RDPRI (0001C988): 957
+scratchpad lw, bit 13 RDPRI: 442
+RAM lw use, bit 13 RDPRI: 966
+RAM lw, bit 15 BGNT (00016988): 957
+scratchpad lw, bit 15 BGNT: 442
+RAM lw use, bit 15 BGNT: 956
+RAM lw, bit 12 INTP (0001F988): 964
+scratchpad lw, bit 12 INTP: 447
+RAM lw use, bit 12 INTP: 961
+RAM lw, bit 17 NOSTR (0003E988): 984
+scratchpad lw, bit 17 NOSTR: 459
+RAM lw use, bit 17 NOSTR: 963
+RAM lw, DBLKSZ 1 (0001E998): 958
+scratchpad lw, DBLKSZ 1: 442
+RAM lw use, DBLKSZ 1: 961
+RAM lw, DBLKSZ 2 (0001E9A8): 958
+scratchpad lw, DBLKSZ 2: 442
+RAM lw use, DBLKSZ 2: 961
+RAM lw, DBLKSZ 3 (0001E9B8): 959
+scratchpad lw, DBLKSZ 3: 442
+RAM lw use, DBLKSZ 3: 964
+D-cache mode (bit 3 cleared, bit 7 set), one access; slot = (address >> 2) & FFh:
+KSEG0 lw: loaded 0DA7A000, scratchpad 1F8003E8 now 0DA7A000, RAM word 0DA7A000, BCC 0001E988
+KSEG0 lbu +1: loaded 000000A0, scratchpad 1F8003E8 now 0DA7A000, RAM word 0DA7A000, BCC 0001E988
+KSEG1 lw: loaded 0DA7A000, scratchpad 1F8003E8 now DEAD03E8, RAM word 0DA7A000, BCC 0001E988
+KSEG0 sw: loaded 00000000, scratchpad 1F8003E8 now DEAD03E8, RAM word 5EED0000, BCC 0001E988
+Done.
+```
+
+### 28 September 2026 card-h
+
+Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/00RUN.txt) · [01RDB.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/01RDB.txt) · [02RSV.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/02RSV.txt) · [03BRT.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/03BRT.txt) · [04SRT.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/04SRT.txt) · [05CRT.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/05CRT.txt) · [06XRT.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/06XRT.txt) · [07CMA.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/07CMA.txt) · [08CMB.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/08CMB.txt) · [09WRT.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/09WRT.txt) · [10SCR.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/10SCR.txt) · [11PWR.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/11PWR.txt) · [12WIN.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/12WIN.txt) · [13RSX.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/13RSX.txt) · [14BCC.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/14BCC.txt)
+
+00RUN.txt:
+
+```
+===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+14 tests
+A chain program, linked at 80100000
+Saved on the card in slot 2, from image 1
+COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 00000480 BDAM 00000000
+BPCM 00000000 SR 40000000 Cause 00000020 EPC 80021D24 PRId 00000002
+```
+
+01RDB.txt:
+
+```
+===== 01 RDB MEMCTL READ BACK | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Memory control read back, every register at each width:
+EXP1 base 1F801000: lw 1F000000, KSEG0 1F000000, KSEG1 1F000000, lhu 0000 1F00, lbu 00 00 00 1F
+EXP2 base 1F801004: lw 1F802000, KSEG0 1F802000, KSEG1 1F802000, lhu 2000 1F80, lbu 00 20 80 1F
+EXP1 delay 1F801008: lw 0013243F, KSEG0 0013243F, KSEG1 0013243F, lhu 243F 0013, lbu 3F 24 13 00
+EXP3 delay 1F80100C: lw 00003022, KSEG0 00003022, KSEG1 00003022, lhu 3022 0000, lbu 22 30 00 00
+BIOS delay 1F801010: lw 0013243F, KSEG0 0013243F, KSEG1 0013243F, lhu 243F 0013, lbu 3F 24 13 00
+SPU delay 1F801014: lw 200931E1, KSEG0 200931E1, KSEG1 200931E1, lhu 31E1 2009, lbu E1 31 09 20
+CDROM delay 1F801018: lw 00020843, KSEG0 00020843, KSEG1 00020843, lhu 0843 0002, lbu 43 08 02 00
+EXP2 delay 1F80101C: lw 00070777, KSEG0 00070777, KSEG1 00070777, lhu 0777 0007, lbu 77 07 07 00
+COM_DELAY 1F801020: lw 00031125, KSEG0 00031125, KSEG1 00031125, lhu 1125 0003, lbu 25 11 03 00
+RAM_SIZE 1F801060: lw 00000B88, KSEG0 3C080B88, KSEG1 3C080B88, lhu 0B88 0000, lbu 88 0B 00 00
+cache control FFFE0130: lw 0001E988, lhu E988 0001, lbu 88 00 00 00
+RAM_SIZE three times: 0C040B88 0C040B88 3C040B88
+RAM_SIZE after a BIOS lw: 24840B88
+CDROM 1F801800: lw 19191919, lhu 1919, lbu 19
+SPU 1F801C00: lw 00000000, lhu 0000 0000
+Done.
+```
+
+02RSV.txt:
+
+```
+===== 02 RSV RESERVED BITS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Reserved bits, written and read back (the register put back at once):
+EXP1 base 1F0000FF: wrote 1F0000FF, read 1F0000FF, put back 1F000000, read 1F000000
+EXP1 base 1F000001: wrote 1F000001, read 1F000001, put back 1F000000, read 1F000000
+EXP1 base 1F07FFFF: wrote 1F07FFFF, read 1F07FFFF, put back 1F000000, read 1F000000
+EXP2 base 1F802001: wrote 1F802001, read 1F802001, put back 1F802000, read 1F802000
+EXP2 base 1F802080: wrote 1F802080, read 1F802080, put back 1F802000, read 1F802000
+EXP1 delay bits 14-15: wrote 0013E43F, read 0013E43F, put back 0013243F, read 0013243F
+EXP1 delay bits 21-23: wrote 00F3243F, read 0013243F, put back 0013243F, read 0013243F
+EXP1 delay bits 24-27: wrote 0F13243F, read 0F13243F, put back 0013243F, read 0013243F
+EXP1 delay bit 29: wrote 2013243F, read 2013243F, put back 0013243F, read 0013243F
+EXP1 delay low 16 all set: wrote 0013FFFF, read 0013FFFF, put back 0013243F, read 0013243F
+EXP3 delay bits 14-15: wrote 0000F022, read 0000F022, put back 00003022, read 00003022
+EXP3 delay bits 21-23: wrote 00E03022, read 00003022, put back 00003022, read 00003022
+EXP3 delay bits 24-27: wrote 0F003022, read 0F003022, put back 00003022, read 00003022
+EXP3 delay bit 29: wrote 20003022, read 20003022, put back 00003022, read 00003022
+EXP3 delay low 16 all set: wrote 0000FFFF, read 0000FFFF, put back 00003022, read 00003022
+EXP3 delay all zero: wrote 00000000, read 00000000, put back 00003022, read 00003022
+COM_DELAY bits 16-17 cleared: wrote 00001125, read 00001125, put back 00031125, read 00031125
+COM_DELAY bits 16-31 set: wrote FFFF1125, read 00031125, put back 00031125, read 00031125
+COM_DELAY bit 18 set: wrote 00071125, read 00031125, put back 00031125, read 00031125
+Done.
+```
+
+03BRT.txt:
+
+```
+===== 03 BRT BIOS READ TIMING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+BIOS reads at BFC00100, BIOS delay 0013243F:
+no load: 357
+BIOS lw, read delay 0: 1744, value FFFFFFFF
+BIOS lw, read delay 1: 2141, value 951214FF
+BIOS lw, read delay 2: 2544, value 19951204
+BIOS lw, read delay 3: 2941, value 19951204
+BIOS lw, read delay 4: 3344, value 19951204
+BIOS lw, read delay 5: 3741, value 19951204
+BIOS lw, read delay 6: 4141, value 19951204
+BIOS lw, read delay 7: 4544, value 19951204
+BIOS lw, read delay 8: 4944, value 19951204
+BIOS lw, read delay 9: 5341, value 19951204
+BIOS lw, read delay 10: 5741, value 19951204
+BIOS lw, read delay 11: 6141, value 19951204
+BIOS lw, read delay 12: 6541, value 19951204
+BIOS lw, read delay 13: 6941, value 19951204
+BIOS lw, read delay 14: 7341, value 19951204
+BIOS lw, read delay 15: 7741, value 19951204
+BIOS lhu, read delay 0: 1152, value 0000FFFF
+BIOS lhu, read delay 1: 1352, value 000016FF
+BIOS lhu, read delay 2: 1552, value 00001204
+BIOS lhu, read delay 3: 1752, value 00001204
+BIOS lhu, read delay 4: 1952, value 00001204
+BIOS lhu, read delay 5: 2152, value 00001204
+BIOS lhu, read delay 6: 2352, value 00001204
+BIOS lhu, read delay 7: 2552, value 00001204
+BIOS lhu, read delay 8: 2752, value 00001204
+BIOS lhu, read delay 9: 2952, value 00001204
+BIOS lhu, read delay 10: 3152, value 00001204
+BIOS lhu, read delay 11: 3352, value 00001204
+BIOS lhu, read delay 12: 3552, value 00001204
+BIOS lhu, read delay 13: 3752, value 00001204
+BIOS lhu, read delay 14: 3952, value 00001204
+BIOS lhu, read delay 15: 4155, value 00001204
+BIOS lbu, read delay 0: 844, value 000000FF
+BIOS lbu, read delay 1: 941, value 000000FF
+BIOS lbu, read delay 2: 1041, value 00000004
+BIOS lbu, read delay 3: 1147, value 00000004
+BIOS lbu, read delay 4: 1241, value 00000004
+BIOS lbu, read delay 5: 1341, value 00000004
+BIOS lbu, read delay 6: 1447, value 00000004
+BIOS lbu, read delay 7: 1541, value 00000004
+BIOS lbu, read delay 8: 1647, value 00000004
+BIOS lbu, read delay 9: 1741, value 00000004
+BIOS lbu, read delay 10: 1844, value 00000004
+BIOS lbu, read delay 11: 1941, value 00000004
+BIOS lbu, read delay 12: 2041, value 00000004
+BIOS lbu, read delay 13: 2141, value 00000004
+BIOS lbu, read delay 14: 2254, value 00000004
+BIOS lbu, read delay 15: 2341, value 00000004
+BIOS lw, as set (0013243F): 2944, value 19951204
+BIOS lhu, as set (0013243F): 1752, value 00001204
+BIOS lbu, as set (0013243F): 1141, value 00000004
+BIOS lw, bit 8 flipped (0013253F): 4444, value 19951204
+BIOS lhu, bit 8 flipped (0013253F): 2255, value 00001204
+BIOS lbu, bit 8 flipped (0013253F): 1141, value 00000004
+BIOS lw, bit 9 flipped (0013263F): 2944, value 19951204
+BIOS lhu, bit 9 flipped (0013263F): 1752, value 00001204
+BIOS lbu, bit 9 flipped (0013263F): 1154, value 00000004
+BIOS lw, bit 10 flipped (0013203F): 2644, value 19951204
+BIOS lhu, bit 10 flipped (0013203F): 1652, value 00001204
+BIOS lbu, bit 10 flipped (0013203F): 1141, value 00000004
+BIOS lw, bit 11 flipped (00132C3F): 2948, value 19951204
+BIOS lhu, bit 11 flipped (00132C3F): 1752, value 00001204
+BIOS lbu, bit 11 flipped (00132C3F): 1141, value 00000004
+BIOS lw, bit 12 flipped (0013343F): 1744, value FF95FF04
+BIOS lhu, bit 12 flipped (0013343F): 1152, value 0000FF04
+BIOS lbu, bit 12 flipped (0013343F): 1144, value 00000004
+BIOS lw, bit 13 flipped (0013043F): 2948, value 04040404
+BIOS lhu, bit 13 flipped (0013043F): 1752, value 00000404
+BIOS lbu, bit 13 flipped (0013043F): 1141, value 00000004
+BIOS lw, write delay 0: 2944, value 19951204
+BIOS lw, write delay 1: 2941, value 19951204
+BIOS lw, write delay 2: 2941, value 19951204
+BIOS lw, write delay 3: 2941, value 19951204
+BIOS lw, write delay 4: 2944, value 19951204
+BIOS lw, write delay 5: 2941, value 19951204
+BIOS lw, write delay 6: 2941, value 19951204
+BIOS lw, write delay 7: 2944, value 19951204
+BIOS lw, write delay 8: 2941, value 19951204
+BIOS lw, write delay 9: 2941, value 19951204
+BIOS lw, write delay 10: 2941, value 19951204
+BIOS lw, write delay 11: 2941, value 19951204
+BIOS lw, write delay 12: 2941, value 19951204
+BIOS lw, write delay 13: 2941, value 19951204
+BIOS lw, write delay 14: 2941, value 19951204
+BIOS lw, write delay 15: 2941, value 19951204
+Done.
+```
+
+04SRT.txt:
+
+```
+===== 04 SRT SPU READ TIMING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+SPU reads at 1F801C00, SPU delay 200931E1:
+SPU lw, read delay 0: 1444, value FFFFFFFF
+SPU lw, read delay 1: 1641, value FFFFFFFF
+SPU lw, read delay 2: 1841, value FFFFFFFF
+SPU lw, read delay 3: 2044, value FFFFFFFF
+SPU lw, read delay 4: 2241, value FFFFFFFF
+SPU lw, read delay 5: 2441, value FFFFFFFF
+SPU lw, read delay 6: 2641, value FFFFFFFF
+SPU lw, read delay 7: 2844, value FFFFFFFF
+SPU lw, read delay 8: 3044, value FFFFFFFF
+SPU lw, read delay 9: 3241, value FFFFFFFF
+SPU lw, read delay 10: 3441, value FFFFFFFF
+SPU lw, read delay 11: 3654, value 00000000
+SPU lw, read delay 12: 3841, value 00000000
+SPU lw, read delay 13: 4047, value 00000000
+SPU lw, read delay 14: 4245, value 00000000
+SPU lw, read delay 15: 4447, value 00000000
+SPU lhu, read delay 0: 852, value 0000FFFF
+SPU lhu, read delay 1: 952, value 0000FFFF
+SPU lhu, read delay 2: 1052, value 0000FFFF
+SPU lhu, read delay 3: 1152, value 0000FFFF
+SPU lhu, read delay 4: 1252, value 0000FFFF
+SPU lhu, read delay 5: 1354, value 0000FFFF
+SPU lhu, read delay 6: 1452, value 0000FFFF
+SPU lhu, read delay 7: 1557, value 0000FFFF
+SPU lhu, read delay 8: 1652, value 0000FFFF
+SPU lhu, read delay 9: 1752, value 0000FFFF
+SPU lhu, read delay 10: 1853, value 0000FFFF
+SPU lhu, read delay 11: 1952, value 00000000
+SPU lhu, read delay 12: 2052, value 00000000
+SPU lhu, read delay 13: 2152, value 00000000
+SPU lhu, read delay 14: 2252, value 00000000
+SPU lhu, read delay 15: 2352, value 00000000
+SPU lbu, read delay 0: 844, value 000000FF
+SPU lbu, read delay 1: 945, value 000000FF
+SPU lbu, read delay 2: 1041, value 000000FF
+SPU lbu, read delay 3: 1141, value 000000FF
+SPU lbu, read delay 4: 1241, value 000000FF
+SPU lbu, read delay 5: 1341, value 000000FF
+SPU lbu, read delay 6: 1441, value 000000FF
+SPU lbu, read delay 7: 1541, value 000000FF
+SPU lbu, read delay 8: 1641, value 000000FF
+SPU lbu, read delay 9: 1741, value 000000FF
+SPU lbu, read delay 10: 1846, value 000000FF
+SPU lbu, read delay 11: 1941, value 00000000
+SPU lbu, read delay 12: 2044, value 00000000
+SPU lbu, read delay 13: 2146, value 00000000
+SPU lbu, read delay 14: 2241, value 00000000
+SPU lbu, read delay 15: 2341, value 00000000
+SPU lw, as set (200931E1): 4248, value 00000000
+SPU lhu, as set (200931E1): 2252, value 00000000
+SPU lbu, as set (200931E1): 2241, value 00000000
+SPU lw, bit 8 flipped (200930E1): 3844, value 00000000
+SPU lhu, bit 8 flipped (200930E1): 2252, value 00000000
+SPU lbu, bit 8 flipped (200930E1): 2241, value 00000000
+SPU lw, bit 9 flipped (200933E1): 4244, value 00000000
+SPU lhu, bit 9 flipped (200933E1): 2252, value 00000000
+SPU lbu, bit 9 flipped (200933E1): 2241, value 00000000
+SPU lw, bit 10 flipped (200935E1): 4444, value 00000000
+SPU lhu, bit 10 flipped (200935E1): 2257, value 00000000
+SPU lbu, bit 10 flipped (200935E1): 2241, value 00000000
+SPU lw, bit 11 flipped (200939E1): 4244, value 00000000
+SPU lhu, bit 11 flipped (200939E1): 2252, value 00000000
+SPU lbu, bit 11 flipped (200939E1): 2241, value 00000000
+SPU lw, bit 12 flipped (200921E1): 8244, value 00000000
+SPU lhu, bit 12 flipped (200921E1): 4252, value 00000000
+SPU lbu, bit 12 flipped (200921E1): 2244, value 00000000
+SPU lw, bit 13 flipped (200911E1): 4244, value 00000000
+SPU lhu, bit 13 flipped (200911E1): 2252, value 00000000
+SPU lbu, bit 13 flipped (200911E1): 2244, value 00000000
+SPU lw, bit 29 flipped (000931E1): 4244, value 00000000
+SPU lhu, bit 29 flipped (000931E1): 2252, value 00000000
+SPU lbu, bit 29 flipped (000931E1): 2241, value 00000000
+SPU lhu, bits 24-27 = F: 2252, value 00000000
+SPU lhu, bits 24-27 = 2 (220931E1h): 2257, value 00000000
+Done.
+```
+
+05CRT.txt:
+
+```
+===== 05 CRT CDROM READ TIMING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+CD-ROM reads at 1F801800, CDROM delay 00020843:
+CDROM lw, read delay 0: 1844, value 19191919
+CDROM lw, read delay 1: 1844, value 19191919
+CDROM lw, read delay 2: 2241, value 19191919
+CDROM lw, read delay 3: 2641, value 19191919
+CDROM lw, read delay 4: 3044, value 19191919
+CDROM lw, read delay 5: 3441, value 19191919
+CDROM lw, read delay 6: 3844, value 19191919
+CDROM lw, read delay 7: 4244, value 19191919
+CDROM lw, read delay 8: 4641, value 19191919
+CDROM lw, read delay 9: 5041, value 19191919
+CDROM lw, read delay 10: 5441, value 19191919
+CDROM lw, read delay 11: 5841, value 19191919
+CDROM lw, read delay 12: 6241, value 19191919
+CDROM lw, read delay 13: 6641, value 19191919
+CDROM lw, read delay 14: 7041, value 19191919
+CDROM lw, read delay 15: 7441, value 19191919
+CDROM lhu, read delay 0: 1252, value 00001919
+CDROM lhu, read delay 1: 1252, value 00001919
+CDROM lhu, read delay 2: 1452, value 00001919
+CDROM lhu, read delay 3: 1652, value 00001919
+CDROM lhu, read delay 4: 1852, value 00001919
+CDROM lhu, read delay 5: 2052, value 00001919
+CDROM lhu, read delay 6: 2252, value 00001919
+CDROM lhu, read delay 7: 2452, value 00001919
+CDROM lhu, read delay 8: 2652, value 00001919
+CDROM lhu, read delay 9: 2852, value 00001919
+CDROM lhu, read delay 10: 3052, value 00001919
+CDROM lhu, read delay 11: 3252, value 00001919
+CDROM lhu, read delay 12: 3452, value 00001919
+CDROM lhu, read delay 13: 3655, value 00001919
+CDROM lhu, read delay 14: 3852, value 00001919
+CDROM lhu, read delay 15: 4052, value 00001919
+CDROM lbu, read delay 0: 944, value 00000019
+CDROM lbu, read delay 1: 941, value 00000019
+CDROM lbu, read delay 2: 1041, value 00000019
+CDROM lbu, read delay 3: 1141, value 00000019
+CDROM lbu, read delay 4: 1241, value 00000019
+CDROM lbu, read delay 5: 1341, value 00000019
+CDROM lbu, read delay 6: 1441, value 00000019
+CDROM lbu, read delay 7: 1541, value 00000019
+CDROM lbu, read delay 8: 1641, value 00000019
+CDROM lbu, read delay 9: 1741, value 00000019
+CDROM lbu, read delay 10: 1844, value 00000019
+CDROM lbu, read delay 11: 1941, value 00000019
+CDROM lbu, read delay 12: 2041, value 00000019
+CDROM lbu, read delay 13: 2141, value 00000019
+CDROM lbu, read delay 14: 2241, value 00000019
+CDROM lbu, read delay 15: 2341, value 00000019
+CDROM lw, as set (00020843): 3044, value 19191919
+CDROM lhu, as set (00020843): 1857, value 00001919
+CDROM lbu, as set (00020843): 1241, value 00000019
+CDROM lw, bit 8 flipped (00020943): 4244, value 19191919
+CDROM lhu, bit 8 flipped (00020943): 2252, value 00001919
+CDROM lbu, bit 8 flipped (00020943): 1244, value 00000019
+CDROM lw, bit 9 flipped (00020A43): 3044, value 19191919
+CDROM lhu, bit 9 flipped (00020A43): 1857, value 00001919
+CDROM lbu, bit 9 flipped (00020A43): 1241, value 00000019
+CDROM lw, bit 10 flipped (00020C43): 3344, value 19191919
+CDROM lhu, bit 10 flipped (00020C43): 1952, value 00001919
+CDROM lbu, bit 10 flipped (00020C43): 1241, value 00000019
+CDROM lw, bit 11 flipped (00020043): 3059, value 19191919
+CDROM lhu, bit 11 flipped (00020043): 1852, value 00001919
+CDROM lbu, bit 11 flipped (00020043): 1241, value 00000019
+CDROM lw, bit 12 flipped (00021843): 1844, value FF19FF19
+CDROM lhu, bit 12 flipped (00021843): 1252, value 0000FF19
+CDROM lbu, bit 12 flipped (00021843): 1259, value 00000019
+Done.
+```
+
+06XRT.txt:
+
+```
+===== 06 XRT EXP READ TIMING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Expansion reads, EXP1 0013243F EXP2 00070777 EXP3 00003022:
+EXP1 lbu, read delay 0: 844, value 000000FF
+EXP1 lbu, read delay 1: 941, value 000000FF
+EXP1 lbu, read delay 2: 1041, value 000000FF
+EXP1 lbu, read delay 3: 1147, value 000000FF
+EXP1 lbu, read delay 4: 1241, value 000000FF
+EXP1 lbu, read delay 5: 1347, value 000000FF
+EXP1 lbu, read delay 6: 1441, value 000000FF
+EXP1 lbu, read delay 7: 1541, value 000000FF
+EXP1 lbu, read delay 8: 1641, value 000000FF
+EXP1 lbu, read delay 9: 1747, value 000000FF
+EXP1 lbu, read delay 10: 1841, value 000000FF
+EXP1 lbu, read delay 11: 1945, value 000000FF
+EXP1 lbu, read delay 12: 2041, value 000000FF
+EXP1 lbu, read delay 13: 2141, value 000000FF
+EXP1 lbu, read delay 14: 2241, value 000000FF
+EXP1 lbu, read delay 15: 2345, value 000000FF
+EXP2 lbu, read delay 0: 841, value 000000FF
+EXP2 lbu, read delay 1: 941, value 000000FF
+EXP2 lbu, read delay 2: 1041, value 000000FF
+EXP2 lbu, read delay 3: 1141, value 000000FF
+EXP2 lbu, read delay 4: 1244, value 000000FF
+EXP2 lbu, read delay 5: 1341, value 000000FF
+EXP2 lbu, read delay 6: 1443, value 000000FF
+EXP2 lbu, read delay 7: 1547, value 000000FF
+EXP2 lbu, read delay 8: 1641, value 000000FF
+EXP2 lbu, read delay 9: 1741, value 000000FF
+EXP2 lbu, read delay 10: 1841, value 000000FF
+EXP2 lbu, read delay 11: 1941, value 000000FF
+EXP2 lbu, read delay 12: 2041, value 000000FF
+EXP2 lbu, read delay 13: 2141, value 000000FF
+EXP2 lbu, read delay 14: 2241, value 000000FF
+EXP2 lbu, read delay 15: 2341, value 000000FF
+EXP2 lw, read delay 0: 3244, value FFFFFFFF
+EXP2 lw, read delay 1: 3641, value FFFFFFFF
+EXP2 lw, read delay 2: 4041, value FFFFFFFF
+EXP2 lw, read delay 3: 4441, value FFFFFFFF
+EXP2 lw, read delay 4: 4841, value FFFFFFFF
+EXP2 lw, read delay 5: 5241, value FFFFFFFF
+EXP2 lw, read delay 6: 5641, value FFFFFFFF
+EXP2 lw, read delay 7: 6041, value FFFFFFFF
+EXP2 lw, read delay 8: 6441, value FFFFFFFF
+EXP2 lw, read delay 9: 6841, value FFFFFFFF
+EXP2 lw, read delay 10: 7249, value FFFFFFFF
+EXP2 lw, read delay 11: 7641, value FFFFFFFF
+EXP2 lw, read delay 12: 8041, value FFFFFFFF
+EXP2 lw, read delay 13: 8445, value FFFFFFFF
+EXP2 lw, read delay 14: 8857, value FFFFFFFF
+EXP2 lw, read delay 15: 9241, value FFFFFFFF
+EXP3 lbu, read delay 0: 850, value 000000FF
+EXP3 lbu, read delay 1: 941, value 000000FF
+EXP3 lbu, read delay 2: 1043, value 000000FF
+EXP3 lbu, read delay 3: 1141, value 000000FF
+EXP3 lbu, read delay 4: 1241, value 000000FF
+EXP3 lbu, read delay 5: 1341, value 000000FF
+EXP3 lbu, read delay 6: 1441, value 000000FF
+EXP3 lbu, read delay 7: 1541, value 000000FF
+EXP3 lbu, read delay 8: 1641, value 000000FF
+EXP3 lbu, read delay 9: 1741, value 000000FF
+EXP3 lbu, read delay 10: 1841, value 000000FF
+EXP3 lbu, read delay 11: 1941, value 000000FF
+EXP3 lbu, read delay 12: 2041, value 000000FF
+EXP3 lbu, read delay 13: 2141, value 000000FF
+EXP3 lbu, read delay 14: 2241, value 000000FF
+EXP3 lbu, read delay 15: 2341, value 000000FF
+EXP3 lw, read delay 0: 1044, value FFFFFFFF
+EXP3 lw, read delay 1: 1244, value FFFFFFFF
+EXP3 lw, read delay 2: 1441, value FFFFFFFF
+EXP3 lw, read delay 3: 1641, value FFFFFFFF
+EXP3 lw, read delay 4: 1844, value FFFFFFFF
+EXP3 lw, read delay 5: 2041, value FFFFFFFF
+EXP3 lw, read delay 6: 2241, value FFFFFFFF
+EXP3 lw, read delay 7: 2441, value FFFFFFFF
+EXP3 lw, read delay 8: 2641, value FFFFFFFF
+EXP3 lw, read delay 9: 2841, value FFFFFFFF
+EXP3 lw, read delay 10: 3041, value FFFFFFFF
+EXP3 lw, read delay 11: 3241, value FFFFFFFF
+EXP3 lw, read delay 12: 3441, value FFFFFFFF
+EXP3 lw, read delay 13: 3641, value FFFFFFFF
+EXP3 lw, read delay 14: 3841, value FFFFFFFF
+EXP3 lw, read delay 15: 4041, value FFFFFFFF
+Done.
+```
+
+07CMA.txt:
+
+```
+===== 07 CMA COM0 COM1 SWEEP | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+COM_DELAY 00031125; COM0 with SPU (bit 8 set) and BIOS (bit 8 set here):
+SPU lhu, COM0 0: 2266
+SPU lhu, COM0 1: 2252
+SPU lhu, COM0 2: 2253
+SPU lhu, COM0 3: 2252
+SPU lhu, COM0 4: 2252
+SPU lhu, COM0 5: 2252
+SPU lhu, COM0 6: 2255
+SPU lhu, COM0 7: 2351
+SPU lhu, COM0 8: 2450
+SPU lhu, COM0 9: 2549
+SPU lhu, COM0 10: 2648
+SPU lhu, COM0 11: 2747
+SPU lhu, COM0 12: 2846
+SPU lhu, COM0 13: 2945
+SPU lhu, COM0 14: 3047
+SPU lhu, COM0 15: 3143
+SPU lw, COM0 0: 3844
+SPU lw, COM0 1: 3841
+SPU lw, COM0 2: 3941
+SPU lw, COM0 3: 4041
+SPU lw, COM0 4: 4141
+SPU lw, COM0 5: 4245
+SPU lw, COM0 6: 4341
+SPU lw, COM0 7: 4540
+SPU lw, COM0 8: 4739
+SPU lw, COM0 9: 4942
+SPU lw, COM0 10: 5137
+SPU lw, COM0 11: 5336
+SPU lw, COM0 12: 5535
+SPU lw, COM0 13: 5734
+SPU lw, COM0 14: 5936
+SPU lw, COM0 15: 6132
+BIOS+bit8 lbu, COM0 0: 1144
+BIOS+bit8 lbu, COM0 1: 1141
+BIOS+bit8 lbu, COM0 2: 1146
+BIOS+bit8 lbu, COM0 3: 1141
+BIOS+bit8 lbu, COM0 4: 1161
+BIOS+bit8 lbu, COM0 5: 1141
+BIOS+bit8 lbu, COM0 6: 1240
+BIOS+bit8 lbu, COM0 7: 1339
+BIOS+bit8 lbu, COM0 8: 1438
+BIOS+bit8 lbu, COM0 9: 1537
+BIOS+bit8 lbu, COM0 10: 1636
+BIOS+bit8 lbu, COM0 11: 1735
+BIOS+bit8 lbu, COM0 12: 1834
+BIOS+bit8 lbu, COM0 13: 1933
+BIOS+bit8 lbu, COM0 14: 2032
+BIOS+bit8 lbu, COM0 15: 2131
+BIOS+bit8 lw, COM0 0: 2941
+BIOS+bit8 lw, COM0 1: 3241
+BIOS+bit8 lw, COM0 2: 3541
+BIOS+bit8 lw, COM0 3: 3841
+BIOS+bit8 lw, COM0 4: 4145
+BIOS+bit8 lw, COM0 5: 4441
+BIOS+bit8 lw, COM0 6: 4840
+BIOS+bit8 lw, COM0 7: 5239
+BIOS+bit8 lw, COM0 8: 5638
+BIOS+bit8 lw, COM0 9: 6037
+BIOS+bit8 lw, COM0 10: 6436
+BIOS+bit8 lw, COM0 11: 6835
+BIOS+bit8 lw, COM0 12: 7234
+BIOS+bit8 lw, COM0 13: 7640
+BIOS+bit8 lw, COM0 14: 8032
+BIOS+bit8 lw, COM0 15: 8431
+COM1 with EXP2 (delay 00070777, bit 9 set):
+EXP2 lbu, COM1 0: 1546
+EXP2 lbu, COM1 1: 1546
+EXP2 lbu, COM1 2: 1541
+EXP2 lbu, COM1 3: 1541
+EXP2 lbu, COM1 4: 1541
+EXP2 lbu, COM1 5: 1541
+EXP2 lbu, COM1 6: 1541
+EXP2 lbu, COM1 7: 1541
+EXP2 lbu, COM1 8: 1541
+EXP2 lbu, COM1 9: 1541
+EXP2 lbu, COM1 10: 1541
+EXP2 lbu, COM1 11: 1541
+EXP2 lbu, COM1 12: 1541
+EXP2 lbu, COM1 13: 1541
+EXP2 lbu, COM1 14: 1545
+EXP2 lbu, COM1 15: 1541
+Bits 16-17:
+BIOS lw, COM bits 16-17 = 0: 2955
+SPU lhu, COM bits 16-17 = 0: 2252
+CDROM lbu, COM bits 16-17 = 0: 1236
+EXP2 lbu, COM bits 16-17 = 0: 1536
+BIOS lw, COM bits 16-17 = 1: 2941
+SPU lhu, COM bits 16-17 = 1: 2244
+CDROM lbu, COM bits 16-17 = 1: 1236
+EXP2 lbu, COM bits 16-17 = 1: 1536
+BIOS lw, COM bits 16-17 = 2: 2941
+SPU lhu, COM bits 16-17 = 2: 2244
+CDROM lbu, COM bits 16-17 = 2: 1236
+EXP2 lbu, COM bits 16-17 = 2: 1536
+BIOS lw, COM bits 16-17 = 3: 2941
+SPU lhu, COM bits 16-17 = 3: 2257
+CDROM lbu, COM bits 16-17 = 3: 1239
+EXP2 lbu, COM bits 16-17 = 3: 1536
+Done.
+```
+
+08CMB.txt:
+
+```
+===== 08 CMB COM2 COM3 SWEEP | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+COM2 with BIOS (bit 10 set) and CDROM (bit 10 set here):
+BIOS lbu, COM2 0: 1144
+BIOS lbu, COM2 1: 1141
+BIOS lbu, COM2 2: 1141
+BIOS lbu, COM2 3: 1141
+BIOS lbu, COM2 4: 1141
+BIOS lbu, COM2 5: 1141
+BIOS lbu, COM2 6: 1240
+BIOS lbu, COM2 7: 1339
+BIOS lbu, COM2 8: 1440
+BIOS lbu, COM2 9: 1537
+BIOS lbu, COM2 10: 1636
+BIOS lbu, COM2 11: 1735
+BIOS lbu, COM2 12: 1834
+BIOS lbu, COM2 13: 1937
+BIOS lbu, COM2 14: 2032
+BIOS lbu, COM2 15: 2131
+BIOS lw, COM2 0: 2650
+BIOS lw, COM2 1: 2941
+BIOS lw, COM2 2: 3244
+BIOS lw, COM2 3: 3541
+BIOS lw, COM2 4: 3841
+BIOS lw, COM2 5: 4141
+BIOS lw, COM2 6: 4540
+BIOS lw, COM2 7: 4939
+BIOS lw, COM2 8: 5338
+BIOS lw, COM2 9: 5737
+BIOS lw, COM2 10: 6142
+BIOS lw, COM2 11: 6535
+BIOS lw, COM2 12: 6954
+BIOS lw, COM2 13: 7339
+BIOS lw, COM2 14: 7735
+BIOS lw, COM2 15: 8131
+CDROM+bit10 lbu, COM2 0: 1245
+CDROM+bit10 lbu, COM2 1: 1246
+CDROM+bit10 lbu, COM2 2: 1241
+CDROM+bit10 lbu, COM2 3: 1241
+CDROM+bit10 lbu, COM2 4: 1241
+CDROM+bit10 lbu, COM2 5: 1246
+CDROM+bit10 lbu, COM2 6: 1340
+CDROM+bit10 lbu, COM2 7: 1439
+CDROM+bit10 lbu, COM2 8: 1538
+CDROM+bit10 lbu, COM2 9: 1637
+CDROM+bit10 lbu, COM2 10: 1736
+CDROM+bit10 lbu, COM2 11: 1835
+CDROM+bit10 lbu, COM2 12: 1934
+CDROM+bit10 lbu, COM2 13: 2033
+CDROM+bit10 lbu, COM2 14: 2132
+CDROM+bit10 lbu, COM2 15: 2231
+COM3 with CDROM (bit 11 set) and BIOS (bit 11 set here):
+CDROM lbu, COM3 0: 1241
+CDROM lbu, COM3 1: 1241
+CDROM lbu, COM3 2: 1241
+CDROM lbu, COM3 3: 1241
+CDROM lbu, COM3 4: 1241
+CDROM lbu, COM3 5: 1341
+CDROM lbu, COM3 6: 1441
+CDROM lbu, COM3 7: 1541
+CDROM lbu, COM3 8: 1641
+CDROM lbu, COM3 9: 1741
+CDROM lbu, COM3 10: 1841
+CDROM lbu, COM3 11: 1941
+CDROM lbu, COM3 12: 2041
+CDROM lbu, COM3 13: 2141
+CDROM lbu, COM3 14: 2244
+CDROM lbu, COM3 15: 2341
+CDROM lw, COM3 0: 3046
+CDROM lw, COM3 1: 3041
+CDROM lw, COM3 2: 3041
+CDROM lw, COM3 3: 3041
+CDROM lw, COM3 4: 3041
+CDROM lw, COM3 5: 3441
+CDROM lw, COM3 6: 3841
+CDROM lw, COM3 7: 4241
+CDROM lw, COM3 8: 4641
+CDROM lw, COM3 9: 5041
+CDROM lw, COM3 10: 5441
+CDROM lw, COM3 11: 5841
+CDROM lw, COM3 12: 6241
+CDROM lw, COM3 13: 6645
+CDROM lw, COM3 14: 7041
+CDROM lw, COM3 15: 7441
+BIOS+bit11 lbu, COM3 0: 1141
+BIOS+bit11 lbu, COM3 1: 1141
+BIOS+bit11 lbu, COM3 2: 1141
+BIOS+bit11 lbu, COM3 3: 1141
+BIOS+bit11 lbu, COM3 4: 1241
+BIOS+bit11 lbu, COM3 5: 1341
+BIOS+bit11 lbu, COM3 6: 1441
+BIOS+bit11 lbu, COM3 7: 1541
+BIOS+bit11 lbu, COM3 8: 1641
+BIOS+bit11 lbu, COM3 9: 1741
+BIOS+bit11 lbu, COM3 10: 1841
+BIOS+bit11 lbu, COM3 11: 1941
+BIOS+bit11 lbu, COM3 12: 2041
+BIOS+bit11 lbu, COM3 13: 2141
+BIOS+bit11 lbu, COM3 14: 2244
+BIOS+bit11 lbu, COM3 15: 2341
+Done.
+```
+
+09WRT.txt:
+
+```
+===== 09 WRT WRITE TIMING | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Stores by write delay; SPU word 00000000, CD index 1:
+SPU sh, as set: 828
+CDROM sb, as set: 651
+POST sb, as set: 1600
+SPU sh, write delay 0: 730
+SPU sh, write delay 1: 828
+SPU sh, write delay 2: 926
+SPU sh, write delay 3: 1024
+SPU sh, write delay 4: 1123
+SPU sh, write delay 5: 1201
+SPU sh, write delay 6: 1305
+SPU sh, write delay 7: 1402
+SPU sh, write delay 8: 1499
+SPU sh, write delay 9: 1596
+SPU sh, write delay 10: 1698
+SPU sh, write delay 11: 1790
+SPU sh, write delay 12: 1887
+SPU sh, write delay 13: 1984
+SPU sh, write delay 14: 2086
+SPU sh, write delay 15: 2178
+SPU sw, write delay 0: 1323
+SPU sw, write delay 1: 1512
+SPU sw, write delay 2: 1708
+SPU sw, write delay 3: 1904
+SPU sw, write delay 4: 2100
+SPU sw, write delay 5: 2296
+SPU sw, write delay 6: 2492
+SPU sw, write delay 7: 2688
+SPU sw, write delay 8: 2884
+SPU sw, write delay 9: 3080
+SPU sw, write delay 10: 3276
+SPU sw, write delay 11: 3472
+SPU sw, write delay 12: 3668
+SPU sw, write delay 13: 3864
+SPU sw, write delay 14: 4060
+SPU sw, write delay 15: 4256
+CDROM sb, write delay 0: 455
+CDROM sb, write delay 1: 461
+CDROM sb, write delay 2: 549
+CDROM sb, write delay 3: 646
+CDROM sb, write delay 4: 743
+CDROM sb, write delay 5: 840
+CDROM sb, write delay 6: 937
+CDROM sb, write delay 7: 1035
+CDROM sb, write delay 8: 1133
+CDROM sb, write delay 9: 1212
+CDROM sb, write delay 10: 1316
+CDROM sb, write delay 11: 1413
+CDROM sb, write delay 12: 1511
+CDROM sb, write delay 13: 1609
+CDROM sb, write delay 14: 1707
+CDROM sb, write delay 15: 1805
+POST sb, write delay 0: 933
+POST sb, write delay 1: 1031
+POST sb, write delay 2: 1134
+POST sb, write delay 3: 1208
+POST sb, write delay 4: 1312
+POST sb, write delay 5: 1409
+POST sb, write delay 6: 1507
+POST sb, write delay 7: 1605
+POST sb, write delay 8: 1703
+POST sb, write delay 9: 1801
+POST sb, write delay 10: 1899
+POST sb, write delay 11: 1997
+POST sb, write delay 12: 2095
+POST sb, write delay 13: 2193
+POST sb, write delay 14: 2296
+POST sb, write delay 15: 2389
+POST sb, COM1 0: 1409
+POST sb, COM1 1: 1507
+POST sb, COM1 2: 1605
+POST sb, COM1 3: 1703
+POST sb, COM1 4: 1801
+POST sb, COM1 5: 1899
+POST sb, COM1 6: 1997
+POST sb, COM1 7: 2095
+POST sb, COM1 8: 2193
+POST sb, COM1 9: 2293
+POST sb, COM1 10: 2389
+POST sb, COM1 11: 2487
+POST sb, COM1 12: 2585
+POST sb, COM1 13: 2683
+POST sb, COM1 14: 2781
+POST sb, COM1 15: 2879
+SPU sh, bit 9 (hold) set: 1024
+CDROM sb, bit 9 (hold) set: 837
+POST sb, bit 9 (hold) cleared: 1404
+SPU word after: 00000000; CD index after: 1
+SPU word put back: 00000000; CD index: 1
+Done.
+```
+
+10SCR.txt:
+
+```
+===== 10 SCR SCRATCHPAD | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Scratchpad and RAM loads and stores (100 each):
+no load: 353
+scratchpad KUSEG lw: 447
+scratchpad KUSEG lhu: 454
+scratchpad KUSEG lbu: 442
+scratchpad KUSEG lw, use: 552
+scratchpad KUSEG sw: 454
+scratchpad KUSEG sh: 457
+scratchpad KUSEG sb: 468
+scratchpad KSEG0 lw: 442
+scratchpad KSEG0 lw, use: 548
+scratchpad KSEG0 sw: 454
+scratchpad last word lw: 442
+RAM KSEG0 lw: 959
+RAM KSEG0 lw, use: 959
+RAM KSEG0 sw: 462
+RAM KSEG1 lw: 954
+Code from KSEG1 (uncached):
+uncached, no load: 1904
+uncached, scratchpad lw: 2514
+uncached, scratchpad sw: 2514
+uncached, RAM lw: 2930
+scratchpad 1F800100 5C4A0100, 9F800100 5C4A0100, 1F8003FC 5C4A03FC, 9F8003FC 5C4A03FC
+Done.
+```
+
+11PWR.txt:
+
+```
+===== 11 PWR NARROW WRITES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Narrow stores, EXP3 delay 00003022, COM_DELAY 00031125, BCC 0001E988:
+EXP3 delay sh +0: rt 05003022, read 05003022, put back 00003022
+EXP3 delay sb +0: rt 05003022, read 05003022, put back 00003022
+EXP3 delay sh +2: rt 00003022, read 20020000, put back 00003022
+EXP3 delay sb +1: rt 00003022, read 00102200, put back 00003022
+EXP3 delay sb +2: rt 00003022, read 20020000, put back 00003022
+EXP3 delay sb +3: rt 00003022, read 22000000, put back 00003022
+COM_DELAY sh +0: rt FFFF1125, read 00031125, put back 00031125
+COM_DELAY sb +1: rt 00031125, read 00012500, put back 00031125
+RAM_SIZE sh +0: rt ABCD0B88, read ABCD0B88, put back 00000B88
+BCC sh +0: rt 0005E988, read 0005E988, put back 0001E988
+BCC sb +0: rt 0005E988, read 0005E988, put back 0001E988
+BCC sh +2: rt 0005E988, read 0001E988, put back 0001E988
+BCC sb +1: rt 0005E988, read 0001E988, put back 0001E988
+Done.
+```
+
+12WIN.txt:
+
+```
+===== 12 WIN WINDOW SIZE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Window sizes and bit 28:
+EXP3 lbu 1FA00000, size 0: none, reg 000000FF, register after 00003022
+EXP3 lbu 1FA00001, size 0: exception 7, reg 5A5A5A5A, register after 00003022
+EXP3 lbu 1FA00002, size 0: exception 7, reg 5A5A5A5A, register after 00003022
+EXP3 lhu 1FA00002, size 0: exception 7, reg 5A5A5A5A, register after 00003022
+EXP3 delay bit 28 written 1: wrote 10003022, read 00003022, put back 00003022, read 00003022
+EXP3 lbu 1FA00001, size 1: none, reg 000000FF, register after 00013022
+EXP3 lbu 1FA00002, size 1: exception 7, reg 5A5A5A5A, register after 00013022
+EXP3 lbu 1FBFFFFF, size 15h: none, reg 000000FF, register after 00153022
+EXP2 lbu 1F80207F, size 7: none, reg 000000FF, register after 00070777
+EXP2 lbu 1F802080, size 7: exception 7, reg 5A5A5A5A, register after 00070777
+EXP2 lbu 1F802080, size 0Dh: none, reg 000000FF, register after 000D0777
+EXP2 lbu 1F803FFF, size 0Dh: none, reg 000000FF, register after 000D0777
+EXP2 lbu 1F802001, size 0: exception 7, reg 5A5A5A5A, register after 00000777
+EXP1 lbu 1F07FFFF, size 13h: none, reg 000000FF, register after 0013243F
+EXP1 lbu 1F080000, size 13h: exception 7, reg 5A5A5A5A, register after 0013243F
+EXP1 lbu 1F080000, size 14h: none, reg 000000FF, register after 0014243F
+EXP1 lbu 1F000001, size 0: exception 7, reg 5A5A5A5A, register after 0000243F
+SPU lhu 1F801C02, size 0: none, reg 00000000, register after 200031E1
+SPU lhu 1F801D80, size 0: none, reg 00000000, register after 200031E1
+CDROM lbu 1F801803, size 0: none, reg 000000E0, register after 00000843
+BIOS lw BFC80100, size 13h: none, reg 00000001, register after 0013243F
+BIOS lw BFC80100, size 14h: none, reg 19951204, register after 0014243F
+BIOS lw BFF80100, size 16h: none, reg 19951204, register after 0016243F
+BIOS lw BFE00100, size 16h: none, reg 19951204, register after 0016243F
+After: EXP1 0013243F EXP2 00070777 EXP3 00003022 BIOS 0013243F SPU 200931E1 CDROM 00020843
+KSEG2 lw FFFE0000: none, reg 00000000, register after 0001E988
+KSEG2 lw FFFE0100: none, reg 00000000, register after 0001E988
+KSEG2 lw FFFE0134: none, reg 00000000, register after 0001E988
+KSEG2 lw FFFE013C: none, reg 00000000, register after 0001E988
+KSEG2 lw FFFE0140: none, reg 00000001, register after 0001E988
+Done.
+```
+
+13RSX.txt:
+
+```
+===== 13 RSX RESERVED BITS LIVE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Reserved bits of the registers in use:
+EXP1 delay bit 28: wrote 1013243F, read 0013243F, put back 0013243F, read 0013243F
+EXP1 delay bit 30: wrote 4013243F, read 0013243F, put back 0013243F, read 0013243F
+EXP1 delay bit 31: wrote 8013243F, read 8013243F, put back 0013243F, read 0013243F
+EXP3 delay bit 28: wrote 10003022, read 00003022, put back 00003022, read 00003022
+EXP3 delay bit 30: wrote 40003022, read 00003022, put back 00003022, read 00003022
+EXP3 delay bit 31: wrote 80003022, read 00003022, put back 00003022, read 00003022
+EXP2 delay bits 14-15: wrote 0007C777, read 0007C777, put back 00070777, read 00070777
+EXP2 delay bits 21-23: wrote 00E70777, read 00070777, put back 00070777, read 00070777
+EXP2 delay bits 24-27: wrote 0F070777, read 0F070777, put back 00070777, read 00070777
+EXP2 delay bit 29 flipped: wrote 20070777, read 20070777, put back 00070777, read 00070777
+EXP2 delay bit 28: wrote 10070777, read 00070777, put back 00070777, read 00070777
+EXP2 delay bit 30: wrote 40070777, read 00070777, put back 00070777, read 00070777
+EXP2 delay bit 31: wrote 80070777, read 00070777, put back 00070777, read 00070777
+CDROM delay bits 14-15: wrote 0002C843, read 0002C843, put back 00020843, read 00020843
+CDROM delay bits 21-23: wrote 00E20843, read 00020843, put back 00020843, read 00020843
+CDROM delay bits 24-27: wrote 0F020843, read 0F020843, put back 00020843, read 00020843
+CDROM delay bit 29 flipped: wrote 20020843, read 20020843, put back 00020843, read 00020843
+CDROM delay bit 28: wrote 10020843, read 00020843, put back 00020843, read 00020843
+CDROM delay bit 30: wrote 40020843, read 00020843, put back 00020843, read 00020843
+CDROM delay bit 31: wrote 80020843, read 00020843, put back 00020843, read 00020843
+SPU delay bits 14-15: wrote 2009F1E1, read 2009F1E1, put back 200931E1, read 200931E1
+SPU delay bits 21-23: wrote 20E931E1, read 200931E1, put back 200931E1, read 200931E1
+SPU delay bits 24-27: wrote 2F0931E1, read 2F0931E1, put back 200931E1, read 200931E1
+SPU delay bit 29 flipped: wrote 000931E1, read 000931E1, put back 200931E1, read 200931E1
+SPU delay bit 28: wrote 300931E1, read 200931E1, put back 200931E1, read 200931E1
+SPU delay bit 30: wrote 600931E1, read 200931E1, put back 200931E1, read 200931E1
+SPU delay bit 31: wrote A00931E1, read 200931E1, put back 200931E1, read 200931E1
+BIOS delay bits 14-15: wrote 0013E43F, read 0013E43F, put back 0013243F, read 0013243F
+BIOS delay bits 21-23: wrote 00F3243F, read 0013243F, put back 0013243F, read 0013243F
+BIOS delay bits 24-27: wrote 0F13243F, read 0F13243F, put back 0013243F, read 0013243F
+BIOS delay bit 29 flipped: wrote 2013243F, read 2013243F, put back 0013243F, read 0013243F
+BIOS delay bit 28: wrote 1013243F, read 0013243F, put back 0013243F, read 0013243F
+BIOS delay bit 30: wrote 4013243F, read 0013243F, put back 0013243F, read 0013243F
+BIOS delay bit 31: wrote 8013243F, read 0013243F, put back 0013243F, read 0013243F
+EXP1 base FF000000: wrote FF000000, read 1F000000, put back 1F000000, read 1F000000
+EXP1 base 00000000: wrote 00000000, read 1F000000, put back 1F000000, read 1F000000
+Done.
+```
+
+14BCC.txt:
+
+```
+===== 14 BCC CACHE CONTROL | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 00000480
+
+Cache control 0001E988, read back:
+BCC bits 18-31: wrote FFFDE988, read FFFDE988, put back 0001E988, read 0001E988
+BCC bit 6: wrote 0001E9C8, read 0001E988, put back 0001E988, read 0001E988
+BCC bit 17: wrote 0003E988, read 0003E988, put back 0001E988, read 0001E988
+BCC bit 12: wrote 0001F988, read 0001F988, put back 0001E988, read 0001E988
+BCC bit 10 (IS0): wrote 0001ED88, read 0001E988, put back 0001E988, read 0001E988
+Loads by BCC bit (100 each):
+RAM lw, as set: 954
+scratchpad lw, as set: 442
+RAM lw use, as set: 960
+RAM lw, bit 16 LDSCH (0000E988): 1063
+scratchpad lw, bit 16 LDSCH: 442
+RAM lw use, bit 16 LDSCH: 1164
+RAM lw, bit 14 NOPAD (0001A988): 968
+scratchpad lw, bit 14 NOPAD: 453
+RAM lw use, bit 14 NOPAD: 964
+RAM lw, bit 13 RDPRI (0001C988): 964
+scratchpad lw, bit 13 RDPRI: 442
+RAM lw use, bit 13 RDPRI: 962
+RAM lw, bit 15 BGNT (00016988): 955
+scratchpad lw, bit 15 BGNT: 447
+RAM lw use, bit 15 BGNT: 961
+RAM lw, bit 12 INTP (0001F988): 955
+scratchpad lw, bit 12 INTP: 447
+RAM lw use, bit 12 INTP: 961
+RAM lw, bit 17 NOSTR (0003E988): 984
+scratchpad lw, bit 17 NOSTR: 459
+RAM lw use, bit 17 NOSTR: 963
+RAM lw, DBLKSZ 1 (0001E998): 959
+scratchpad lw, DBLKSZ 1: 442
+RAM lw use, DBLKSZ 1: 957
+RAM lw, DBLKSZ 2 (0001E9A8): 958
+scratchpad lw, DBLKSZ 2: 442
+RAM lw use, DBLKSZ 2: 961
+RAM lw, DBLKSZ 3 (0001E9B8): 958
+scratchpad lw, DBLKSZ 3: 442
+RAM lw use, DBLKSZ 3: 961
+D-cache mode (bit 3 cleared, bit 7 set), one access; slot = (address >> 2) & FFh:
+KSEG0 lw: loaded 0DA7A000, scratchpad 1F8003E8 now 0DA7A000, RAM word 0DA7A000, BCC 0001E988
+KSEG0 lbu +1: loaded 000000A0, scratchpad 1F8003E8 now 0DA7A000, RAM word 0DA7A000, BCC 0001E988
+KSEG1 lw: loaded 0DA7A000, scratchpad 1F8003E8 now DEAD03E8, RAM word 0DA7A000, BCC 0001E988
+KSEG0 sw: loaded 00000000, scratchpad 1F8003E8 now DEAD03E8, RAM word 5EED0000, BCC 0001E988
+Done.
+```
+
+### 27 September 2026 card-d
+
+Raw output: [00RUN.txt](/tests/raw/20260927T0000Z-5501a-card-d/memctl_end/00RUN.txt) · [01EN4.txt](/tests/raw/20260927T0000Z-5501a-card-d/memctl_end/01EN4.txt)
+
+00RUN.txt:
+
+```
+===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+1 tests
+A chain program, linked at 80010000
+Saved on the card in slot 2, from image 1
+COP0 at start: BPC 00000000 BDA 80024F50 TAR BFC02BAC DCIC 00000000 BadVaddr 800154CE BDAM FFFFFFFF
+BPCM 00000000 SR 40000000 Cause 00000020 EPC 80111DF8 PRId 00000002
+```
+
+01EN4.txt:
+
+```
+===== 01 EN4 HANG RISK 4 | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 800154CE
+
+The step that may hang the console, after the one that did:
+sw BF800100: exception no 0, scratchpad 1F800100 now 5C4A0001
+Done.
+```
+
+### 28 September 2026 card-h memctl_end
+
+Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_end/00RUN.txt) · [01EN4.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_end/01EN4.txt)
+
+00RUN.txt:
+
+```
+===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+1 tests
+A chain program, linked at 80010000
+Saved on the card in slot 2, from image 1
+COP0 at start: BPC 00000000 BDA 80024F50 TAR BFC02BAC DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
+BPCM 00000000 SR 70000000 Cause 00000020 EPC 80111BC0 PRId 00000002
+```
+
+01EN4.txt:
+
+```
+===== 01 EN4 HANG RISK 4 | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 1F801DAA
+
+The step that may hang the console, after the one that did:
+sw BF800100: exception no 0, scratchpad 1F800100 now 5C4A0001
+Done.
+```
+
+### 28 September 2026 card-h memctl_end1
+
+Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_end1/00RUN.txt) · [01END.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_end1/01END.txt)
+
+00RUN.txt:
+
+```
+===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+1 tests
+A chain program, linked at 80100000
+Saved on the card in slot 2, from image 1
+COP0 at start: BPC 00000000 BDA 80024F50 TAR BFC02BAC DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
+BPCM 00000000 SR 70000000 Cause 00000020 EPC 80021BC4 PRId 00000002
+```
+
+01END.txt:
+
+```
+===== 01 END HANG RISKS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 1F801DAA
+
+The steps that may hang the console:
+EXP3 delay bit 31 set, lbu 1FA00000: FF, delay put back 00003022
+Step 2, RAM_SIZE 0288: not run in this table.
+Step 3, BCC bit 7 cleared: not run in this table.
+Step 4, sw BF800100: not run in this table.
+Done.
+```
+
+### 28 September 2026 card-h memctl_end2
+
+Raw output: [00RUN.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_end2/00RUN.txt) · [01END.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_end2/01END.txt)
+
+00RUN.txt:
+
+```
+===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+1 tests
+A chain program, linked at 80010000
+Saved on the card in slot 2, from image 1
+COP0 at start: BPC 00000000 BDA 80024F50 TAR 8010D58C DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
+BPCM 00000000 SR 70000000 Cause 00000020 EPC 8010E0F8 PRId 00000002
+```
+
+01END.txt:
+
+```
+===== 01 END HANG RISKS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
+BadVaddr as the group starts: 1F801DAA
+
+The steps that may hang the console:
+Step 1, EXP3 delay bit 31: not run in this table.
+RAM_SIZE 0288, lw A002138C and +2MB: 4D42C0DE 4D42C0DE
+Step 3, BCC bit 7 cleared: not run in this table.
+Step 4, sw BF800100: not run in this table.
+Done.
+```
+
+## References
+
+[^run]: SCPH-5501 output: [memctl_safe/03BRT.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/03BRT.txt).
+[^h-rdb]: Run 20260928T0000Z-5501a-card-h: [memctl_safe/01RDB.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/01RDB.txt).
+[^h-rsv]: Run 20260928T0000Z-5501a-card-h: [memctl_safe/02RSV.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/02RSV.txt).
+[^h-rsx]: Run 20260928T0000Z-5501a-card-h: [memctl_safe/13RSX.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/13RSX.txt).
+[^h-bcc]: Run 20260928T0000Z-5501a-card-h: [memctl_safe/14BCC.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/14BCC.txt).
+[^h-brt]: Run 20260928T0000Z-5501a-card-h: [memctl_safe/03BRT.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/03BRT.txt).
+[^h-srt]: Run 20260928T0000Z-5501a-card-h: [memctl_safe/04SRT.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/04SRT.txt).
+[^h-crt]: Run 20260928T0000Z-5501a-card-h: [memctl_safe/05CRT.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/05CRT.txt).
+[^h-xrt]: Run 20260928T0000Z-5501a-card-h: [memctl_safe/06XRT.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/06XRT.txt).
+[^h-cma]: Run 20260928T0000Z-5501a-card-h: [memctl_safe/07CMA.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/07CMA.txt).
+[^h-cmb]: Run 20260928T0000Z-5501a-card-h: [memctl_safe/08CMB.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/08CMB.txt).
+[^h-wrt]: Run 20260928T0000Z-5501a-card-h: [memctl_safe/09WRT.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/09WRT.txt).
+[^h-scr]: Run 20260928T0000Z-5501a-card-h: [memctl_safe/10SCR.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/10SCR.txt).
+[^h-pwr]: Run 20260928T0000Z-5501a-card-h: [memctl_safe/11PWR.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/11PWR.txt).
+[^h-win]: Run 20260928T0000Z-5501a-card-h: [memctl_safe/12WIN.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_safe/12WIN.txt).
+[^g-ram]: Run 20260927T0000Z-5501a-card-g: [memctl_safe/14RAM.txt](/tests/raw/20260927T0000Z-5501a-card-g/memctl_safe/14RAM.txt).
+[^h-end]: Run 20260928T0000Z-5501a-card-h: [memctl_end1/01END.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_end1/01END.txt), [memctl_end2/01END.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_end2/01END.txt), [memctl_end/01EN4.txt](/tests/raw/20260928T0000Z-5501a-card-h/memctl_end/01EN4.txt).
+