Memory Control and Bus Timing: Difference between revisions
| Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | Revision as of 05:18, 23 October 2026 RemmyLee (Hardware tests: nine DMA, MDEC and BIOS test pages with part names for titles; join one-sentence paragraphs per voice.md) | ||
| Line 38: | Line 38: | ||
| ### Reserved Bits | ### Reserved Bits | ||
| − | In each delay/size register, bits 14 and 15, bits 24 to 27 and bit 29 keep the value written. Bits 21 to 23, 28 and 30 read 0. Bit 31 kept its value only in the EXP1 register. The EXP1 and EXP2 base registers keep their low bits.[^h-rsv][^h-rsx] | + | In each delay/size register, bits 14 and 15, bits 24 to 27 and bit 29 keep the value written. Bits 21 to 23, 28 and 30 read 0. Bit 31 kept its value only in the EXP1 register. The EXP1 and EXP2 base registers keep their low bits.[^h-rsv][^h-rsx] Cache control keeps bits 12, 17 and 18 to 31, and bits 6 and 10 read 0.[^h-bcc] |
| − | Cache control keeps bits 12, 17 and 18 to 31, and bits 6 and 10 read 0.[^h-bcc] | ||
| − | |||
| ### Read Delay | ### Read Delay | ||