Memory Control and Bus Timing: Difference between revisions
| Revision as of 05:40, 23 October 2026 RemmyLee (Hardware tests: 15 more test pages (CPU, DMA, SPU, GPU, MDEC, CD-ROM, bus), each with See also links to the pages that measure the same parts) | Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | ||
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| A timing row is the number of system clock cycles for 100 turns of a loop around one instruction. A row with no load gives the cost of the loop. The groups that write undocumented bits save the card before each risky step, and the steps that may hang the console run last as separate images (memctl_end, memctl_end1 and memctl_end2).[^run] | A timing row is the number of system clock cycles for 100 turns of a loop around one instruction. A row with no load gives the cost of the loop. The groups that write undocumented bits save the card before each risky step, and the steps that may hang the console run last as separate images (memctl_end, memctl_end1 and memctl_end2).[^run] | ||
| + | See also: | ||
| + | |||
| + | - [CPU Stores and Device Delays](/tests/cpu-stores-device-delays/) | ||
| + | - [Peripheral Registers and Bus Delays](/tests/peripheral-bus-delays/) | ||
| + | - [Bus Access and Device Register Timing](/tests/bus-access-register-timing/) | ||
| + | |||
| ## Results | ## Results | ||