Memory Control and Bus Timing: Difference between revisions
| Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | ||
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| A timing row is the number of system clock cycles for 100 turns of a loop around one instruction. A row with no load gives the cost of the loop. The groups that write undocumented bits save the card before each risky step, and the steps that may hang the console run last as separate images (memctl_end, memctl_end1 and memctl_end2).[^run] | A timing row is the number of system clock cycles for 100 turns of a loop around one instruction. A row with no load gives the cost of the loop. The groups that write undocumented bits save the card before each risky step, and the steps that may hang the console run last as separate images (memctl_end, memctl_end1 and memctl_end2).[^run] | ||
| + | See also: | ||
| + | |||
| + | - [CPU Stores and Device Delays](/tests/cpu-stores-device-delays/) | ||
| + | - [Peripheral Registers and Bus Delays](/tests/peripheral-bus-delays/) | ||
| + | - [Bus Access and Device Register Timing](/tests/bus-access-register-timing/) | ||
| + | |||
| ## Results | ## Results | ||
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| ### Reserved Bits | ### Reserved Bits | ||
| − | In each delay/size register, bits 14 and 15, bits 24 to 27 and bit 29 keep the value written. Bits 21 to 23, 28 and 30 read 0. Bit 31 kept its value only in the EXP1 register. The EXP1 and EXP2 base registers keep their low bits.[^h-rsv][^h-rsx] | + | In each delay/size register, bits 14 and 15, bits 24 to 27 and bit 29 keep the value written. Bits 21 to 23, 28 and 30 read 0. Bit 31 kept its value only in the EXP1 register. The EXP1 and EXP2 base registers keep their low bits.[^h-rsv][^h-rsx] Cache control keeps bits 12, 17 and 18 to 31, and bits 6 and 10 read 0.[^h-bcc] |
| − | Cache control keeps bits 12, 17 and 18 to 31, and bits 6 and 10 read 0.[^h-bcc] | ||
| − | |||
| ### Read Delay | ### Read Delay | ||