Partial Writes to I/O Registers: Difference between revisions
| Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | Revision as of 05:49, 23 October 2026 RemmyLee (Hardware tests: the last 15 test pages (timers, SPU, CPU, GPU, DMA, CD-ROM, GTE), See also links both ways; uncited clock claim removed) | ||
| Line 14: | Line 14: | ||
| The registers are I_MASK (1F801074h) and DPCR (1F8010F0h), which are 32-bit registers inside the main chip, and the SPU's main volume left (1F801D80h) and voice 0 volume left (1F801C00h), which are 16-bit registers on the SPU's bus. For the SPU the program also reads the next register.[^src] | The registers are I_MASK (1F801074h) and DPCR (1F8010F0h), which are 32-bit registers inside the main chip, and the SPU's main volume left (1F801D80h) and voice 0 volume left (1F801C00h), which are 16-bit registers on the SPU's bus. For the SPU the program also reads the next register.[^src] | ||
| + | See also: | ||
| + | |||
| + | - [I/O Load and Store Spacing](/tests/io-load-store-spacing/) | ||
| + | |||
| ## Results | ## Results | ||