psx.wiki

Partial Writes to I/O Registers: Difference between revisions

Revision as of 04:31, 23 October 2026
RemmyLee
(Hardware tests: test page type, raw console output served from truth/, first test page)		Revision as of 05:11, 23 October 2026
RemmyLee
(Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published)
Line 1:Line 1:
+---
+title: Partial Writes to I/O Registers
+type: test
+summary: Measures what byte, halfword and unaligned stores do to 32-bit on-chip registers and to 16-bit SPU registers.
+category: Hardware tests
+info: Machine = SCPH-5501
+info: Program = regwrites (pcsx-redux nugget)
+---
+
+## Overview
+
+The program writes a base value to a register with a store of the register's own width, then runs one test store and reads the register back. The test stores are SW, SB and SH at each aligned offset, SWL and SWR at all four offsets, and SH at the misaligned offsets 1 and 3. The source values are AABBCCDDh and FEDCBA98h, and the base values are 0, FFFFFFFFh and 11223344h.[^src]
+
+The registers are I_MASK (1F801074h) and DPCR (1F8010F0h), which are 32-bit registers inside the main chip, and the SPU's main volume left (1F801D80h) and voice 0 volume left (1F801C00h), which are 16-bit registers on the SPU's bus. For the SPU the program also reads the next register.[^src]
+
+## Results
+
+### 32-bit On-chip Registers
+
+A byte or halfword store to DPCR writes all 32 bits. The register receives the source register shifted into the byte lane of the store, with zeros below it, whatever the base value was. With source AABBCCDDh, SB at offset 1 left DPCR at BBCCDD00h, SB at offset 3 left DD000000h and SH at offset 2 left CCDD0000h.[^run]
+
+I_MASK behaves the same way within its own bits. Its upper half reads back as BF80h regardless of what was written.[^run]
+
+SWL and SWR also write the whole register. SWL at offset 0 left DPCR at 000000AAh and SWR at offset 1 left BBCCDD00h.[^run]
+
+### 16-bit SPU Registers
+
+A byte store at offset 0 of an SPU register writes the whole halfword: SB of AABBCCDDh left the register at CCDDh. A byte store at offset 1 changes neither register. A byte store at offset 2 writes CCDDh into the next register.[^run]
+
+### Misaligned Halfword Stores
+
+SH at offset 1 or 3 of any register raises an address error on store (Cause 10000014h). BadVaddr then holds the odd address.[^run]
+
+## Runs
+
+### 22 October 2026 (link-4)
+
+[REGWRITES.txt](/tests/raw/20261022T2245Z-5501a-link-4/regwrites/REGWRITES.txt):
+
+```
+=== PS1 MMIO Partial-Word Write Masking Probe ===
+Compiled: Oct 22 2026 18:23:50
+Format:
+ <reg> <op> +<off> base=<seed> src=<src> got=<readback> [neigh=<next-reg>]
+ AdES rows: faulting instruction trapped (cause/epc/badvaddr).
+
+--- IMASK @ 0xbf801074 (on-die, 32-bit) ---
+IMASK sw +0 base=0x00000000 src=0xaabbccdd got=0xbf8004dd
+IMASK sb +0 base=0x00000000 src=0xaabbccdd got=0xbf8004dd
+IMASK sb +1 base=0x00000000 src=0xaabbccdd got=0xbf800500
+IMASK sb +2 base=0x00000000 src=0xaabbccdd got=0xbf800000
+IMASK sb +3 base=0x00000000 src=0xaabbccdd got=0xbf800000
+IMASK sh +0 base=0x00000000 src=0xaabbccdd got=0xbf8004dd
+IMASK sh +2 base=0x00000000 src=0xaabbccdd got=0xbf800000
+IMASK sh +1 base=0x00000000 src=0xaabbccdd AdES cause=0x10000014 epc=0x80010ab4 badvaddr=0xbf801075
+IMASK sh +3 base=0x00000000 src=0xaabbccdd AdES cause=0x10000014 epc=0x80010ab4 badvaddr=0xbf801077
+IMASK swl +0 base=0x00000000 src=0xaabbccdd got=0xbf8000aa
+IMASK swl +1 base=0x00000000 src=0xaabbccdd got=0xbf8002bb
+IMASK swl +2 base=0x00000000 src=0xaabbccdd got=0xbf8003cc
+IMASK swl +3 base=0x00000000 src=0xaabbccdd got=0xbf8004dd
+IMASK swr +0 base=0x00000000 src=0xaabbccdd got=0xbf8004dd
+IMASK swr +1 base=0x00000000 src=0xaabbccdd got=0xbf800500
+IMASK swr +2 base=0x00000000 src=0xaabbccdd got=0xbf800000
+IMASK swr +3 base=0x00000000 src=0xaabbccdd got=0xbf800000
+IMASK sw +0 base=0x00000000 src=0xfedcba98 got=0xbf800298
+IMASK sb +0 base=0x00000000 src=0xfedcba98 got=0xbf800298
+IMASK sb +1 base=0x00000000 src=0xfedcba98 got=0xbf800000
+IMASK sb +2 base=0x00000000 src=0xfedcba98 got=0xbf800000
+IMASK sb +3 base=0x00000000 src=0xfedcba98 got=0xbf800000
+IMASK sh +0 base=0x00000000 src=0xfedcba98 got=0xbf800298
+IMASK sh +2 base=0x00000000 src=0xfedcba98 got=0xbf800000
+IMASK sh +1 base=0x00000000 src=0xfedcba98 AdES cause=0x10000014 epc=0x80010ab4 badvaddr=0xbf801075
+IMASK sh +3 base=0x00000000 src=0xfedcba98 AdES cause=0x10000014 epc=0x80010ab4 badvaddr=0xbf801077
+IMASK swl +0 base=0x00000000 src=0xfedcba98 got=0xbf8000fe
+IMASK swl +1 base=0x00000000 src=0xfedcba98 got=0xbf8006dc
+IMASK swl +2 base=0x00000000 src=0xfedcba98 got=0xbf8004ba
+IMASK swl +3 base=0x00000000 src=0xfedcba98 got=0xbf800298
+IMASK swr +0 base=0x00000000 src=0xfedcba98 got=0xbf800298
+IMASK swr +1 base=0x00000000 src=0xfedcba98 got=0xbf800000
+IMASK swr +2 base=0x00000000 src=0xfedcba98 got=0xbf800000
+IMASK swr +3 base=0x00000000 src=0xfedcba98 got=0xbf800000
+IMASK sw +0 base=0xffffffff src=0xaabbccdd got=0xbf8004dd
+IMASK sb +0 base=0xffffffff src=0xaabbccdd got=0xbf8004dd
+IMASK sb +1 base=0xffffffff src=0xaabbccdd got=0xbf800500
+IMASK sb +2 base=0xffffffff src=0xaabbccdd got=0xbf800000
+IMASK sb +3 base=0xffffffff src=0xaabbccdd got=0xbf800000
+IMASK sh +0 base=0xffffffff src=0xaabbccdd got=0xbf8004dd
+IMASK sh +2 base=0xffffffff src=0xaabbccdd got=0xbf800000
+IMASK sh +1 base=0xffffffff src=0xaabbccdd AdES cause=0x10000414 epc=0x80010ab4 badvaddr=0xbf801075
+IMASK sh +3 base=0xffffffff src=0xaabbccdd AdES cause=0x10000414 epc=0x80010ab4 badvaddr=0xbf801077
+IMASK swl +0 base=0xffffffff src=0xaabbccdd got=0xbf8000aa
+IMASK swl +1 base=0xffffffff src=0xaabbccdd got=0xbf8002bb
+IMASK swl +2 base=0xffffffff src=0xaabbccdd got=0xbf8003cc
+IMASK swl +3 base=0xffffffff src=0xaabbccdd got=0xbf8004dd
+IMASK swr +0 base=0xffffffff src=0xaabbccdd got=0xbf8004dd
+IMASK swr +1 base=0xffffffff src=0xaabbccdd got=0xbf800500
+IMASK swr +2 base=0xffffffff src=0xaabbccdd got=0xbf800000
+IMASK swr +3 base=0xffffffff src=0xaabbccdd got=0xbf800000
+IMASK sw +0 base=0xffffffff src=0xfedcba98 got=0xbf800298
+IMASK sb +0 base=0xffffffff src=0xfedcba98 got=0xbf800298
+IMASK sb +1 base=0xffffffff src=0xfedcba98 got=0xbf800000
+IMASK sb +2 base=0xffffffff src=0xfedcba98 got=0xbf800000
+IMASK sb +3 base=0xffffffff src=0xfedcba98 got=0xbf800000
+IMASK sh +0 base=0xffffffff src=0xfedcba98 got=0xbf800298
+IMASK sh +2 base=0xffffffff src=0xfedcba98 got=0xbf800000
+IMASK sh +1 base=0xffffffff src=0xfedcba98 AdES cause=0x10000414 epc=0x80010ab4 badvaddr=0xbf801075
+IMASK sh +3 base=0xffffffff src=0xfedcba98 AdES cause=0x10000414 epc=0x80010ab4 badvaddr=0xbf801077
+IMASK swl +0 base=0xffffffff src=0xfedcba98 got=0xbf8000fe
+IMASK swl +1 base=0xffffffff src=0xfedcba98 got=0xbf8006dc
+IMASK swl +2 base=0xffffffff src=0xfedcba98 got=0xbf8004ba
+IMASK swl +3 base=0xffffffff src=0xfedcba98 got=0xbf800298
+IMASK swr +0 base=0xffffffff src=0xfedcba98 got=0xbf800298
+IMASK swr +1 base=0xffffffff src=0xfedcba98 got=0xbf800000
+IMASK swr +2 base=0xffffffff src=0xfedcba98 got=0xbf800000
+IMASK swr +3 base=0xffffffff src=0xfedcba98 got=0xbf800000
+IMASK sw +0 base=0x11223344 src=0xaabbccdd got=0xbf8004dd
+IMASK sb +0 base=0x11223344 src=0xaabbccdd got=0xbf8004dd
+IMASK sb +1 base=0x11223344 src=0xaabbccdd got=0xbf800500
+IMASK sb +2 base=0x11223344 src=0xaabbccdd got=0xbf800000
+IMASK sb +3 base=0x11223344 src=0xaabbccdd got=0xbf800000
+IMASK sh +0 base=0x11223344 src=0xaabbccdd got=0xbf8004dd
+IMASK sh +2 base=0x11223344 src=0xaabbccdd got=0xbf800000
+IMASK sh +1 base=0x11223344 src=0xaabbccdd AdES cause=0x10000014 epc=0x80010ab4 badvaddr=0xbf801075
+IMASK sh +3 base=0x11223344 src=0xaabbccdd AdES cause=0x10000014 epc=0x80010ab4 badvaddr=0xbf801077
+IMASK swl +0 base=0x11223344 src=0xaabbccdd got=0xbf8000aa
+IMASK swl +1 base=0x11223344 src=0xaabbccdd got=0xbf8002bb
+IMASK swl +2 base=0x11223344 src=0xaabbccdd got=0xbf8003cc
+IMASK swl +3 base=0x11223344 src=0xaabbccdd got=0xbf8004dd
+IMASK swr +0 base=0x11223344 src=0xaabbccdd got=0xbf8004dd
+IMASK swr +1 base=0x11223344 src=0xaabbccdd got=0xbf800500
+IMASK swr +2 base=0x11223344 src=0xaabbccdd got=0xbf800000
+IMASK swr +3 base=0x11223344 src=0xaabbccdd got=0xbf800000
+IMASK sw +0 base=0x11223344 src=0xfedcba98 got=0xbf800298
+IMASK sb +0 base=0x11223344 src=0xfedcba98 got=0xbf800298
+IMASK sb +1 base=0x11223344 src=0xfedcba98 got=0xbf800000
+IMASK sb +2 base=0x11223344 src=0xfedcba98 got=0xbf800000
+IMASK sb +3 base=0x11223344 src=0xfedcba98 got=0xbf800000
+IMASK sh +0 base=0x11223344 src=0xfedcba98 got=0xbf800298
+IMASK sh +2 base=0x11223344 src=0xfedcba98 got=0xbf800000
+IMASK sh +1 base=0x11223344 src=0xfedcba98 AdES cause=0x10000014 epc=0x80010ab4 badvaddr=0xbf801075
+IMASK sh +3 base=0x11223344 src=0xfedcba98 AdES cause=0x10000014 epc=0x80010ab4 badvaddr=0xbf801077
+IMASK swl +0 base=0x11223344 src=0xfedcba98 got=0xbf8000fe
+IMASK swl +1 base=0x11223344 src=0xfedcba98 got=0xbf8006dc
+IMASK swl +2 base=0x11223344 src=0xfedcba98 got=0xbf8004ba
+IMASK swl +3 base=0x11223344 src=0xfedcba98 got=0xbf800298
+IMASK swr +0 base=0x11223344 src=0xfedcba98 got=0xbf800298
+IMASK swr +1 base=0x11223344 src=0xfedcba98 got=0xbf800000
+IMASK swr +2 base=0x11223344 src=0xfedcba98 got=0xbf800000
+IMASK swr +3 base=0x11223344 src=0xfedcba98 got=0xbf800000
+
+--- DPCR @ 0xbf8010f0 (on-die, 32-bit) ---
+DPCR sw +0 base=0x00000000 src=0xaabbccdd got=0xaabbccdd
+DPCR sb +0 base=0x00000000 src=0xaabbccdd got=0xaabbccdd
+DPCR sb +1 base=0x00000000 src=0xaabbccdd got=0xbbccdd00
+DPCR sb +2 base=0x00000000 src=0xaabbccdd got=0xccdd0000
+DPCR sb +3 base=0x00000000 src=0xaabbccdd got=0xdd000000
+DPCR sh +0 base=0x00000000 src=0xaabbccdd got=0xaabbccdd
+DPCR sh +2 base=0x00000000 src=0xaabbccdd got=0xccdd0000
+DPCR sh +1 base=0x00000000 src=0xaabbccdd AdES cause=0x10000014 epc=0x80010ab4 badvaddr=0xbf8010f1
+DPCR sh +3 base=0x00000000 src=0xaabbccdd AdES cause=0x10000014 epc=0x80010ab4 badvaddr=0xbf8010f3
+DPCR swl +0 base=0x00000000 src=0xaabbccdd got=0x000000aa
+DPCR swl +1 base=0x00000000 src=0xaabbccdd got=0x0000aabb
+DPCR swl +2 base=0x00000000 src=0xaabbccdd got=0x00aabbcc
+DPCR swl +3 base=0x00000000 src=0xaabbccdd got=0xaabbccdd
+DPCR swr +0 base=0x00000000 src=0xaabbccdd got=0xaabbccdd
+DPCR swr +1 base=0x00000000 src=0xaabbccdd got=0xbbccdd00
+DPCR swr +2 base=0x00000000 src=0xaabbccdd got=0xccdd0000
+DPCR swr +3 base=0x00000000 src=0xaabbccdd got=0xdd000000
+DPCR sw +0 base=0x00000000 src=0xfedcba98 got=0xfedcba98
+DPCR sb +0 base=0x00000000 src=0xfedcba98 got=0xfedcba98
+DPCR sb +1 base=0x00000000 src=0xfedcba98 got=0xdcba9800
+DPCR sb +2 base=0x00000000 src=0xfedcba98 got=0xba980000
+DPCR sb +3 base=0x00000000 src=0xfedcba98 got=0x98000000
+DPCR sh +0 base=0x00000000 src=0xfedcba98 got=0xfedcba98
+DPCR sh +2 base=0x00000000 src=0xfedcba98 got=0xba980000
+DPCR sh +1 base=0x00000000 src=0xfedcba98 AdES cause=0x10000014 epc=0x80010ab4 badvaddr=0xbf8010f1
+DPCR sh +3 base=0x00000000 src=0xfedcba98 AdES cause=0x10000014 epc=0x80010ab4 badvaddr=0xbf8010f3
+DPCR swl +0 base=0x00000000 src=0xfedcba98 got=0x000000fe
+DPCR swl +1 base=0x00000000 src=0xfedcba98 got=0x0000fedc
+DPCR swl +2 base=0x00000000 src=0xfedcba98 got=0x00fedcba
+DPCR swl +3 base=0x00000000 src=0xfedcba98 got=0xfedcba98
+DPCR swr +0 base=0x00000000 src=0xfedcba98 got=0xfedcba98
+DPCR swr +1 base=0x00000000 src=0xfedcba98 got=0xdcba9800
+DPCR swr +2 base=0x00000000 src=0xfedcba98 got=0xba980000
+DPCR swr +3 base=0x00000000 src=0xfedcba98 got=0x98000000
+DPCR sw +0 base=0xffffffff src=0xaabbccdd got=0xaabbccdd
+DPCR sb +0 base=0xffffffff src=0xaabbccdd got=0xaabbccdd
+DPCR sb +1 base=0xffffffff src=0xaabbccdd got=0xbbccdd00
+DPCR sb +2 base=0xffffffff src=0xaabbccdd got=0xccdd0000
+DPCR sb +3 base=0xffffffff src=0xaabbccdd got=0xdd000000
+DPCR sh +0 base=0xffffffff src=0xaabbccdd got=0xaabbccdd
+DPCR sh +2 base=0xffffffff src=0xaabbccdd got=0xccdd0000
+DPCR sh +1 base=0xffffffff src=0xaabbccdd AdES cause=0x10000014 epc=0x80010ab4 badvaddr=0xbf8010f1
+DPCR sh +3 base=0xffffffff src=0xaabbccdd AdES cause=0x10000014 epc=0x80010ab4 badvaddr=0xbf8010f3
+DPCR swl +0 base=0xffffffff src=0xaabbccdd got=0x000000aa
+DPCR swl +1 base=0xffffffff src=0xaabbccdd got=0x0000aabb
+DPCR swl +2 base=0xffffffff src=0xaabbccdd got=0x00aabbcc
+DPCR swl +3 base=0xffffffff src=0xaabbccdd got=0xaabbccdd
+DPCR swr +0 base=0xffffffff src=0xaabbccdd got=0xaabbccdd
+DPCR swr +1 base=0xffffffff src=0xaabbccdd got=0xbbccdd00
+DPCR swr +2 base=0xffffffff src=0xaabbccdd got=0xccdd0000
+DPCR swr +3 base=0xffffffff src=0xaabbccdd got=0xdd000000
+DPCR sw +0 base=0xffffffff src=0xfedcba98 got=0xfedcba98
+DPCR sb +0 base=0xffffffff src=0xfedcba98 got=0xfedcba98
+DPCR sb +1 base=0xffffffff src=0xfedcba98 got=0xdcba9800
+DPCR sb +2 base=0xffffffff src=0xfedcba98 got=0xba980000
+DPCR sb +3 base=0xffffffff src=0xfedcba98 got=0x98000000
+DPCR sh +0 base=0xffffffff src=0xfedcba98 got=0xfedcba98
+DPCR sh +2 base=0xffffffff src=0xfedcba98 got=0xba980000
+DPCR sh +1 base=0xffffffff src=0xfedcba98 AdES cause=0x10000014 epc=0x80010ab4 badvaddr=0xbf8010f1
+DPCR sh +3 base=0xffffffff src=0xfedcba98 AdES cause=0x10000014 epc=0x80010ab4 badvaddr=0xbf8010f3
+DPCR swl +0 base=0xffffffff src=0xfedcba98 got=0x000000fe
+DPCR swl +1 base=0xffffffff src=0xfedcba98 got=0x0000fedc
+DPCR swl +2 base=0xffffffff src=0xfedcba98 got=0x00fedcba
+DPCR swl +3 base=0xffffffff src=0xfedcba98 got=0xfedcba98
+DPCR swr +0 base=0xffffffff src=0xfedcba98 got=0xfedcba98
+DPCR swr +1 base=0xffffffff src=0xfedcba98 got=0xdcba9800
+DPCR swr +2 base=0xffffffff src=0xfedcba98 got=0xba980000
+DPCR swr +3 base=0xffffffff src=0xfedcba98 got=0x98000000
+DPCR sw +0 base=0x11223344 src=0xaabbccdd got=0xaabbccdd
+DPCR sb +0 base=0x11223344 src=0xaabbccdd got=0xaabbccdd
+DPCR sb +1 base=0x11223344 src=0xaabbccdd got=0xbbccdd00
+DPCR sb +2 base=0x11223344 src=0xaabbccdd got=0xccdd0000
+DPCR sb +3 base=0x11223344 src=0xaabbccdd got=0xdd000000
+DPCR sh +0 base=0x11223344 src=0xaabbccdd got=0xaabbccdd
+DPCR sh +2 base=0x11223344 src=0xaabbccdd got=0xccdd0000
+DPCR sh +1 base=0x11223344 src=0xaabbccdd AdES cause=0x10000014 epc=0x80010ab4 badvaddr=0xbf8010f1
+DPCR sh +3 base=0x11223344 src=0xaabbccdd AdES cause=0x10000014 epc=0x80010ab4 badvaddr=0xbf8010f3
+DPCR swl +0 base=0x11223344 src=0xaabbccdd got=0x000000aa
+DPCR swl +1 base=0x11223344 src=0xaabbccdd got=0x0000aabb
+DPCR swl +2 base=0x11223344 src=0xaabbccdd got=0x00aabbcc
+DPCR swl +3 base=0x11223344 src=0xaabbccdd got=0xaabbccdd
+DPCR swr +0 base=0x11223344 src=0xaabbccdd got=0xaabbccdd
+DPCR swr +1 base=0x11223344 src=0xaabbccdd got=0xbbccdd00
+DPCR swr +2 base=0x11223344 src=0xaabbccdd got=0xccdd0000
+DPCR swr +3 base=0x11223344 src=0xaabbccdd got=0xdd000000
+DPCR sw +0 base=0x11223344 src=0xfedcba98 got=0xfedcba98
+DPCR sb +0 base=0x11223344 src=0xfedcba98 got=0xfedcba98
+DPCR sb +1 base=0x11223344 src=0xfedcba98 got=0xdcba9800
+DPCR sb +2 base=0x11223344 src=0xfedcba98 got=0xba980000
+DPCR sb +3 base=0x11223344 src=0xfedcba98 got=0x98000000
+DPCR sh +0 base=0x11223344 src=0xfedcba98 got=0xfedcba98
+DPCR sh +2 base=0x11223344 src=0xfedcba98 got=0xba980000
+DPCR sh +1 base=0x11223344 src=0xfedcba98 AdES cause=0x10000014 epc=0x80010ab4 badvaddr=0xbf8010f1
+DPCR sh +3 base=0x11223344 src=0xfedcba98 AdES cause=0x10000014 epc=0x80010ab4 badvaddr=0xbf8010f3
+DPCR swl +0 base=0x11223344 src=0xfedcba98 got=0x000000fe
+DPCR swl +1 base=0x11223344 src=0xfedcba98 got=0x0000fedc
+DPCR swl +2 base=0x11223344 src=0xfedcba98 got=0x00fedcba
+DPCR swl +3 base=0x11223344 src=0xfedcba98 got=0xfedcba98
+DPCR swr +0 base=0x11223344 src=0xfedcba98 got=0xfedcba98
+DPCR swr +1 base=0x11223344 src=0xfedcba98 got=0xdcba9800
+DPCR swr +2 base=0x11223344 src=0xfedcba98 got=0xba980000
+DPCR swr +3 base=0x11223344 src=0xfedcba98 got=0x98000000
+
+--- SPU_MAINVOL_L @ 0xbf801d80 (SBUS, 16-bit) ---
+SPU_MAINVOL_L sh +0 base=0x00000000 src=0xaabbccdd got=0xccdd neigh=0x0000
+SPU_MAINVOL_L sb +0 base=0x00000000 src=0xaabbccdd got=0xccdd neigh=0x0000
+SPU_MAINVOL_L sb +1 base=0x00000000 src=0xaabbccdd got=0x0000 neigh=0x0000
+SPU_MAINVOL_L sb +2 base=0x00000000 src=0xaabbccdd got=0x0000 neigh=0xccdd
+SPU_MAINVOL_L sb +3 base=0x00000000 src=0xaabbccdd got=0x0000 neigh=0x0000
+SPU_MAINVOL_L swl +0 base=0x00000000 src=0xaabbccdd got=0x00aa neigh=0x0000
+SPU_MAINVOL_L swl +1 base=0x00000000 src=0xaabbccdd got=0xaabb neigh=0x0000
+SPU_MAINVOL_L swl +2 base=0x00000000 src=0xaabbccdd got=0xbbcc neigh=0x0000
+SPU_MAINVOL_L swl +3 base=0x00000000 src=0xaabbccdd got=0xccdd neigh=0xaabb
+SPU_MAINVOL_L swr +0 base=0x00000000 src=0xaabbccdd got=0xccdd neigh=0xaabb
+SPU_MAINVOL_L swr +1 base=0x00000000 src=0xaabbccdd got=0xdd00 neigh=0x0000
+SPU_MAINVOL_L swr +2 base=0x00000000 src=0xaabbccdd got=0x0000 neigh=0xccdd
+SPU_MAINVOL_L swr +3 base=0x00000000 src=0xaabbccdd got=0x0000 neigh=0x0000
+SPU_MAINVOL_L sh +0 base=0x00000000 src=0xfedcba98 got=0xba98 neigh=0x0000
+SPU_MAINVOL_L sb +0 base=0x00000000 src=0xfedcba98 got=0xba98 neigh=0x0000
+SPU_MAINVOL_L sb +1 base=0x00000000 src=0xfedcba98 got=0x0000 neigh=0x0000
+SPU_MAINVOL_L sb +2 base=0x00000000 src=0xfedcba98 got=0x0000 neigh=0xba98
+SPU_MAINVOL_L sb +3 base=0x00000000 src=0xfedcba98 got=0x0000 neigh=0x0000
+SPU_MAINVOL_L swl +0 base=0x00000000 src=0xfedcba98 got=0x00fe neigh=0x0000
+SPU_MAINVOL_L swl +1 base=0x00000000 src=0xfedcba98 got=0xfedc neigh=0x0000
+SPU_MAINVOL_L swl +2 base=0x00000000 src=0xfedcba98 got=0xdcba neigh=0x0000
+SPU_MAINVOL_L swl +3 base=0x00000000 src=0xfedcba98 got=0xba98 neigh=0xfedc
+SPU_MAINVOL_L swr +0 base=0x00000000 src=0xfedcba98 got=0xba98 neigh=0xfedc
+SPU_MAINVOL_L swr +1 base=0x00000000 src=0xfedcba98 got=0x9800 neigh=0x0000
+SPU_MAINVOL_L swr +2 base=0x00000000 src=0xfedcba98 got=0x0000 neigh=0xba98
+SPU_MAINVOL_L swr +3 base=0x00000000 src=0xfedcba98 got=0x0000 neigh=0x0000
+SPU_MAINVOL_L sh +0 base=0xffffffff src=0xaabbccdd got=0xccdd neigh=0xffff
+SPU_MAINVOL_L sb +0 base=0xffffffff src=0xaabbccdd got=0xccdd neigh=0xffff
+SPU_MAINVOL_L sb +1 base=0xffffffff src=0xaabbccdd got=0xffff neigh=0xffff
+SPU_MAINVOL_L sb +2 base=0xffffffff src=0xaabbccdd got=0xffff neigh=0xccdd
+SPU_MAINVOL_L sb +3 base=0xffffffff src=0xaabbccdd got=0xffff neigh=0xffff
+SPU_MAINVOL_L swl +0 base=0xffffffff src=0xaabbccdd got=0x00aa neigh=0xffff
+SPU_MAINVOL_L swl +1 base=0xffffffff src=0xaabbccdd got=0xaabb neigh=0xffff
+SPU_MAINVOL_L swl +2 base=0xffffffff src=0xaabbccdd got=0xbbcc neigh=0xffff
+SPU_MAINVOL_L swl +3 base=0xffffffff src=0xaabbccdd got=0xccdd neigh=0xaabb
+SPU_MAINVOL_L swr +0 base=0xffffffff src=0xaabbccdd got=0xccdd neigh=0xaabb
+SPU_MAINVOL_L swr +1 base=0xffffffff src=0xaabbccdd got=0xdd00 neigh=0xffff
+SPU_MAINVOL_L swr +2 base=0xffffffff src=0xaabbccdd got=0xffff neigh=0xccdd
+SPU_MAINVOL_L swr +3 base=0xffffffff src=0xaabbccdd got=0xffff neigh=0xffff
+SPU_MAINVOL_L sh +0 base=0xffffffff src=0xfedcba98 got=0xba98 neigh=0xffff
+SPU_MAINVOL_L sb +0 base=0xffffffff src=0xfedcba98 got=0xba98 neigh=0xffff
+SPU_MAINVOL_L sb +1 base=0xffffffff src=0xfedcba98 got=0xffff neigh=0xffff
+SPU_MAINVOL_L sb +2 base=0xffffffff src=0xfedcba98 got=0xffff neigh=0xba98
+SPU_MAINVOL_L sb +3 base=0xffffffff src=0xfedcba98 got=0xffff neigh=0xffff
+SPU_MAINVOL_L swl +0 base=0xffffffff src=0xfedcba98 got=0x00fe neigh=0xffff
+SPU_MAINVOL_L swl +1 base=0xffffffff src=0xfedcba98 got=0xfedc neigh=0xffff
+SPU_MAINVOL_L swl +2 base=0xffffffff src=0xfedcba98 got=0xdcba neigh=0xffff
+SPU_MAINVOL_L swl +3 base=0xffffffff src=0xfedcba98 got=0xba98 neigh=0xfedc
+SPU_MAINVOL_L swr +0 base=0xffffffff src=0xfedcba98 got=0xba98 neigh=0xfedc
+SPU_MAINVOL_L swr +1 base=0xffffffff src=0xfedcba98 got=0x9800 neigh=0xffff
+SPU_MAINVOL_L swr +2 base=0xffffffff src=0xfedcba98 got=0xffff neigh=0xba98
+SPU_MAINVOL_L swr +3 base=0xffffffff src=0xfedcba98 got=0xffff neigh=0xffff
+SPU_MAINVOL_L sh +0 base=0x11223344 src=0xaabbccdd got=0xccdd neigh=0x3344
+SPU_MAINVOL_L sb +0 base=0x11223344 src=0xaabbccdd got=0xccdd neigh=0x3344
+SPU_MAINVOL_L sb +1 base=0x11223344 src=0xaabbccdd got=0x3344 neigh=0x3344
+SPU_MAINVOL_L sb +2 base=0x11223344 src=0xaabbccdd got=0x3344 neigh=0xccdd
+SPU_MAINVOL_L sb +3 base=0x11223344 src=0xaabbccdd got=0x3344 neigh=0x3344
+SPU_MAINVOL_L swl +0 base=0x11223344 src=0xaabbccdd got=0x00aa neigh=0x3344
+SPU_MAINVOL_L swl +1 base=0x11223344 src=0xaabbccdd got=0xaabb neigh=0x3344
+SPU_MAINVOL_L swl +2 base=0x11223344 src=0xaabbccdd got=0xbbcc neigh=0x3344
+SPU_MAINVOL_L swl +3 base=0x11223344 src=0xaabbccdd got=0xccdd neigh=0xaabb
+SPU_MAINVOL_L swr +0 base=0x11223344 src=0xaabbccdd got=0xccdd neigh=0xaabb
+SPU_MAINVOL_L swr +1 base=0x11223344 src=0xaabbccdd got=0xdd00 neigh=0x3344
+SPU_MAINVOL_L swr +2 base=0x11223344 src=0xaabbccdd got=0x3344 neigh=0xccdd
+SPU_MAINVOL_L swr +3 base=0x11223344 src=0xaabbccdd got=0x3344 neigh=0x3344
+SPU_MAINVOL_L sh +0 base=0x11223344 src=0xfedcba98 got=0xba98 neigh=0x3344
+SPU_MAINVOL_L sb +0 base=0x11223344 src=0xfedcba98 got=0xba98 neigh=0x3344
+SPU_MAINVOL_L sb +1 base=0x11223344 src=0xfedcba98 got=0x3344 neigh=0x3344
+SPU_MAINVOL_L sb +2 base=0x11223344 src=0xfedcba98 got=0x3344 neigh=0xba98
+SPU_MAINVOL_L sb +3 base=0x11223344 src=0xfedcba98 got=0x3344 neigh=0x3344
+SPU_MAINVOL_L swl +0 base=0x11223344 src=0xfedcba98 got=0x00fe neigh=0x3344
+SPU_MAINVOL_L swl +1 base=0x11223344 src=0xfedcba98 got=0xfedc neigh=0x3344
+SPU_MAINVOL_L swl +2 base=0x11223344 src=0xfedcba98 got=0xdcba neigh=0x3344
+SPU_MAINVOL_L swl +3 base=0x11223344 src=0xfedcba98 got=0xba98 neigh=0xfedc
+SPU_MAINVOL_L swr +0 base=0x11223344 src=0xfedcba98 got=0xba98 neigh=0xfedc
+SPU_MAINVOL_L swr +1 base=0x11223344 src=0xfedcba98 got=0x9800 neigh=0x3344
+SPU_MAINVOL_L swr +2 base=0x11223344 src=0xfedcba98 got=0x3344 neigh=0xba98
+SPU_MAINVOL_L swr +3 base=0x11223344 src=0xfedcba98 got=0x3344 neigh=0x3344
+
+--- SPU_V0_VOL_L @ 0xbf801c00 (SBUS, 16-bit) ---
+SPU_V0_VOL_L sh +0 base=0x00000000 src=0xaabbccdd got=0xccdd neigh=0x0000
+SPU_V0_VOL_L sb +0 base=0x00000000 src=0xaabbccdd got=0xccdd neigh=0x0000
+SPU_V0_VOL_L sb +1 base=0x00000000 src=0xaabbccdd got=0x0000 neigh=0x0000
+SPU_V0_VOL_L sb +2 base=0x00000000 src=0xaabbccdd got=0x0000 neigh=0xccdd
+SPU_V0_VOL_L sb +3 base=0x00000000 src=0xaabbccdd got=0x0000 neigh=0x0000
+SPU_V0_VOL_L swl +0 base=0x00000000 src=0xaabbccdd got=0x00aa neigh=0x0000
+SPU_V0_VOL_L swl +1 base=0x00000000 src=0xaabbccdd got=0xaabb neigh=0x0000
+SPU_V0_VOL_L swl +2 base=0x00000000 src=0xaabbccdd got=0xbbcc neigh=0x0000
+SPU_V0_VOL_L swl +3 base=0x00000000 src=0xaabbccdd got=0xccdd neigh=0xaabb
+SPU_V0_VOL_L swr +0 base=0x00000000 src=0xaabbccdd got=0xccdd neigh=0xaabb
+SPU_V0_VOL_L swr +1 base=0x00000000 src=0xaabbccdd got=0xdd00 neigh=0x0000
+SPU_V0_VOL_L swr +2 base=0x00000000 src=0xaabbccdd got=0x0000 neigh=0xccdd
+SPU_V0_VOL_L swr +3 base=0x00000000 src=0xaabbccdd got=0x0000 neigh=0x0000
+SPU_V0_VOL_L sh +0 base=0x00000000 src=0xfedcba98 got=0xba98 neigh=0x0000
+SPU_V0_VOL_L sb +0 base=0x00000000 src=0xfedcba98 got=0xba98 neigh=0x0000
+SPU_V0_VOL_L sb +1 base=0x00000000 src=0xfedcba98 got=0x0000 neigh=0x0000
+SPU_V0_VOL_L sb +2 base=0x00000000 src=0xfedcba98 got=0x0000 neigh=0xba98
+SPU_V0_VOL_L sb +3 base=0x00000000 src=0xfedcba98 got=0x0000 neigh=0x0000
+SPU_V0_VOL_L swl +0 base=0x00000000 src=0xfedcba98 got=0x00fe neigh=0x0000
+SPU_V0_VOL_L swl +1 base=0x00000000 src=0xfedcba98 got=0xfedc neigh=0x0000
+SPU_V0_VOL_L swl +2 base=0x00000000 src=0xfedcba98 got=0xdcba neigh=0x0000
+SPU_V0_VOL_L swl +3 base=0x00000000 src=0xfedcba98 got=0xba98 neigh=0xfedc
+SPU_V0_VOL_L swr +0 base=0x00000000 src=0xfedcba98 got=0xba98 neigh=0xfedc
+SPU_V0_VOL_L swr +1 base=0x00000000 src=0xfedcba98 got=0x9800 neigh=0x0000
+SPU_V0_VOL_L swr +2 base=0x00000000 src=0xfedcba98 got=0x0000 neigh=0xba98
+SPU_V0_VOL_L swr +3 base=0x00000000 src=0xfedcba98 got=0x0000 neigh=0x0000
+SPU_V0_VOL_L sh +0 base=0xffffffff src=0xaabbccdd got=0xccdd neigh=0xffff
+SPU_V0_VOL_L sb +0 base=0xffffffff src=0xaabbccdd got=0xccdd neigh=0xffff
+SPU_V0_VOL_L sb +1 base=0xffffffff src=0xaabbccdd got=0xffff neigh=0xffff
+SPU_V0_VOL_L sb +2 base=0xffffffff src=0xaabbccdd got=0xffff neigh=0xccdd
+SPU_V0_VOL_L sb +3 base=0xffffffff src=0xaabbccdd got=0xffff neigh=0xffff
+SPU_V0_VOL_L swl +0 base=0xffffffff src=0xaabbccdd got=0x00aa neigh=0xffff
+SPU_V0_VOL_L swl +1 base=0xffffffff src=0xaabbccdd got=0xaabb neigh=0xffff
+SPU_V0_VOL_L swl +2 base=0xffffffff src=0xaabbccdd got=0xbbcc neigh=0xffff
+SPU_V0_VOL_L swl +3 base=0xffffffff src=0xaabbccdd got=0xccdd neigh=0xaabb
+SPU_V0_VOL_L swr +0 base=0xffffffff src=0xaabbccdd got=0xccdd neigh=0xaabb
+SPU_V0_VOL_L swr +1 base=0xffffffff src=0xaabbccdd got=0xdd00 neigh=0xffff
+SPU_V0_VOL_L swr +2 base=0xffffffff src=0xaabbccdd got=0xffff neigh=0xccdd
+SPU_V0_VOL_L swr +3 base=0xffffffff src=0xaabbccdd got=0xffff neigh=0xffff
+SPU_V0_VOL_L sh +0 base=0xffffffff src=0xfedcba98 got=0xba98 neigh=0xffff
+SPU_V0_VOL_L sb +0 base=0xffffffff src=0xfedcba98 got=0xba98 neigh=0xffff
+SPU_V0_VOL_L sb +1 base=0xffffffff src=0xfedcba98 got=0xffff neigh=0xffff
+SPU_V0_VOL_L sb +2 base=0xffffffff src=0xfedcba98 got=0xffff neigh=0xba98
+SPU_V0_VOL_L sb +3 base=0xffffffff src=0xfedcba98 got=0xffff neigh=0xffff
+SPU_V0_VOL_L swl +0 base=0xffffffff src=0xfedcba98 got=0x00fe neigh=0xffff
+SPU_V0_VOL_L swl +1 base=0xffffffff src=0xfedcba98 got=0xfedc neigh=0xffff
+SPU_V0_VOL_L swl +2 base=0xffffffff src=0xfedcba98 got=0xdcba neigh=0xffff
+SPU_V0_VOL_L swl +3 base=0xffffffff src=0xfedcba98 got=0xba98 neigh=0xfedc
+SPU_V0_VOL_L swr +0 base=0xffffffff src=0xfedcba98 got=0xba98 neigh=0xfedc
+SPU_V0_VOL_L swr +1 base=0xffffffff src=0xfedcba98 got=0x9800 neigh=0xffff
+SPU_V0_VOL_L swr +2 base=0xffffffff src=0xfedcba98 got=0xffff neigh=0xba98
+SPU_V0_VOL_L swr +3 base=0xffffffff src=0xfedcba98 got=0xffff neigh=0xffff
+SPU_V0_VOL_L sh +0 base=0x11223344 src=0xaabbccdd got=0xccdd neigh=0x3344
+SPU_V0_VOL_L sb +0 base=0x11223344 src=0xaabbccdd got=0xccdd neigh=0x3344
+SPU_V0_VOL_L sb +1 base=0x11223344 src=0xaabbccdd got=0x3344 neigh=0x3344
+SPU_V0_VOL_L sb +2 base=0x11223344 src=0xaabbccdd got=0x3344 neigh=0xccdd
+SPU_V0_VOL_L sb +3 base=0x11223344 src=0xaabbccdd got=0x3344 neigh=0x3344
+SPU_V0_VOL_L swl +0 base=0x11223344 src=0xaabbccdd got=0x00aa neigh=0x3344
+SPU_V0_VOL_L swl +1 base=0x11223344 src=0xaabbccdd got=0xaabb neigh=0x3344
+SPU_V0_VOL_L swl +2 base=0x11223344 src=0xaabbccdd got=0xbbcc neigh=0x3344
+SPU_V0_VOL_L swl +3 base=0x11223344 src=0xaabbccdd got=0xccdd neigh=0xaabb
+SPU_V0_VOL_L swr +0 base=0x11223344 src=0xaabbccdd got=0xccdd neigh=0xaabb
+SPU_V0_VOL_L swr +1 base=0x11223344 src=0xaabbccdd got=0xdd00 neigh=0x3344
+SPU_V0_VOL_L swr +2 base=0x11223344 src=0xaabbccdd got=0x3344 neigh=0xccdd
+SPU_V0_VOL_L swr +3 base=0x11223344 src=0xaabbccdd got=0x3344 neigh=0x3344
+SPU_V0_VOL_L sh +0 base=0x11223344 src=0xfedcba98 got=0xba98 neigh=0x3344
+SPU_V0_VOL_L sb +0 base=0x11223344 src=0xfedcba98 got=0xba98 neigh=0x3344
+SPU_V0_VOL_L sb +1 base=0x11223344 src=0xfedcba98 got=0x3344 neigh=0x3344
+SPU_V0_VOL_L sb +2 base=0x11223344 src=0xfedcba98 got=0x3344 neigh=0xba98
+SPU_V0_VOL_L sb +3 base=0x11223344 src=0xfedcba98 got=0x3344 neigh=0x3344
+SPU_V0_VOL_L swl +0 base=0x11223344 src=0xfedcba98 got=0x00fe neigh=0x3344
+SPU_V0_VOL_L swl +1 base=0x11223344 src=0xfedcba98 got=0xfedc neigh=0x3344
+SPU_V0_VOL_L swl +2 base=0x11223344 src=0xfedcba98 got=0xdcba neigh=0x3344
+SPU_V0_VOL_L swl +3 base=0x11223344 src=0xfedcba98 got=0xba98 neigh=0xfedc
+SPU_V0_VOL_L swr +0 base=0x11223344 src=0xfedcba98 got=0xba98 neigh=0xfedc
+SPU_V0_VOL_L swr +1 base=0x11223344 src=0xfedcba98 got=0x9800 neigh=0x3344
+SPU_V0_VOL_L swr +2 base=0x11223344 src=0xfedcba98 got=0x3344 neigh=0xba98
+SPU_V0_VOL_L swr +3 base=0x11223344 src=0xfedcba98 got=0x3344 neigh=0x3344
+
+=== Done ===
+ResetGraph:jtb=801e78b8,env=801e7900
+```
+
+[bench.txt](/tests/raw/20261022T2245Z-5501a-link-4/regwrites/bench.txt):
+
+```
+27723 bytes of TTY text in psx.log
+```
+
+[when.txt](/tests/raw/20261022T2245Z-5501a-link-4/regwrites/when.txt):
+
+```
+20261022T2245Z
+```
+
+## References
+
+[^src]: pcsx-redux nugget, tests/regwrites/regwrites.c, header comment. MIT License. https://github.com/pcsx-redux/nugget
+[^run]: Hardware test run 20261022T2245Z-5501a-link-4 on the SCPH-5501: [REGWRITES.txt](/tests/raw/20261022T2245Z-5501a-link-4/regwrites/REGWRITES.txt).