SPU Voice After End and Mute: Difference between revisions
| Revision as of 05:40, 23 October 2026 RemmyLee (Hardware tests: 15 more test pages (CPU, DMA, SPU, GPU, MDEC, CD-ROM, bus), each with See also links to the pages that measure the same parts) | Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | ||
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| The IRQ address is set in turn to M's first block (M0), to the first three blocks of R (R0, R1, R2) and to its last block (R3), and to an address no block reaches (X). After key on, the probe counts system clock cycles on root counter 2 until SPUSTAT bit 6 sets. It waits up to 400000 cycles and makes two rounds for each address.[^run] | The IRQ address is set in turn to M's first block (M0), to the first three blocks of R (R0, R1, R2) and to its last block (R3), and to an address no block reaches (X). After key on, the probe counts system clock cycles on root counter 2 until SPUSTAT bit 6 sets. It waits up to 400000 cycles and makes two rounds for each address.[^run] | ||
| + | See also: | ||
| + | |||
| + | - [SPU Voice Flags and Interrupts](/tests/spu-voice-flags-interrupts/) | ||
| + | |||
| ## Results | ## Results | ||