SPU Read Timing: Difference between revisions

Revision as of 04:48, 23 October 2026
RemmyLee
(Main page: drop the Hardware Tests lede)

Revision as of 05:11, 23 October 2026
RemmyLee
(Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published)

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---

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title: SPU Read Timing

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type: test

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summary: Times one load from the SPU and two loads in a row against the SPU delay register and COM_DELAY.

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category: Hardware tests

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info: Machine = SCPH-5501

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info: Program = spulhu and spulhu2

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---

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## Overview

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The probes time a single load with root counter 2 counting system clock cycles. Root counter 2 is read with LHU just before and just after the load. A second stub with a NOP in place of the load gives the overhead. The difference between the two is the "net" time of the load. Each case runs eight times after FlushCache, and the eighth run comes from a warm cache.[^run1]

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The first probe sets COM0 in COM_DELAY (1F801020h) to each value from 0 to 15, then the SPU read delay (bits 4 to 7 of 1F801014h) to each value from 0 to 15. It puts a NOP, a store to RAM, a store to an I/O register, or another SPU load just before the timed load.[^run1]

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The second probe times one load alone and two loads back to back. It covers the SPU read delay with bit 8 on and off, COM2 with bit 10 on and COM3 with bit 11 on, word and byte loads, a CD-ROM register, the BIOS ROM, and two SPU loads with 1 to 5 NOPs between them.[^run2] The [memory control](/hardware/memory-control/) page describes these registers.

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## Results

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A single LHU from the SPU costs the SPU read delay plus 5 cycles. With the delay register as found (200931E1h, read delay 14) it costs 19 cycles, and the read delay steps it from 5 cycles at 0 to 20 cycles at 15.[^run1]

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COM0 does not change a single SPU load. With a NOP, a store to RAM or a store to an I/O register before the load, the warm net stayed at 19 cycles for every COM0 from 0 to 15. However, COM0 applies when one SPU load follows another: the second load then cost the read delay plus COM0 (COM0 values below 3 counting as 3).[^run1]

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Table: SPU LHU after another SPU LHU by COM0

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| COM0 | Net cycles |

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| --- | --- |

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| 0 to 3 | 17 |

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| 4 | 18 |

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| 5 | 19 |

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| 10 | 24 |

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| 15 | 29 |

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Clearing bit 8 of the SPU delay register (200930E1h) removes the COM0 cost: two loads in a row cost 17 cycles with COM0 at 0 and at 15. With bit 10 set, COM2 adds to the second load: it cost 17, 20 and 30 cycles for COM2 of 0, 5 and 15. With bit 11 set, COM3 changed the time by at most one cycle. Placing 1, 2, 3 or 5 NOPs between two SPU loads with COM0 at 15 did not shorten the second load, which cost 29 cycles in every case.[^run2]

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Table: Other loads in net cycles

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| --- | --- | --- | --- | --- |

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| SPU LHU | 19 | 17 | 19 | 29 |

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| SPU LB | 19 | 17 | 19 | 29 |

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| SPU LW | 35 to 49 | 33 | 39 | 59 |

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| CD-ROM LBU (delay 00020943h) | 9 | 7 | 9 | 19 |

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| BIOS ROM LW | 26 | 24 | 24 | 24 |

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A single SPU LW took 35, 39 and 49 cycles with COM0 at 0, 5 and 15, whereas the BIOS ROM load did not depend on COM0.[^run2]

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## Runs

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### Run 5501a-link-spulhu on 9 October 2026

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Raw output: [SPULHU1.txt](/tests/raw/20261009T0000Z-5501a-link-spulhu/spulhu/SPULHU1.txt) · [SPULHU2.txt](/tests/raw/20261009T0000Z-5501a-link-spulhu/spulhu/SPULHU2.txt)

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The output of this run is 89 KB. Its files are listed above and are not shown in full on this page.

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## References

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[^run1]: Hardware test run 20261009T0000Z-5501a-link-spulhu on the SCPH-5501: [SPULHU1.txt](/tests/raw/20261009T0000Z-5501a-link-spulhu/spulhu/SPULHU1.txt).

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[^run2]: Hardware test run 20261009T0000Z-5501a-link-spulhu on the SCPH-5501: [SPULHU2.txt](/tests/raw/20261009T0000Z-5501a-link-spulhu/spulhu/SPULHU2.txt).