SPU Wide Writes: Difference between revisions
| Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | Revision as of 05:18, 23 October 2026 RemmyLee (Hardware tests: nine DMA, MDEC and BIOS test pages with part names for titles; join one-sentence paragraphs per voice.md) | ||
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| Two halfword stores never lost a half. In the burst, the losses fell on all eight pairs in uneven numbers, between 63 and 257 each. A byte store to byte 1 was lost every time under every setting.[^run] | Two halfword stores never lost a half. In the burst, the losses fell on all eight pairs in uneven numbers, between 63 and 257 each. A byte store to byte 1 was lost every time under every setting.[^run] | ||
| − | The SPU write delay in bits 0 to 3 decides the loss. With bits 0 to 3 at Fh (200931EFh and 200931FFh) no SW, SH or burst store lost a half. With bits 8 and 9 set (200933E1h) none was lost either. With bits 8 and 10 set (200935E1h) the SW stores lost their low half as often as at 200931E1h.[^run] | + | The SPU write delay in bits 0 to 3 decides the loss. With bits 0 to 3 at Fh (200931EFh and 200931FFh) no SW, SH or burst store lost a half. With bits 8 and 9 set (200933E1h) none was lost either. With bits 8 and 10 set (200935E1h) the SW stores lost their low half as often as at 200931E1h.[^run] With bit 8 clear (200930E1h) every SW, SH and burst write to the high half was lost while the low half always landed.[^run] The [SPU 32-bit Stores](/tests/spu-32-bit-stores/) probe, whose stores were spaced 1536 cycles apart, found no loss on the same register with the same delay value. |
| − | With bit 8 clear (200930E1h) every SW, SH and burst write to the high half was lost while the low half always landed.[^run] | ||
| − | |||
| − | The [SPU 32-bit Stores](/tests/spu-32-bit-stores/) probe, whose stores were spaced 1536 cycles apart, found no loss on the same register with the same delay value. | ||
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| ## Runs | ## Runs | ||