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SPU Wide Writes: Difference between revisions

Revision as of 04:31, 23 October 2026
RemmyLee
(Hardware tests: test page type, raw console output served from truth/, first test page)		Revision as of 05:18, 23 October 2026
RemmyLee
(Hardware tests: nine DMA, MDEC and BIOS test pages with part names for titles; join one-sentence paragraphs per voice.md)
Line 1:Line 1:
+---
+title: SPU Wide Writes
+type: test
+summary: Counts how often a 32-bit store to an SPU register pair loses a half for each tested value of the SPU delay register.
+category: Hardware tests
+info: Machine = SCPH-5501
+info: Program = spu-wide-writes (pcsx-redux nugget)
+---
+
+## Overview
+
+A SW to an SPU register pair reaches the SPU as two halfword writes. The program checks thousands of times whether both halves land. The targets read back what was written and do nothing while no voice plays: the reverb configuration at 1F801DC0h with reverb off, and the voice 0 ADSR pair at 1F801C08h with voice 0 keyed off.[^src]
+
+Each target gets five kinds of write. SW is one 32-bit store read back at once, and SH is two halfword stores read back the same way. swLate is a SW read back after about 2000 cycles, burst is SW to eight pairs in a row, and sb1 is a byte store to byte 1, which the SPU drops. A wrong half is read again after a delay to tell a late write from a lost one.[^src]
+
+The program runs the set with the SPU delay register (1F801014h) as found, then with the value set to 200931E1h, 200931EFh, 200931FFh, 200930E1h, 200933E1h and 200935E1h.[^src][^run] The [memory control](/hardware/memory-control/) page describes the delay register.
+
+## Results
+
+With the SPU delay register at 200931E1h, as found, about half of all SW stores lost their low half and none lost the high half. A lost half was never written late: it stayed at its old value.[^run]
+
+Table: Lost halves with the SPU delay register at 200931E1h
+
+| Write | Target | Stores | Low half lost | High half lost |
+| --- | --- | --- | --- | --- |
+| SW | Reverb | 8192 | 4094 | 0 |
+| SW | ADSR | 8192 | 4089 | 0 |
+| SH, two stores | Reverb and ADSR | 8192 each | 0 | 0 |
+| SW, late read | Reverb | 2048 | 511 | 0 |
+| SW, burst of 8 | Reverb | 8192 | 1024 | 0 |
+| SB to byte 1 | Reverb and ADSR | 1024 each | 1024 | 0 |
+
+Two halfword stores never lost a half. In the burst, the losses fell on all eight pairs in uneven numbers, between 63 and 257 each. A byte store to byte 1 was lost every time under every setting.[^run]
+
+The SPU write delay in bits 0 to 3 decides the loss. With bits 0 to 3 at Fh (200931EFh and 200931FFh) no SW, SH or burst store lost a half. With bits 8 and 9 set (200933E1h) none was lost either. With bits 8 and 10 set (200935E1h) the SW stores lost their low half as often as at 200931E1h.[^run] With bit 8 clear (200930E1h) every SW, SH and burst write to the high half was lost while the low half always landed.[^run] The [SPU 32-bit Stores](/tests/spu-32-bit-stores/) probe, whose stores were spaced 1536 cycles apart, found no loss on the same register with the same delay value.
+
+## Runs
+
+### Run 5501a-link on 22 October 2026
+
+Raw output: [SPUWIDEWRITES.txt](/tests/raw/20261022T2245Z-5501a-link/spuwidewrites/SPUWIDEWRITES.txt)
+
+SPUWIDEWRITES.txt:
+
+```
+SPUW-START spucnt=c085 spudelay=200931e1
+SPUW rev0 sw n=8192 missLo=4094 missHi=0 lateLo=0 lateHi=0 badBits=ffff/0000 first wrote=703a0788 got=703aac98
+SPUW rev0 sh n=8192 missLo=0 missHi=0 lateLo=0 lateHi=0 badBits=0000/0000
+SPUW rev0 swLate n=2048 missLo=511 missHi=0 lateLo=0 lateHi=0 badBits=ffff/0000 first wrote=f7ac8739 got=f7acbd0f
+SPUW rev0 sb1 n=1024 missLo=1024 missHi=0 lateLo=0 lateHi=0 badBits=ffff/0000 first wrote=6533616e got=65338ee8
+SPUW adsr0 sw n=8192 missLo=4089 missHi=0 lateLo=0 lateHi=0 badBits=ffff/0000 first wrote=bbd0f1c0 got=bbd07ab4
+SPUW adsr0 sh n=8192 missLo=0 missHi=0 lateLo=0 lateHi=0 badBits=0000/0000
+SPUW adsr0 swLate n=2048 missLo=510 missHi=0 lateLo=0 lateHi=0 badBits=ffff/0000 first wrote=2a6f5a7b got=2a6f6a2b
+SPUW adsr0 sb1 n=1024 missLo=1024 missHi=0 lateLo=0 lateHi=0 badBits=ffff/0000 first wrote=a1d4f120 got=a1d40e20
+SPUW rev0-7 burst n=8192 missLo=1024 missHi=0 lateLo=0 lateHi=0 badBits=ffff/0000 first wrote=93fb5d6e got=93fb7e00
+SPUW rev0-7 slots 0:128/128 1:66/66 2:63/63 3:257/257 4:128/128 5:253/253 6:65/65 7:64/64
+SPUW rev0 sw n=8192 missLo=4067 missHi=0 lateLo=0 lateHi=0 badBits=ffff/0000 first wrote=8ec6fad7 got=8ec665c3
+SPUW rev0 sh n=8192 missLo=0 missHi=0 lateLo=0 lateHi=0 badBits=0000/0000
+SPUW rev0 swLate n=2048 missLo=509 missHi=0 lateLo=0 lateHi=0 badBits=ffff/0000 first wrote=9acc7f3d got=9acc4ee5
+SPUW rev0 sb1 n=1024 missLo=1024 missHi=0 lateLo=0 lateHi=0 badBits=ffff/0000 first wrote=57336f5d got=5733905d
+SPUW adsr0 sw n=8192 missLo=4086 missHi=0 lateLo=0 lateHi=0 badBits=ffff/0000 first wrote=d0534625 got=d05318b5
+SPUW adsr0 sh n=8192 missLo=0 missHi=0 lateLo=0 lateHi=0 badBits=0000/0000
+SPUW adsr0 swLate n=2048 missLo=510 missHi=0 lateLo=0 lateHi=0 badBits=ffff/0000 first wrote=43f3245e got=43f39afa
+SPUW adsr0 sb1 n=1024 missLo=1024 missHi=0 lateLo=0 lateHi=0 badBits=ffff/0000 first wrote=3b6b18eb got=3b6be7eb
+SPUW rev0-7 burst n=8192 missLo=1024 missHi=0 lateLo=0 lateHi=0 badBits=ffff/0000 first wrote=73a1ad63 got=73a18c34
+SPUW rev0-7 slots 0:128/128 1:65/65 2:64/64 3:256/256 4:128/128 5:255/255 6:64/64 7:64/64
+SPUW-DELAY set=200931e1 read=200931e1
+SPUW rev0 sw n=8192 missLo=4078 missHi=0 lateLo=0 lateHi=0 badBits=ffff/0000 first wrote=412accad got=412a91ee
+SPUW rev0 sh n=8192 missLo=0 missHi=0 lateLo=0 lateHi=0 badBits=0000/0000
+SPUW rev0 swLate n=2048 missLo=509 missHi=0 lateLo=0 lateHi=0 badBits=ffff/0000 first wrote=d641fd7d got=d64183af
+SPUW rev0 sb1 n=1024 missLo=1024 missHi=0 lateLo=0 lateHi=0 badBits=ffff/0000 first wrote=13f6899b got=13f6769b
+SPUW rev0-7 burst n=8192 missLo=1024 missHi=0 lateLo=0 lateHi=0 badBits=ffff/0000 first wrote=1d22f011 got=1d22184d
+SPUW rev0-7 slots 0:128/128 1:64/64 2:64/64 3:255/255 4:128/128 5:257/257 6:64/64 7:64/64
+SPUW-DELAY set=200931ef read=200931ef
+SPUW rev0 sw n=8192 missLo=0 missHi=0 lateLo=0 lateHi=0 badBits=0000/0000
+SPUW rev0 sh n=8192 missLo=0 missHi=0 lateLo=0 lateHi=0 badBits=0000/0000
+SPUW rev0 swLate n=2048 missLo=0 missHi=0 lateLo=0 lateHi=0 badBits=0000/0000
+SPUW rev0 sb1 n=1024 missLo=1024 missHi=0 lateLo=0 lateHi=0 badBits=ff00/0000 first wrote=04cf2b59 got=04cfd459
+SPUW rev0-7 burst n=8192 missLo=0 missHi=0 lateLo=0 lateHi=0 badBits=0000/0000
+SPUW rev0-7 slots 0:0/0 1:0/0 2:0/0 3:0/0 4:0/0 5:0/0 6:0/0 7:0/0
+SPUW-DELAY set=200931ff read=200931ff
+SPUW rev0 sw n=8192 missLo=0 missHi=0 lateLo=0 lateHi=0 badBits=0000/0000
+SPUW rev0 sh n=8192 missLo=0 missHi=0 lateLo=0 lateHi=0 badBits=0000/0000
+SPUW rev0 swLate n=2048 missLo=0 missHi=0 lateLo=0 lateHi=0 badBits=0000/0000
+SPUW rev0 sb1 n=1024 missLo=1024 missHi=0 lateLo=0 lateHi=0 badBits=ff00/0000 first wrote=56006fbe got=560090be
+SPUW rev0-7 burst n=8192 missLo=0 missHi=0 lateLo=0 lateHi=0 badBits=0000/0000
+SPUW rev0-7 slots 0:0/0 1:0/0 2:0/0 3:0/0 4:0/0 5:0/0 6:0/0 7:0/0
+SPUW-DELAY set=200930e1 read=200930e1
+SPUW rev0 sw n=8192 missLo=0 missHi=8192 lateLo=0 lateHi=0 badBits=0000/ffff first wrote=093ea7d4 got=093ca7d4
+SPUW rev0 sh n=8192 missLo=0 missHi=8192 lateLo=0 lateHi=0 badBits=0000/ffff first wrote=62b6d265 got=093cd265
+SPUW rev0 swLate n=2048 missLo=0 missHi=2048 lateLo=0 lateHi=0 badBits=0000/ffff first wrote=8fe02fe6 got=093c2fe6
+SPUW rev0 sb1 n=1024 missLo=1024 missHi=1024 lateLo=0 lateHi=0 badBits=ff00/ffff first wrote=f5fb67b7 got=093c98b7
+SPUW rev0-7 burst n=8192 missLo=0 missHi=8192 lateLo=0 lateHi=0 badBits=0000/ffff first wrote=3612701d got=093c701d
+SPUW rev0-7 slots 0:1020/0 1:0/0 2:0/0 3:0/0 4:0/0 5:0/0 6:0/0 7:0/0
+SPUW-DELAY set=200933e1 read=200933e1
+SPUW rev0 sw n=8192 missLo=0 missHi=0 lateLo=0 lateHi=0 badBits=0000/0000
+SPUW rev0 sh n=8192 missLo=0 missHi=0 lateLo=0 lateHi=0 badBits=0000/0000
+SPUW rev0 swLate n=2048 missLo=0 missHi=0 lateLo=0 lateHi=0 badBits=0000/0000
+SPUW rev0 sb1 n=1024 missLo=1024 missHi=0 lateLo=0 lateHi=0 badBits=ff00/0000 first wrote=64344275 got=6434bd75
+SPUW rev0-7 burst n=8192 missLo=0 missHi=0 lateLo=0 lateHi=0 badBits=0000/0000
+SPUW rev0-7 slots 0:0/0 1:0/0 2:0/0 3:0/0 4:0/0 5:0/0 6:0/0 7:0/0
+SPUW-DELAY set=200935e1 read=200935e1
+SPUW rev0 sw n=8192 missLo=4079 missHi=0 lateLo=0 lateHi=0 badBits=ffff/0000 first wrote=11b8e117 got=11b87a9a
+SPUW rev0 sh n=8192 missLo=0 missHi=0 lateLo=0 lateHi=0 badBits=0000/0000
+SPUW rev0 swLate n=2048 missLo=508 missHi=0 lateLo=0 lateHi=0 badBits=ffff/0000 first wrote=4051305c got=40515e70
+SPUW rev0 sb1 n=1024 missLo=1024 missHi=0 lateLo=0 lateHi=0 badBits=ffff/0000 first wrote=351d9ba6 got=351dbadf
+SPUW rev0-7 burst n=8192 missLo=1024 missHi=0 lateLo=0 lateHi=0 badBits=ffff/0000 first wrote=b66854bc got=b668a344
+SPUW rev0-7 slots 0:291/291 1:146/146 2:4/4 3:145/145 4:145/145 5:3/3 6:290/290 7:0/0
+SPUW-DONE
+ResetGraph:jtb=801e78b8,env=801e7900
+```
+
+## References
+
+[^src]: pcsx-redux nugget, tests/spu-wide-writes/spu-wide-writes.c, header comment. MIT License. https://github.com/pcsx-redux/nugget
+[^run]: Hardware test run 20261022T2245Z-5501a-link on the SCPH-5501: [SPUWIDEWRITES.txt](/tests/raw/20261022T2245Z-5501a-link/spuwidewrites/SPUWIDEWRITES.txt).