Store and Load Sequences: Difference between revisions
| Revision as of 05:40, 23 October 2026 RemmyLee (Hardware tests: 15 more test pages (CPU, DMA, SPU, GPU, MDEC, CD-ROM, bus), each with See also links to the pages that measure the same parts) | Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | ||
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| Its GTE groups narrow the gaps that earlier runs left as ranges, and a last group reads IR1 back by SWC2 after an MTC2. Each GTE row runs cold from RAM and then cached.[^runh] | Its GTE groups narrow the gaps that earlier runs left as ranges, and a last group reads IR1 back by SWC2 after an MTC2. Each GTE row runs cold from RAM and then cached.[^runh] | ||
| + | See also: | ||
| + | |||
| + | - [CPU Pipeline Timing and Cache Isolation](/tests/cpu-pipeline-cache-isolation/) | ||
| + | |||
| ## Results | ## Results | ||