Timer Write and Cache Line Fills: Difference between revisions
| Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | Revision as of 05:18, 23 October 2026 RemmyLee (Hardware tests: nine DMA, MDEC and BIOS test pages with part names for titles; join one-sentence paragraphs per voice.md) | ||
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| ### Landing Time of the Store | ### Landing Time of the Store | ||
| − | The store to the counter lands 11 cycles after the first T1 read when the delay slot of the JALR lies in a line that is already filled. This holds cold and warm and for every target word. When the delay slot opens a new cold line, the store lands 18 cycles after the T1 read (20 in one cold run).[^run1] | + | The store to the counter lands 11 cycles after the first T1 read when the delay slot of the JALR lies in a line that is already filled. This holds cold and warm and for every target word. When the delay slot opens a new cold line, the store lands 18 cycles after the T1 read (20 in one cold run).[^run1] In the warm window, T2 read 7, 6 and 5 cycles for target words 0, 1 and 2.[^run1] |
| − | In the warm window, T2 read 7, 6 and 5 cycles for target words 0, 1 and 2.[^run1] | ||
| − | |||
| ### Cost of the Fills | ### Cost of the Fills | ||
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| ### The Instruction after the Last Timer Read | ### The Instruction after the Last Timer Read | ||
| − | The window takes one cycle more when the instruction after the last T1 read uses the register loaded by the T2 read just before it. With SW of that register or ADDU from it after the read, the window took 18 cycles warm and 37 cold. With a store of another register, a store of zero, a store to the counter or a NOP in that place it took 17 and 36. A RAM load in that place took 17 warm and 36 to 39 cold.[^run4][^run5] | + | The window takes one cycle more when the instruction after the last T1 read uses the register loaded by the T2 read just before it. With SW of that register or ADDU from it after the read, the window took 18 cycles warm and 37 cold. With a store of another register, a store of zero, a store to the counter or a NOP in that place it took 17 and 36. A RAM load in that place took 17 warm and 36 to 39 cold.[^run4][^run5] The instruction before the first T1 read made no difference.[^run4] |
| − | The instruction before the first T1 read made no difference.[^run4] | ||
| − | |||
| ## Runs | ## Runs | ||