Root Counter Clocks and Sync Modes: Difference between revisions
| Revision as of 05:11, 23 October 2026 RemmyLee (Hardware tests: 72 more test pages, listed on the main page by area; RUN.toml no longer published) | Revision as of 05:49, 23 October 2026 RemmyLee (Hardware tests: the last 15 test pages (timers, SPU, CPU, GPU, DMA, CD-ROM, GTE), See also links both ways; uncited clock claim removed) | ||
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| Last it sets timer 2's target to 10 with reset at target and counts how often each value 0 to 11 is read. It also writes the mode register and reads it back around a target hit.[^src] | Last it sets timer 2's target to 10 with reset at target and counts how often each value 0 to 11 is read. It also writes the mode register and reads it back around a target hit.[^src] | ||
| + | See also: | ||
| + | |||
| + | - [Timer Sync and SIO0 Timing](/tests/timer-sync-sio0-timing/) | ||
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| ## Results | ## Results | ||