Write Queue and GTE Interrupts: Difference between revisions
| Revision as of 05:40, 23 October 2026 RemmyLee (Hardware tests: 15 more test pages (CPU, DMA, SPU, GPU, MDEC, CD-ROM, bus), each with See also links to the pages that measure the same parts) | Revision as of 05:41, 23 October 2026 RemmyLee (Hardware tests: See also links back from 37 existing pages to the new ones) | ||
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| The groups time a RAM store and a load with NOPs between, I/O loads in pairs, runs of 1 to 40 RAM stores, the instruction that runs as a RAM load completes, a backward branch before a load, and stores and loads from code in KSEG1. They also time the CD-ROM drive's reply to a command, run a GTE command with interrupts enabled and repeat GTE rows from four places in the cache.[^runh] | The groups time a RAM store and a load with NOPs between, I/O loads in pairs, runs of 1 to 40 RAM stores, the instruction that runs as a RAM load completes, a backward branch before a load, and stores and loads from code in KSEG1. They also time the CD-ROM drive's reply to a command, run a GTE command with interrupts enabled and repeat GTE rows from four places in the cache.[^runh] | ||
| + | See also: | ||
| + | |||
| + | - [CPU Pipeline Timing and Cache Isolation](/tests/cpu-pipeline-cache-isolation/) | ||
| + | |||
| ## Results | ## Results | ||