View source for DMA Registers and Timer Pulse Mode

This is an old revision of this page, as edited by RemmyLee at 05:49, 23 October 2026. Publishing it replaces the current version.
← DMA Registers and Timer Pulse Mode
You do not have permission to edit this page. Log in to edit.
---
title: DMA Registers and Timer Pulse Mode
type: test
summary: Measures OTC transfer times, the DMA registers at 1F8010F8h and 1F8010FCh, the timer reached-target bit in pulse mode, SPU register 1DA0h, the first samples after key on and the MDEC status after a reset.
category: Hardware tests
info: Machine = SCPH-5501
info: Program = followup29
---

## Overview

The program runs seven groups. Each one prints what the console did, and the times are counts of root counter 2.[^run][^otl]

Table: Groups

| Tag | Group |
| --- | --- |
| HWT | A RAM sh and one access, then a store that links a DMA2 list node 4, 8 or 16 nodes ahead of D2_MADR to a side node |
| OTL | 32 OTC transfers of 64 words in a row with 0 to 15 NOPs before each CHCR write, and 200 loads from RAM and from the scratchpad |
| PLW | Timer 0, 1 and 2 in pulse mode with target 0100h, mode register read 448 times |
| F8C | 1F8010F8h and 1F8010FCh read after a transfer on each DMA channel and after DPCR and DICR writes |
| UDA | SPU registers 1E60h to 1E7Fh as found, and 1DA0h read 256 times by SPUCNT setting and voice state |
| GSN | Voice 1 keyed on at four pitches, and the first samples of the capture |
| MRT | The MDEC status 0 to 100 NOPs after a reset written at the end of a decode |

See also:

- [DMA Registers and Interrupt Latency](/tests/dma2/)
- [Root Counter Mode Combinations](/tests/timers3/)

## Results

### OTC Transfers

Each OTC of 64 words took 86 to 97 counts from before its CHCR write to the poll that saw CHCR bit 24 clear. With 0 NOPs before the CHCR write the times were 86, 88, 90 or 96 counts, and with 1 to 15 NOPs they were mostly 87 and 97. The table in RAM was correct after the last transfer.[^otl] From cached code, 200 loads from RAM took 1,422 to 1,428 counts, about 7.1 a load, and 200 loads from the scratchpad took 204 counts.[^otl]

### Pulse Mode

In each of the modes 0010h, 0018h, 0030h and 0050h the first mode read showed bit 10 set, bit 10 then did not change in 448 reads, and the timer's I_STAT bit read 1. The reads came about 7.1 cycles apart. In mode 0058h bit 10 read 0 for single reads: reads 109, 218 and 363 on timers 0 and 1, and reads 109, 254 and 363 on timer 2.[^plw]

### 1F8010F8h and 1F8010FCh

1F8010FCh read 00FFFFFFh after every step. 1F8010F8h read 7FE72A23h as the group started and changed after the transfers on DMA4, DMA0, DMA1, DMA2, DMA5 and DMA6, but not after the second DMA0 transfer or the DMA4 read. Writing DPCR 07654321h, which turns every channel enable off, changed it from 3BE0ACE5h to 0BE0ACE5h, and writing DPCR back restored 3BE0ACE5h. DPCR written 00000000h and the four DICR writes left it at 3BE0ACE5h.[^f8c]

Table: 1F8010F8h after each step

| Step | 1F8010F8h |
| --- | --- |
| As found | 7FE72A23h |
| DMA4 write and read of 256 words | 7FEB0A63h |
| DMA0, 16 words | 7FEF1AA0h |
| DMA1, 16 words | 3FF32AC1h |
| DMA2 list of 16 empty nodes | 3FF33A0Ah |
| DMA4 write of 16 words | 3FF30A53h |
| DMA5, 1 word | 3BF41C9Ch |
| DMA6 OTC of 256 words | 3BE0ACE5h |

During a DMA6 OTC of 4096 words, a read straight after the CHCR write gave 3AE0ACE5h. A second read, after a read of MADR6, gave 3BE0ACE5h, and CHCR6 then read 00000002h.[^f8c]

### SPU Register 1DA0h

Read 256 times 1,000 cycles apart, 1DA0h read AC00h in runs of 2 to 15 reads with a read of 0100h between them. In three of the nine cases a read of A000h appeared once among the 24 runs printed. The pattern was the same with SPUCNT 0000h, 8000h and C000h and with voices keyed on or released. Written 0000h, 1DA0h read 0000h at the first read and then the same pattern, and written 0100h it read 0100h.[^uda]

### First Samples After Key On

At pitches 1000h, 0800h, 0400h and 0100h the first non-zero sample of the capture came at position 9. The first two non-zero samples were 06F8h and 0DF0h at pitch 1000h and 06F8h and 0DF1h at the other three pitches.[^gsn]

### MDEC Status After a Reset

At the end of the decode the status read 8404FFFFh for 24-bit output and 8604FFFFh for 15-bit output. After the reset it read 8404D7FBh at 6 counts with no NOP, 80000000h at 9 counts with 5 NOPs, and 80040000h at 24 counts or more with 20 or 100 NOPs. It read 80040000h 2,000 counts later in every case. In each case 19 strips came out and the wait after strip 20 ran out.[^mrt]

## Runs

### 5 October 2026

[followup29/00RUN.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup29/00RUN.txt)

```
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
7 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR 800225DC DCIC 00000000 BadVaddr 00000480 BDAM 00000000
BPCM 00000000 SR 00000000 Cause 00000020 EPC 80023190 PRId 00000002
```

[followup29/01HWT.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup29/01HWT.txt)

```
===== 01 HWT F29 HELD WRITE TIMED | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Row 45. Followup14 SRC with times: a RAM sh, one access, then a store linking node m (4, 8
or 16 on from the MADR read) to a side node. Each cell: 1 DMA2 took it, 0 it had passed m;
@ the node at the MADR read > the node at a second MADR read after the link store; then
timer 2 at the MADR read / after the link store, from the CHCR write. L0, L1; two runs.
no RAM sh, nothing: L0 1@34>36 383/403 1@34>36 384/404 1@34>36 384/404; L1 1@34>36 382/408 1@34>36 383/403 1@34>36 383/403; L0 1@33>35 377/397 1@33>35 377/397 1@33>35 377/397; L1 1@34>36 381/401 1@34>36 383/403 1@33>35 377/397;
RAM sh, RAM lw: L0 0@34>37 381/413 0@34>37 380/412 1@34>37 379/411; L1 0@34>37 383/415 0@34>37 383/421 1@34>37 389/421; L0 0@34>37 384/416 0@34>37 379/411 1@34>37 379/417; L1 0@34>37 379/411 0@34>37 383/421 1@34>37 389/421;
RAM sh, SPU KOFF sh 0: L0 0@34>37 379/417 0@34>37 385/418 1@34>37 380/413; L1 0@34>37 380/413 0@34>37 384/423 1@34>37 385/418; L0 0@33>36 377/410 0@34>37 379/412 1@34>37 379/418; L1 0@34>37 379/412 0@33>36 377/410 1@34>37 385/418;
RAM sh, 0 cached NOPs: L0 0@34>36 382/408 1@34>37 379/412 1@34>37 379/412; L1 1@34>37 383/416 1@34>37 379/412 1@33>36 377/410; L0 1@34>37 379/418 1@33>36 377/410 1@34>37 379/412; L1 1@34>37 385/418 1@34>37 381/414 1@34>37 383/416;
RAM sh, 4 cached NOPs: L0 1@34>37 385/418 1@34>37 385/418 1@33>36 377/410; L1 1@34>37 379/412 1@34>37 383/416 1@34>37 383/416; L0 1@33>36 377/410 1@34>37 385/418 1@33>36 377/410; L1 1@34>37 379/412 1@34>37 383/416 1@34>37 383/416;
RAM sh, 8 cached NOPs: L0 1@34>37 383/416 1@34>37 384/417 1@34>37 381/414; L1 1@34>37 389/422 1@34>37 379/412 1@34>37 383/416; L0 1@34>37 383/416 1@34>37 384/417 1@34>37 381/414; L1 1@34>37 389/422 1@34>37 379/412 1@34>37 383/416;
RAM sh, 16 cached NOPs: L0 0@34>38 380/423 1@34>38 379/428 1@34>38 381/424; L1 0@34>38 383/426 1@34>38 379/422 1@34>38 379/422; L0 0@33>37 377/420 1@34>38 379/422 1@34>38 380/423; L1 0@34>38 388/431 1@34>38 379/422 1@34>38 379/422;
Done.
```

[followup29/02OTL.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup29/02OTL.txt)

```
===== 02 OTL F29 OTC LOSSES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Row 81. 32 OTCs of 64 words in a row, each from timer 2 before the CHCR write to timer 2
after the poll that saw bit 24 clear; the second call of each routine (from the cache).
0 NOPs before the CHCR write: 96 86 96 86 86 90 86 96 86 86 88 86 96 86 86 88 86 96 86 86 88 86 96 86 86 88 86 96 86 86 88 86
  each start from the first: 0 110 210 320 420 520 624 724 834 934 1034 1136 1236 1346 1446 1546 1648 1748 1858 1958 2058 2160 2260 2370 2470 2570 2672 2772 2882 2982 3082 3184
1 NOPs before the CHCR write: 87 97 87 87 87 87 97 87 87 88 87 97 87 87 87 87 97 87 97 87 87 87 87 97 87 87 88 87 97 87 87 87
2 NOPs before the CHCR write: 87 97 87 87 88 87 97 87 87 87 87 97 87 97 87 87 87 87 97 87 87 87 87 97 87 87 87 87 97 87 97 87
3 NOPs before the CHCR write: 97 87 87 87 87 97 87 87 87 87 97 87 97 87 87 87 87 97 87 87 87 87 97 87 97 87 87 87 87 97 87 87
4 NOPs before the CHCR write: 87 97 87 97 87 87 87 87 97 87 87 87 87 97 87 97 87 87 88 87 97 87 97 87 87 87 87 97 87 87 87 87
5 NOPs before the CHCR write: 87 87 87 97 87 87 87 87 97 87 97 87 87 87 87 97 87 97 87 87 87 87 97 87 97 87 87 88 87 97 87 97
6 NOPs before the CHCR write: 87 87 87 87 97 87 97 87 87 87 87 97 87 97 87 87 87 87 97 87 97 87 87 87 87 97 87 97 87 87 87 87
7 NOPs before the CHCR write: 87 87 87 87 97 87 97 87 87 87 87 93 87 97 87 97 87 87 87 87 97 87 97 87 87 88 87 97 87 97 87 87
8 NOPs before the CHCR write: 87 87 87 97 87 97 87 97 87 87 87 87 97 87 97 87 87 87 87 97 87 97 87 97 87 87 87 87 97 87 97 87
9 NOPs before the CHCR write: 87 97 87 97 87 87 87 87 88 87 97 87 97 87 87 87 87 97 87 97 87 97 87 87 86 87 97 87 97 87 87 87
10 NOPs before the CHCR write: 97 87 97 87 87 87 87 97 87 97 87 97 87 87 87 87 97 87 97 87 97 87 87 87 87 89 87 97 87 97 87 87
11 NOPs before the CHCR write: 87 97 87 97 87 87 87 87 89 87 97 87 97 87 87 87 87 87 87 97 87 97 87 87 87 87 87 87 97 87 97 87
12 NOPs before the CHCR write: 87 97 87 97 87 87 87 87 87 87 97 87 97 87 97 87 87 87 87 90 87 97 87 97 87 97 87 87 87 87 97 87
13 NOPs before the CHCR write: 97 87 87 87 87 87 87 97 87 97 87 97 87 97 87 87 87 87 87 87 97 87 97 87 97 87 87 87 87 87 87 97
14 NOPs before the CHCR write: 97 87 87 87 87 87 87 97 87 97 87 97 87 97 87 87 87 87 87 87 97 87 97 87 97 87 97 87 87 87 87 87
15 NOPs before the CHCR write: 87 87 89 87 97 87 97 87 97 87 97 87 87 87 87 87 87 97 87 97 87 97 87 97 87 97 87 87 87 87 87 87
The table after the last OTC: right.
200 cached RAM lw, 16 turns, second call: 1428 1422 1426 1426 1422 1426 1422 1426 1426 1422 1426 1422 1426 1426 1422 1426
200 cached scratchpad lw, 16 turns, second call: 204 204 204 204 204 204 204 204 204 204 204 204 204 204 204 204
Done.
```

[followup29/03PLW.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup29/03PLW.txt)

```
===== 03 PLW F29 PULSE BIT 10 LOW | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Row 96. Pulse mode, system clock, target 0100h; 448 mode reads from the mode write
(timers.txt:26-36). Modes: 0010h one-shot, 0018h one-shot reset at target, 0030h one-shot
at target or FFFFh, 0050h repeat, 0058h repeat reset at target. read:bit 10.
T0 0010: 3192 cycles for 448 reads (7.12 each), I_STAT bit 4 1, first 0410; (0 changes)
T0 0018: 3192 cycles for 448 reads (7.12 each), I_STAT bit 4 1, first 0418; (0 changes)
T0 0030: 3192 cycles for 448 reads (7.12 each), I_STAT bit 4 1, first 0430; (0 changes)
T0 0050: 3192 cycles for 448 reads (7.12 each), I_STAT bit 4 1, first 0450; (0 changes)
T0 0058: 3193 cycles for 448 reads (7.12 each), I_STAT bit 4 1, first 0458; 109:0 110:1 218:0 219:1 363:0 364:1 (6 changes)
T1 0010: 3188 cycles for 448 reads (7.11 each), I_STAT bit 5 1, first 0410; (0 changes)
T1 0018: 3189 cycles for 448 reads (7.11 each), I_STAT bit 5 1, first 0418; (0 changes)
T1 0030: 3188 cycles for 448 reads (7.11 each), I_STAT bit 5 1, first 0430; (0 changes)
T1 0050: 3189 cycles for 448 reads (7.11 each), I_STAT bit 5 1, first 0450; (0 changes)
T1 0058: 3189 cycles for 448 reads (7.11 each), I_STAT bit 5 1, first 0458; 109:0 110:1 218:0 219:1 363:0 364:1 (6 changes)
T2 0010: 3190 cycles for 448 reads (7.12 each), I_STAT bit 6 1, first 0410; (0 changes)
T2 0018: 3190 cycles for 448 reads (7.12 each), I_STAT bit 6 1, first 0418; (0 changes)
T2 0030: 3190 cycles for 448 reads (7.12 each), I_STAT bit 6 1, first 0430; (0 changes)
T2 0050: 3190 cycles for 448 reads (7.12 each), I_STAT bit 6 1, first 0450; (0 changes)
T2 0058: 3190 cycles for 448 reads (7.12 each), I_STAT bit 6 1, first 0458; 109:0 110:1 254:0 255:1 363:0 364:1 (6 changes)
Done.
```

[followup29/04F8C.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup29/04F8C.txt)

```
===== 04 F8C F29 1F8010F8 BY CHANNEL | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Row 59. 1F8010F8h and 1F8010FCh (dma/channels.txt:132-141) by lw after each step.
As the group starts, before anything here: F8 7FE72A23 FC 00FFFFFF
The image at 28000h uploaded and read back: 0 halfwords of 512 differ.
After the SPU set up (DMA4 write and read of 256 words): F8 7FEB0A63 FC 00FFFFFF
After DMA0, a quant table of 16 words: F8 7FEF1AA0 FC 00FFFFFF
After DMA0, a scale table of 32 words: F8 7FEF1AA0 FC 00FFFFFF
DMA0 done, DMA1 done.
After DMA1, 16 words of one 8 bit block (and DMA0's 32 words): F8 3FF32AC1 FC 00FFFFFF
After a DMA2 list of 16 empty nodes: F8 3FF33A0A FC 00FFFFFF
After a DMA4 write of 16 words: F8 3FF30A53 FC 00FFFFFF
After a DMA4 read of 16 words: F8 3FF30A53 FC 00FFFFFF
After DMA5, 1 word with bit 28: F8 3BF41C9C FC 00FFFFFF
After a DMA6 OTC of 256 words: F8 3BE0ACE5 FC 00FFFFFF
A DMA6 OTC of 4096 words, read straight after its CHCR write: F8 3AE0ACE5, MADR6 00123C7C, F8
3BE0ACE5, CHCR6 00000002
After it: F8 3BE0ACE5 FC 00FFFFFF
DPCR written its own value: F8 3BE0ACE5 FC 00FFFFFF
DPCR written 00000000: F8 3BE0ACE5 FC 00FFFFFF
DPCR written 07654321 (every enable off): F8 0BE0ACE5 FC 00FFFFFF
DPCR written back: F8 3BE0ACE5 FC 00FFFFFF
DICR written 00000000: F8 3BE0ACE5 FC 00FFFFFF
DICR written 007F0000 (enables, no master): F8 3BE0ACE5 FC 00FFFFFF
DICR written 00800000 (master alone): F8 3BE0ACE5 FC 00FFFFFF
DICR written back, flags acknowledged: F8 3BE0ACE5 FC 00FFFFFF
Done.
```

[followup29/05UDA.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup29/05UDA.txt)

```
===== 05 UDA F29 SPU 1DA0 AND 1E60 | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Row 89. 1E60h-1E7Fh as this group finds them (after the BIOS, the runner and the groups
before; a program cannot run before the BIOS card screen's first SPU write): F5FF F3EF BFFF 29DF 74BB FFFE BFF7 FFFF FFFF FD7D 6EFF 33B3 FC7F FFFF BFFF 7D8F
1DA0h read 256 times 1000 cycles apart, value or value x count, in order.
As found, nothing written: 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x15 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 (57 runs, 24 shown)
The image at 28000h uploaded and read back: 0 halfwords of 512 differ.
SPUCNT 8000h, every voice released: AC00x2 0100 AC00x8 0100 AC00x15 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 (55 runs, 24 shown)
SPUCNT C000h, released: AC00x4 0100 AC00x15 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x15 0100 AC00x8 0100 (55 runs, 24 shown)
SPUCNT 0000h, released: AC00x2 0100 AC00x6 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x6 A000 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 (59 runs, 24 shown)
SPUCNT 8000h, voices 1 and 3 keyed: AC00x2 0100 AC00x8 0100 AC00x6 A000 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x6 0100 AC00x8 0100 AC00x8 0100 (59 runs, 24 shown)
SPUCNT C000h, keyed: AC00x8 0100 AC00x15 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 (53 runs, 24 shown)
SPUCNT 0000h, keyed before: 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 (58 runs, 24 shown)
1DA0h written 0000h, SPUCNT 8000h, keyed: 0000 AC00x2 A000 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 (58 runs, 24 shown)
1DA0h written 0000h, SPUCNT 8000h, released: 0000 0100 AC00x6 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 AC00x8 0100 (59 runs, 24 shown)
1DA0h written back 0100: reads 0100.
Done.
```

[followup29/06GSN.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup29/06GSN.txt)

```
===== 06 GSN F29 GAUSS AT KEY ON | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
The image at 28000h uploaded and read back: 0 halfwords of 512 differ.
Row 90. Voice 1 plays 1000h, 2000h, 4000h, 7000h (7 samples each), then 7FFFh, at
each pitch; the capture from the key on (spx:272) and the level register (+0Ch).
Pitch 1000; level at the key on 7FFF, at each half 0000 0000 0000 0000.
 first non-zero at 9; from 7:
  0000x2 06F8 0DF0 0FED 124E 1D85 1FDEx5 24A0 3B0D 3FBFx4 3FBE 46E1 687D 6F87x5 71E7 7D1C
  7F75x45 0000x944
Pitch 0800; level at the key on 7FFF, at each half 0000 0000 0000 0000.
 first non-zero at 9; from 7:
  0000x2 06F8 0DF1 0FED 0FEE 0FED 0FEE 0FED 1023 124E 17ED 1D85 1FAB 1FDEx6 1FDCx3 2046
  249E 2FD8 3B09 3F53 3FBB 3FBA 3FBB 3FBA 3FBB 3FBA 3FBB 3FBAx2 4059 46DD 57B4 687D
  6EEC 6F87x9 6FBB 71E7 7783 7D1C 7F41 7F75 7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75
  7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75
  7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75
  7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75
  7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75
  7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75 7F74 7F75
  0000x872
Pitch 0400; level at the key on 7FFF, at each half 7FF7 0000 0000 0000.
 first non-zero at 9; from 7:
  0000x2 06F8 0DF1 0FED 0FEEx3 0FED 0FEEx3 0FED 0FEEx3 0FED 0FF3 1023 10CE 124D 14C8 17EC
  1B0E 1D83 1F01 1FA9 1FD8 1FDCx17 1FE6 2046 219C 249E 2992 2FD8 361E 3B09 3E04 3F53
  3FB2 3FBBx2 3FBA 3FBBx3 3FBA 3FBBx3 3FBA 3FBBx3 3FBA 3FBB 3FBA 3FC9 4059 425A 46DD 4E49
  57B4 611C 687D 6CF5 6EEC 6F7A 6F87x3 6F88 6F87x3 6F88 6F87x3 6F88 6F87x3 6F88 6F87 6F8C
  6FBB 7067 71E7 7460 7783 7AA7 7D1C 7E99 7F41 7F71 7F75 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2
  7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2
  7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2
  7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2
  7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2
  7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2 7F75x2 7F74x2
  7F75x2 7F74x2 7F75x2 0000x728
Pitch 0100; level at the key on 7FFF, at each half 7FF7 7FF7 7FF7 7FF7.
 first non-zero at 9; from 7:
  0000x2 06F8 0DF1 0FEEx10 0FED 0FEE 0FED 0FEEx3 0FEDx10 0FEC 0FED 0FEC 0FEDx13 0FEC 0FED 0FEC
  0FEDx13 0FEC 0FED 0FEC 0FEDx2 0FEF 0FF2 0FF8 1001 100E 1022 103D 1062 1091 10CD 1116
  116D 11D6 124D 12D6 136E 1414 14C8 1587 164E 171B 17EC 18BC 1989 1A50 1B0E 1BC1
  1C66 1CFC 1D83 1DFA 1E61 1EB8 1F01 1F3C 1F6A 1F8E 1FA9 1FBC 1FC9 1FD2 1FD8 1FDBx2
  1FDCx6 1FDD 1FDCx7 1FDD 1FDCx7 1FDD 1FDCx7 1FDD 1FDCx7 1FDD 1FDCx7 1FDD 1FDCx7 1FDD 1FDCx7 1FDD
  1FDCx4 1FDD 1FE0 1FE6 1FF2 2003 201F 2046 207D 20C6 2124 219C 222E 22DE 23AE 249E
  25AE 26DE 282A 2992 2B0E 2C9D 2E38 2FD8 3179 3314 34A1 361E 3783 38CE 39FA 3B09
  3BF7 3CC5 3D73 3E04 3E79 3ED6 3F1E 3F53 3F7A 3F95 3FA6 3FB2 3FB7 3FBAx2 3FBBx3 3FBA
  3FBBx4 3FBAx2 3FBB 3FBA 3FBBx3 3FBA 3FBBx3 3FBA 3FBBx4 3FBAx2 3FBB 3FBA 3FBBx3 3FBA 3FBBx3 3FBA
  3FBBx4 3FBAx2 3FBB 3FBA 3FBBx3 3FBA 3FBBx3 3FBA 3FBBx4 3FBAx2 3FBB 3FBA 3FBBx3 3FBAx2 3FBB 3FBC
  3FC0 3FC9 3FDA 3FF5 401E 4059 40AB 4119 41A6 425A 4335 443D 4574 46DD 4874 4A3B
  4C2E 4E49 5085 52DB 5544 57B4 5A25 5C8D 5EE1 611C 6334 6523 66E7 687D 69E2 6B16
  6C1B 6CF5 6DA5 6E30 6E9C 6EEC 6F26 6F4F (cut at 200 entries, output 338)
Done.
```

[followup29/07MRT.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup29/07MRT.txt)

```
===== 07 MRT F29 MDEC STATUS AFTER RESET | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Row 67. Followup19 PIO's frame, then MDEC1 80000000h and the status n NOPs after it
(status@timer 2 cycles from the mode write before the reset store). Stream CRC A4FD5107 (as packed).
24 bit, 0 NOPs: 19 strips, the wait after strip 20 word 2880 gave up; table waits that gave up 0
  at the end 8404FFFF; after the reset 8404D7FB@6; 2000 on 80040000
24 bit, 5 NOPs: 19 strips, the wait after strip 20 word 2880 gave up; table waits that gave up 0
  at the end 8404FFFF; after the reset 80000000@9; 2000 on 80040000
24 bit, 20 NOPs: 19 strips, the wait after strip 20 word 2880 gave up; table waits that gave up 0
  at the end 8404FFFF; after the reset 80040000@24; 2000 on 80040000
24 bit, 100 NOPs: 19 strips, the wait after strip 20 word 2880 gave up; table waits that gave up 0
  at the end 8404FFFF; after the reset 80040000@104; 2000 on 80040000
24 bit, 5, 20 and 100 NOPs in one run: 19 strips, the wait after strip 20 word 2880 gave up; table waits that gave up 0
  at the end 8404FFFF; after the reset 80000000@9 80040000@36 80040000@128; 2000 on 80040000
15 bit, 5, 20 and 100 NOPs in one run: 19 strips, the wait after strip 20 word 1920 gave up; table waits that gave up 0
  at the end 8604FFFF; after the reset 80000000@9 80040000@36 80040000@128; 2000 on 80040000
Done.
```

## References

[^run]: SCPH-5501 output: [followup29/00RUN.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup29/00RUN.txt)
[^otl]: SCPH-5501 output: [followup29/02OTL.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup29/02OTL.txt)
[^plw]: SCPH-5501 output: [followup29/03PLW.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup29/03PLW.txt)
[^f8c]: SCPH-5501 output: [followup29/04F8C.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup29/04F8C.txt)
[^uda]: SCPH-5501 output: [followup29/05UDA.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup29/05UDA.txt)
[^gsn]: SCPH-5501 output: [followup29/06GSN.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup29/06GSN.txt)
[^mrt]: SCPH-5501 output: [followup29/07MRT.txt](/tests/raw/20261005T0000Z-5501a-card-q/followup29/07MRT.txt)