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---
title: Root Counter Clocks and Sync Modes
type: test
summary: Measures what each root counter counts over fixed delays and frames for each clock source and sync mode.
category: Hardware tests
info: Machine = SCPH-5501
info: Program = timers (ps1-tests)
---

## Overview

The program reads each [root counter](/hardware/timers/) after a delay loop of 1000 and of 5000 cycles and after one video frame, ten times each, with every clock source the counter has. It then runs each sync mode ten times without resetting the counter between readings: timer 0 at each horizontal resolution on the 33.8688 MHz clock and on the dot clock, timer 1 on the 33.8688 MHz clock and on horizontal blank, and timer 2 on the 33.8688 MHz clock.[^src]

Last it sets timer 2's target to 10 with reset at target and counts how often each value 0 to 11 is read. It also writes the mode register and reads it back around a target hit.[^src]

## Results

All three counters on the 33.8688 MHz clock read 1011 after the 1000-cycle delay and 5011 after the 5000-cycle delay in every reading. Over one frame they read 106,570 to 107,366.[^run]

Table: Counter reading by clock source (run of 25 September 2026)

| Counter and clock | 1000-cycle delay | 5000-cycle delay | One frame |
| --- | --- | --- | --- |
| Timer 0, system clock | 1011 | 5011 | 106,570 to 107,359 |
| Timer 0, dot clock | 199 to 201 | 991 to 992 | 111,951 to 112,033 |
| Timer 1, system clock | 1011 | 5011 | 106,925 to 107,366 |
| Timer 1, horizontal blank | 0 to 1 | 2 to 3 | 263 |
| Timer 2, system clock | 1011 | 5011 | 106,919 to 107,358 |
| Timer 2, system clock / 8 | 126 to 127 | 626 to 627 | 70,708 to 70,763 |

Timer 1 counted 263 horizontal blanks in every frame. Timer 2 at one eighth of the clock gave 126 or 127 for the 1000-cycle delay.[^run]

Timer 2 in sync modes 0 and 3 stayed at 0 for all ten readings, and in sync modes 1 and 2 it counted freely: 240, 362 and on in steps of 122. Timer 1 on the 33.8688 MHz clock in sync modes 2 and 3 also stayed at 0.[^run]

Timer 0 in sync mode 1 (reset at each horizontal blank) dropped back to a small value partway through its readings at every resolution except 512. In sync mode 3 it read 0 for one or more readings and then counted freely, and at some resolutions it read 0 in all ten. In sync mode 2 it read 0 in most readings and counted only inside a horizontal blank.[^run]

With target 10 and reset at target, timer 2 read every value from 0 to 10 and never 11. The counter reset after it reached the target, and it never reached FFFFh.[^run]

A write of 0000h to timer 0's mode register read back 0400h, and a write of FFFFh read back 07FFh. After the counter reached its target the mode read 1C08h, and a second read gave 0408h: the first read cleared bits 11 and 12. A write of the mode after the target hit gave the same pair of reads.[^run]

## Runs

### 25 September 2026

[11TMR.txt](/tests/raw/20260925T0000Z-5501a-card-main/main/11TMR.txt)

```
===== 11 TMR TIMERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
timers test
Detected NTSC system.

Forced NTSC system.
Timer0, clock:   System clock, 1000 cycles delay:   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011, 
Timer0, clock:   System clock, 5000 cycles delay:   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011, 
Timer0, clock:   System clock,       frame delay: 106570, 107323, 107359, 107321, 107348, 107305, 107330, 107352, 107316, 107346, 
Timer0, clock:      Dot clock, 1000 cycles delay:    200,    200,    199,    200,    200,    201,    200,    200,    200,    200, 
Timer0, clock:      Dot clock, 5000 cycles delay:    992,    992,    991,    992,    992,    991,    992,    992,    991,    991, 
Timer0, clock:      Dot clock,       frame delay: 111951, 112027, 112031, 112031, 112032, 112029, 112028, 112031, 112028, 112033, 
Timer1, clock:   System clock, 1000 cycles delay:   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011, 
Timer1, clock:   System clock, 5000 cycles delay:   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011, 
Timer1, clock:   System clock,       frame delay: 106925, 107332, 107354, 107316, 107339, 107319, 107366, 107325, 107306, 107359, 
Timer1, clock:         Hblank, 1000 cycles delay:      1,      0,      1,      0,      1,      0,      1,      0,      1,      0, 
Timer1, clock:         Hblank, 5000 cycles delay:      3,      2,      2,      3,      2,      2,      3,      2,      2,      3, 
Timer1, clock:         Hblank,       frame delay:    263,    263,    263,    263,    263,    263,    263,    263,    263,    263, 
Timer2, clock:   System clock, 1000 cycles delay:   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011, 
Timer2, clock:   System clock, 5000 cycles delay:   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011, 
Timer2, clock:   System clock,       frame delay: 106919, 107319, 107346, 107319, 107358, 107345, 107329, 107305, 107354, 107323, 
Timer2, clock: System clock/8, 1000 cycles delay:    126,    127,    126,    126,    127,    126,    127,    126,    126,    127, 
Timer2, clock: System clock/8, 5000 cycles delay:    626,    627,    626,    626,    627,    626,    627,    626,    626,    627, 
Timer2, clock: System clock/8,       frame delay:  70708,  70761,  70758,  70759,  70763,  70758,  70762,  70756,  70760,  70762, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                311,    433,    555,    677,    799,    921,   1043,   1165,   1287,   1409, 
1 = Reset counter to 0 at Hblanks                               198,    320,    442,    564,    686,    808,    930,   1052,   1174,   1296, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank   240,    362,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,     19,    141, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                285,    407,    529,    651,    773,    895,   1002,   1002,   1002,   1002, 
1 = Reset counter to 0 at Hblanks                               240,    362,     77,    199,    321,    443,    565,    687,    809,    931, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                285,    407,    529,    651,    715,    715,    715,    715,    803,    925, 
1 = Reset counter to 0 at Hblanks                               240,    362,    484,     31,    153,    275,    397,    519,    641,    763, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                285,    407,    529,    651,    773,    895,   1017,   1139,   1261,   1344, 
1 = Reset counter to 0 at Hblanks                               235,    357,    479,    601,    723,    845,    967,   1089,   1211,   1333, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank   240,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,     89,    211,    333,    455,    577,    699, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                  0,     13,    135,    257,    379,    501,    623,    745,    867,    989, 
1 = Reset counter to 0 at Hblanks                               240,    362,    484,    606,    728,    850,    972,   1094,   1216,    107, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 42,     61,     81,    100,    119,    139,    158,    177,    197,    216, 
1 = Reset counter to 0 at Hblanks                                37,     57,     76,     95,    115,    134,     16,     36,     55,     74, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,     12,     31,     50,     70,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 56,     81,     85,     85,     85,     85,     95,    119,    143,    167, 
1 = Reset counter to 0 at Hblanks                                47,     71,     95,    119,      5,     29,     54,     78,    102,    126, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank    42,     66,     90,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      5,     29,     53, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 64,     92,    120,    147,    175,    202,    230,    258,    285,    313, 
1 = Reset counter to 0 at Hblanks                                54,     82,    109,    136,    164,      9,     36,     64,     92,    119, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      7,     34,     62,     89,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run      50,     78,    105,    133,    161,    188,    216,    244,    271,    299, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 67,    106,    145,    184,    222,    261,    300,    338,    377,    416, 
1 = Reset counter to 0 at Hblanks                                75,    114,    153,    191,    230,    269,    307,    346,    384,    423, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,     27,     65,    104,    142,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                113,    161,    210,    258,    289,    289,    289,    289,    289,    334, 
1 = Reset counter to 0 at Hblanks                                94,    143,     43,     91,    140,    188,    236,    285,    333,    381, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,     22,     70,    118,    167, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,     32,     81,    129,    178,    226,    274,    323, 

Testing Timer1 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs)
0 = Pause counter during Vblanks                                285,    407,    529,    651,    773,    895,   1017,   1139,   1261,   1383, 
1 = Reset counter to 0 at Vblanks                               240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Reset counter to 0 at Vblanks and pause outside of Vblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Vblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer1 sync modes (clock source = Hblank, 100 delay cycles, not resetted between runs)
0 = Pause counter during Vblanks                                  1,      1,      1,      1,      1,      1,      1,      1,      1,      1, 
1 = Reset counter to 0 at Vblanks                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      1, 
2 = Reset counter to 0 at Vblanks and pause outside of Vblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Vblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs)
0 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
1 = Free Run                                                    240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Free Run                                                    240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
3 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs)
0 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
1 = Free Run                                                    239,    361,    483,    605,    727,    849,    971,   1093,   1215,   1337, 
2 = Free Run                                                    239,    361,    483,    605,    727,    849,    971,   1093,   1215,   1337, 
3 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Check when Timer2 counter (System clock) is reset when reaching target (= 10).
counter ==  0,  1665 ticks  
counter ==  1,   835 ticks  
counter ==  2,   833 ticks  
counter ==  3,   831 ticks  
counter ==  4,   836 ticks  
counter ==  5,   834 ticks  
counter ==  6,   831 ticks  
counter ==  7,   835 ticks  
counter ==  8,   834 ticks  
counter ==  9,   831 ticks  
counter == 10,   835 ticks  <<<< This value should be non-zero
counter == 11,     0 ticks  
Reached target:                      1 (ok)
Reached 0xFFFF:                      0 (ok)
Counter reset AFTER reaching target: 1 (ok)
Target + 1 not reached:              1 (ok)


Check if write to mode register acknowledges the targetReached flag
Write 0x0000 to Timer0.mode, read 0x0400
Write 0xffff to Timer0.mode, read 0x07ff

Read mode after waiting for targetReached: 0x1c08
Read again: 0x0408

Write mode after waiting for targetReached and then read: 0x1c08
Read again: 0x0408


Done.
```

### 27 September 2026

[11TMR.txt](/tests/raw/20260927T0000Z-5501a-card-2/main/s024/11TMR.txt)

```
===== 11 TMR TIMERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
timers test
Detected NTSC system.

Forced NTSC system.
Timer0, clock:   System clock, 1000 cycles delay:   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011, 
Timer0, clock:   System clock, 5000 cycles delay:   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011, 
Timer0, clock:   System clock,       frame delay: 106456, 107368, 107325, 107349, 107335, 107363, 107359, 107329, 107341, 107335, 
Timer0, clock:      Dot clock, 1000 cycles delay:    200,    200,    201,    200,    200,    201,    200,    200,    199,    200, 
Timer0, clock:      Dot clock, 5000 cycles delay:    991,    992,    992,    991,    992,    992,    991,    992,    992,    991, 
Timer0, clock:      Dot clock,       frame delay: 111937, 112029, 112035, 112027, 112036, 112036, 112031, 112034, 112032, 112031, 
Timer1, clock:   System clock, 1000 cycles delay:   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011, 
Timer1, clock:   System clock, 5000 cycles delay:   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011, 
Timer1, clock:   System clock,       frame delay: 106859, 107349, 107343, 107335, 107371, 107320, 107357, 107344, 107335, 107371, 
Timer1, clock:         Hblank, 1000 cycles delay:      0,      1,      0,      1,      0,      1,      0,      0,      0,      0, 
Timer1, clock:         Hblank, 5000 cycles delay:      2,      2,      2,      2,      3,      2,      2,      3,      2,      2, 
Timer1, clock:         Hblank,       frame delay:    263,    263,    263,    263,    263,    263,    263,    263,    263,    263, 
Timer2, clock:   System clock, 1000 cycles delay:   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011, 
Timer2, clock:   System clock, 5000 cycles delay:   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011, 
Timer2, clock:   System clock,       frame delay: 106836, 107364, 107341, 107328, 107389, 107313, 107363, 107333, 107339, 107379, 
Timer2, clock: System clock/8, 1000 cycles delay:    126,    127,    126,    126,    127,    126,    126,    127,    126,    127, 
Timer2, clock: System clock/8, 5000 cycles delay:    626,    626,    627,    626,    627,    626,    626,    627,    626,    626, 
Timer2, clock: System clock/8,       frame delay:  70700,  70761,  70763,  70762,  70760,  70761,  70761,  70763,  70764,  70759, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                304,    426,    548,    604,    604,    604,    604,    619,    741,    863, 
1 = Reset counter to 0 at Hblanks                               240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,     41,    163,    285, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                290,    327,    327,    327,    327,    361,    483,    605,    727,    849, 
1 = Reset counter to 0 at Hblanks                               254,     85,    207,    329,    451,    573,    695,    817,    939,   1061, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,     13,    135,    257,    379, 
3 = Pause until Hblank occurs once, then switch to Free Run      22,    144,    266,    388,    510,    632,    754,    876,    998,   1120, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                294,    416,    538,    660,    782,    904,    972,    972,    972,    972, 
1 = Reset counter to 0 at Hblanks                               240,     15,    137,    259,    381,    503,    625,    747,    869,    991, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,     55,    177,    299,    421, 
3 = Pause until Hblank occurs once, then switch to Free Run     193,    315,    437,    559,    681,    803,    925,   1047,   1169,   1291, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 68,    190,    312,    434,    556,    678,    800,    922,   1044,   1166, 
1 = Reset counter to 0 at Hblanks                               240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,     11,    133,    255,    377,    499,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,     61,    183,    305,    427,    549,    671,    793,    915, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                122,    244,    366,    488,    610,    732,    854,    976,   1098,   1220, 
1 = Reset counter to 0 at Hblanks                               240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 46,     49,     49,     49,     49,     57,     76,     95,    115,    134, 
1 = Reset counter to 0 at Hblanks                                38,     58,     77,     96,    116,    135,    154,    174,    193,    212, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank    37,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 59,     84,    108,    132,    156,    180,    204,    229,    253,    277, 
1 = Reset counter to 0 at Hblanks                                 6,     31,     55,     79,    103,    127,    151,    176,    200,    224, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank    47,     72,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 66,     94,    121,    149,    177,    204,    232,    234,    234,    234, 
1 = Reset counter to 0 at Hblanks                                54,     82,    110,    137,    165,    193,    220,    248,    276,    303, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     2,     29,     57,     84,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,     24, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 24,     24,     24,     34,     73,    112,    151,    189,    228,    267, 
1 = Reset counter to 0 at Hblanks                                76,    114,    153,     31,     69,    108,    147,    185,    224,    263, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,     36,     74,    113,    151,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                119,    167,    215,    264,    312,    360,    409,    457,    505,    544, 
1 = Reset counter to 0 at Hblanks                                94,    143,    191,     35,     84,    132,    180,    229,    277,    325, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,     44,     92,    140,    189,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer1 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs)
0 = Pause counter during Vblanks                                285,    407,    529,    651,    773,    895,   1017,   1139,   1261,   1383, 
1 = Reset counter to 0 at Vblanks                               240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Reset counter to 0 at Vblanks and pause outside of Vblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Vblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer1 sync modes (clock source = Hblank, 100 delay cycles, not resetted between runs)
0 = Pause counter during Vblanks                                  0,      0,      0,      0,      0,      0,      0,      0,      0,      1, 
1 = Reset counter to 0 at Vblanks                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
2 = Reset counter to 0 at Vblanks and pause outside of Vblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Vblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs)
0 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
1 = Free Run                                                    240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Free Run                                                    254,    376,    498,    620,    742,    864,    986,   1108,   1230,   1352, 
3 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs)
0 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
1 = Free Run                                                    239,    361,    483,    605,    727,    849,    971,   1093,   1215,   1337, 
2 = Free Run                                                    239,    361,    483,    605,    727,    849,    971,   1093,   1215,   1337, 
3 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Check when Timer2 counter (System clock) is reset when reaching target (= 10).
counter ==  0,  1665 ticks  
counter ==  1,   835 ticks  
counter ==  2,   831 ticks  
counter ==  3,   834 ticks  
counter ==  4,   836 ticks  
counter ==  5,   831 ticks  
counter ==  6,   834 ticks  
counter ==  7,   835 ticks  
counter ==  8,   831 ticks  
counter ==  9,   834 ticks  
counter == 10,   834 ticks  <<<< This value should be non-zero
counter == 11,     0 ticks  
Reached target:                      1 (ok)
Reached 0xFFFF:                      0 (ok)
Counter reset AFTER reaching target: 1 (ok)
Target + 1 not reached:              1 (ok)


Check if write to mode register acknowledges the targetReached flag
Write 0x0000 to Timer0.mode, read 0x0400
Write 0xffff to Timer0.mode, read 0x07ff

Read mode after waiting for targetReached: 0x1c08
Read again: 0x0408

Write mode after waiting for targetReached and then read: 0x1c08
Read again: 0x0408


Done.
```

### 27 September 2026 run 2

[11TMR.txt](/tests/raw/20260927T0000Z-5501a-card-b/main/s034/11TMR.txt)

```
===== 11 TMR TIMERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
timers test
Detected NTSC system.

Forced NTSC system.
Timer0, clock:   System clock, 1000 cycles delay:   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011, 
Timer0, clock:   System clock, 5000 cycles delay:   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011, 
Timer0, clock:   System clock,       frame delay: 106459, 107363, 107335, 107352, 107339, 107326, 107354, 107343, 107349, 107339, 
Timer0, clock:      Dot clock, 1000 cycles delay:    200,    200,    201,    200,    201,    200,    200,    200,    199,    200, 
Timer0, clock:      Dot clock, 5000 cycles delay:    991,    992,    992,    991,    992,    992,    991,    991,    992,    992, 
Timer0, clock:      Dot clock,       frame delay: 111936, 112032, 112033, 112032, 112035, 112028, 112035, 112032, 112033, 112035, 
Timer1, clock:   System clock, 1000 cycles delay:   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011, 
Timer1, clock:   System clock, 5000 cycles delay:   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011, 
Timer1, clock:   System clock,       frame delay: 106867, 107340, 107347, 107347, 107334, 107359, 107340, 107369, 107325, 107333, 
Timer1, clock:         Hblank, 1000 cycles delay:      0,      1,      0,      1,      0,      1,      0,      0,      1,      0, 
Timer1, clock:         Hblank, 5000 cycles delay:      2,      2,      3,      2,      2,      2,      2,      3,      2,      2, 
Timer1, clock:         Hblank,       frame delay:    263,    263,    263,    263,    263,    263,    263,    263,    263,    263, 
Timer2, clock:   System clock, 1000 cycles delay:   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011, 
Timer2, clock:   System clock, 5000 cycles delay:   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011, 
Timer2, clock:   System clock,       frame delay: 106861, 107329, 107341, 107335, 107363, 107359, 107329, 107358, 107317, 107364, 
Timer2, clock: System clock/8, 1000 cycles delay:    126,    126,    127,    126,    126,    127,    126,    127,    126,    126, 
Timer2, clock: System clock/8, 5000 cycles delay:    627,    626,    626,    627,    626,    627,    626,    626,    627,    626, 
Timer2, clock: System clock/8,       frame delay:  70704,  70762,  70760,  70761,  70763,  70761,  70762,  70761,  70760,  70764, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                306,    428,    550,    562,    562,    562,    562,    621,    743,    865, 
1 = Reset counter to 0 at Hblanks                               240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,    114,    236,    358, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                290,    412,    450,    450,    450,    450,    483,    605,    727,    849, 
1 = Reset counter to 0 at Hblanks                               254,    376,     49,    171,    293,    415,    537,    659,    781,    903, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,     52,    174,    296,    418,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run     169,    291,    413,    535,    657,    779,    901,   1023,   1145,   1267, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                300,    422,    544,    666,    788,    910,   1032,   1154,   1276,   1398, 
1 = Reset counter to 0 at Hblanks                               240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,      0,     72,    194, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 65,    187,    309,    431,    553,    675,    797,    919,   1041,   1163, 
1 = Reset counter to 0 at Hblanks                               240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,     28,    150,    272,    394,    516, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,     70,    192,    314,    436,    558,    680,    802, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                285,    407,    529,    651,    773,    895,   1017,   1139,   1261,   1383, 
1 = Reset counter to 0 at Hblanks                               240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 35,     35,     35,     35,     36,     55,     74,     94,    113,    132, 
1 = Reset counter to 0 at Hblanks                                38,     57,     77,     96,    115,    135,    154,    173,    193,    212, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 59,     83,    107,    131,    156,    180,    204,    228,    245,    245, 
1 = Reset counter to 0 at Hblanks                                48,     72,     96,    120,    144,    168,    193,    217,    241,    265, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank    47,     71,     95,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      5,     29,     53,     77,    102,    126,    150,    174,    198, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 67,     86,     86,     86,     86,    101,    129,    156,    184,    211, 
1 = Reset counter to 0 at Hblanks                                55,     82,    109,    137,     19,     46,     74,    101,    129,    157, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      1,     28,     56,     84,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      3, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                  0,      0,     31,     69,    108,    147,    186,    224,    263,    302, 
1 = Reset counter to 0 at Hblanks                                67,    106,    144,    183,    222,    260,    299,    338,    376,    415, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,     14,     52,     91,    130,    168,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                118,    167,    215,    263,    312,    360,    408,    457,    505,    553, 
1 = Reset counter to 0 at Hblanks                                95,    143,    191,     17,     65,    114,    162,    210,    259,    307, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,     32,     81,    129,    177,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer1 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs)
0 = Pause counter during Vblanks                                285,    407,    529,    651,    773,    895,   1017,   1139,   1261,   1383, 
1 = Reset counter to 0 at Vblanks                               240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Reset counter to 0 at Vblanks and pause outside of Vblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Vblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer1 sync modes (clock source = Hblank, 100 delay cycles, not resetted between runs)
0 = Pause counter during Vblanks                                  0,      0,      0,      0,      0,      0,      0,      0,      0,      1, 
1 = Reset counter to 0 at Vblanks                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
2 = Reset counter to 0 at Vblanks and pause outside of Vblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Vblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs)
0 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
1 = Free Run                                                    240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Free Run                                                    254,    376,    498,    620,    742,    864,    986,   1108,   1230,   1352, 
3 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs)
0 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
1 = Free Run                                                    239,    361,    483,    605,    727,    849,    971,   1093,   1215,   1337, 
2 = Free Run                                                    239,    361,    483,    605,    727,    849,    971,   1093,   1215,   1337, 
3 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Check when Timer2 counter (System clock) is reset when reaching target (= 10).
counter ==  0,  1665 ticks  
counter ==  1,   834 ticks  
counter ==  2,   831 ticks  
counter ==  3,   834 ticks  
counter ==  4,   837 ticks  
counter ==  5,   831 ticks  
counter ==  6,   834 ticks  
counter ==  7,   835 ticks  
counter ==  8,   831 ticks  
counter ==  9,   834 ticks  
counter == 10,   834 ticks  <<<< This value should be non-zero
counter == 11,     0 ticks  
Reached target:                      1 (ok)
Reached 0xFFFF:                      0 (ok)
Counter reset AFTER reaching target: 1 (ok)
Target + 1 not reached:              1 (ok)


Check if write to mode register acknowledges the targetReached flag
Write 0x0000 to Timer0.mode, read 0x0400
Write 0xffff to Timer0.mode, read 0x07ff

Read mode after waiting for targetReached: 0x1c08
Read again: 0x0408

Write mode after waiting for targetReached and then read: 0x1c08
Read again: 0x0408


Done.
```

### 27 September 2026 run 3

[11TMR.txt](/tests/raw/20260927T0000Z-5501a-card-g/main/11TMR.txt)

```
===== 11 TMR TIMERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
timers test
Detected NTSC system.

Forced NTSC system.
Timer0, clock:   System clock, 1000 cycles delay:   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011, 
Timer0, clock:   System clock, 5000 cycles delay:   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011, 
Timer0, clock:   System clock,       frame delay: 106459, 107363, 107335, 107352, 107339, 107355, 107325, 107343, 107349, 107339, 
Timer0, clock:      Dot clock, 1000 cycles delay:    200,    199,    200,    200,    200,    200,    201,    201,    200,    200, 
Timer0, clock:      Dot clock, 5000 cycles delay:    991,    992,    992,    991,    992,    992,    992,    992,    992,    991, 
Timer0, clock:      Dot clock,       frame delay: 111935, 112035, 112032, 112033, 112035, 112029, 112036, 112031, 112038, 112029, 
Timer1, clock:   System clock, 1000 cycles delay:   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011, 
Timer1, clock:   System clock, 5000 cycles delay:   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011, 
Timer1, clock:   System clock,       frame delay: 106859, 107349, 107369, 107325, 107349, 107335, 107350, 107368, 107332, 107342, 
Timer1, clock:         Hblank, 1000 cycles delay:      0,      1,      0,      1,      0,      1,      0,      0,      1,      0, 
Timer1, clock:         Hblank, 5000 cycles delay:      2,      2,      3,      2,      2,      2,      2,      3,      2,      2, 
Timer1, clock:         Hblank,       frame delay:    263,    263,    263,    263,    263,    263,    263,    263,    263,    263, 
Timer2, clock:   System clock, 1000 cycles delay:   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011, 
Timer2, clock:   System clock, 5000 cycles delay:   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011, 
Timer2, clock:   System clock,       frame delay: 106869, 107339, 107349, 107343, 107335, 107371, 107320, 107357, 107344, 107335, 
Timer2, clock: System clock/8, 1000 cycles delay:    126,    126,    127,    126,    126,    127,    126,    127,    126,    126, 
Timer2, clock: System clock/8, 5000 cycles delay:    627,    626,    626,    627,    626,    627,    626,    626,    627,    626, 
Timer2, clock: System clock/8,       frame delay:  70701,  70766,  70757,  70762,  70763,  70758,  70766,  70757,  70763,  70761, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                306,    428,    550,    572,    572,    572,    572,    622,    744,    866, 
1 = Reset counter to 0 at Hblanks                               240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,    105,    227,    349, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                290,    412,    459,    459,    459,    459,    483,    605,    727,    849, 
1 = Reset counter to 0 at Hblanks                               254,    376,     39,    161,    283,    405,    527,    649,    771,    893, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,     42,    164,    286,    408,    530, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,     58,    180,    302,    424,    546,    668,    790, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                294,    416,    538,    660,    782,    904,   1026,   1148,   1270,   1392, 
1 = Reset counter to 0 at Hblanks                               240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,      0,      0,     79, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,     45,    167,    289, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                299,    421,    519,    519,    519,    519,    519,    614,    736,    858, 
1 = Reset counter to 0 at Hblanks                               240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,      0,      0,    115, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                285,    407,    529,    651,    773,    895,   1017,   1139,   1151,   1151, 
1 = Reset counter to 0 at Hblanks                               240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,    118,    240, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 45,     65,     84,    103,    123,    142,    158,    158,    158,    158, 
1 = Reset counter to 0 at Hblanks                                38,     57,     77,     96,    115,    135,    154,    173,    193,    212, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 59,     83,    107,    131,    155,    180,    204,    214,    214,    214, 
1 = Reset counter to 0 at Hblanks                                48,     72,     96,    120,    145,    169,    193,    217,    241,    265, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank    47,     71,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run      39,     63,     87,    111,    136,    160,    184,    208,    232,    256, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 68,     95,    123,    151,    178,    206,    233,    252,    252,    252, 
1 = Reset counter to 0 at Hblanks                                54,     82,    109,    137,    164,    192,    220,    247,    275,    303, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     6,     33,     60,     88,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      8,     35, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                  0,      0,      4,     42,     81,    120,    158,    197,    236,    274, 
1 = Reset counter to 0 at Hblanks                                76,    115,    154,    192,    231,    270,    308,    347,    386,    424, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank    25,     63,    102,    140,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      6, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                120,    168,    216,    265,    313,    361,    369,    369,    369,    369, 
1 = Reset counter to 0 at Hblanks                                95,    143,    191,    240,    288,    336,    385,    433,    481,    530, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,     24,     72,    121,    169,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer1 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs)
0 = Pause counter during Vblanks                                285,    407,    529,    651,    773,    895,   1017,   1139,   1261,   1383, 
1 = Reset counter to 0 at Vblanks                               240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Reset counter to 0 at Vblanks and pause outside of Vblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Vblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer1 sync modes (clock source = Hblank, 100 delay cycles, not resetted between runs)
0 = Pause counter during Vblanks                                  0,      0,      0,      0,      0,      0,      0,      0,      1,      1, 
1 = Reset counter to 0 at Vblanks                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
2 = Reset counter to 0 at Vblanks and pause outside of Vblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Vblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs)
0 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
1 = Free Run                                                    240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Free Run                                                    254,    376,    498,    620,    742,    864,    986,   1108,   1230,   1352, 
3 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs)
0 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
1 = Free Run                                                    239,    361,    483,    605,    727,    849,    971,   1093,   1215,   1337, 
2 = Free Run                                                    239,    361,    483,    605,    727,    849,    971,   1093,   1215,   1337, 
3 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Check when Timer2 counter (System clock) is reset when reaching target (= 10).
counter ==  0,  1665 ticks  
counter ==  1,   836 ticks  
counter ==  2,   833 ticks  
counter ==  3,   831 ticks  
counter ==  4,   837 ticks  
counter ==  5,   833 ticks  
counter ==  6,   831 ticks  
counter ==  7,   835 ticks  
counter ==  8,   833 ticks  
counter ==  9,   831 ticks  
counter == 10,   835 ticks  <<<< This value should be non-zero
counter == 11,     0 ticks  
Reached target:                      1 (ok)
Reached 0xFFFF:                      0 (ok)
Counter reset AFTER reaching target: 1 (ok)
Target + 1 not reached:              1 (ok)


Check if write to mode register acknowledges the targetReached flag
Write 0x0000 to Timer0.mode, read 0x0400
Write 0xffff to Timer0.mode, read 0x07ff

Read mode after waiting for targetReached: 0x1c08
Read again: 0x0408

Write mode after waiting for targetReached and then read: 0x1c08
Read again: 0x0408


Done.
```

### 27 September 2026 run 4

[11TMR.txt](/tests/raw/20260927T0000Z-5501a-card-g3/main/11TMR.txt)

```
===== 11 TMR TIMERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
timers test
Detected NTSC system.

Forced NTSC system.
Timer0, clock:   System clock, 1000 cycles delay:   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011, 
Timer0, clock:   System clock, 5000 cycles delay:   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011, 
Timer0, clock:   System clock,       frame delay: 106394, 107338, 107349, 107364, 107330, 107336, 107348, 107344, 107358, 107328, 
Timer0, clock:      Dot clock, 1000 cycles delay:    199,    200,    200,    201,    200,    201,    200,    200,    200,    200, 
Timer0, clock:      Dot clock, 5000 cycles delay:    991,    991,    992,    992,    992,    992,    992,    992,    991,    991, 
Timer0, clock:      Dot clock,       frame delay: 111934, 112031, 112037, 112029, 112030, 112033, 112032, 112038, 112028, 112033, 
Timer1, clock:   System clock, 1000 cycles delay:   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011, 
Timer1, clock:   System clock, 5000 cycles delay:   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011, 
Timer1, clock:   System clock,       frame delay: 106819, 107374, 107318, 107349, 107335, 107351, 107349, 107326, 107366, 107335, 
Timer1, clock:         Hblank, 1000 cycles delay:      1,      0,      1,      0,      1,      0,      1,      0,      1,      0, 
Timer1, clock:         Hblank, 5000 cycles delay:      3,      2,      2,      3,      2,      2,      3,      2,      2,      3, 
Timer1, clock:         Hblank,       frame delay:    263,    263,    263,    263,    263,    263,    263,    263,    263,    263, 
Timer2, clock:   System clock, 1000 cycles delay:   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011, 
Timer2, clock:   System clock, 5000 cycles delay:   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011, 
Timer2, clock:   System clock,       frame delay: 106837, 107323, 107358, 107337, 107347, 107352, 107332, 107359, 107337, 107347, 
Timer2, clock: System clock/8, 1000 cycles delay:    126,    126,    127,    126,    127,    126,    126,    127,    126,    126, 
Timer2, clock: System clock/8, 5000 cycles delay:    626,    627,    626,    627,    626,    626,    627,    626,    626,    627, 
Timer2, clock: System clock/8,       frame delay:  70701,  70759,  70762,  70764,  70759,  70763,  70759,  70764,  70760,  70761, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                216,    338,    460,    582,    704,    826,    948,   1070,   1192,   1314, 
1 = Reset counter to 0 at Hblanks                               240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                275,    397,    519,    641,    763,    885,    974,    974,    974,    974, 
1 = Reset counter to 0 at Hblanks                               240,    362,    484,    606,     42,    164,    286,    408,    530,    652, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,     97,    219,    341,    463,    585,    707,    829, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                  0,    120,    242,    364,    486,    608,    730,    852,    974,   1096, 
1 = Reset counter to 0 at Hblanks                               240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,    111,    233,    355, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,     60,    182,    304,    426,    548,    670,    792,    914,   1036, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                282,    404,    468,    468,    468,    468,    476,    598,    720,    842, 
1 = Reset counter to 0 at Hblanks                                62,    184,    306,    428,    550,    672,    794,    916,   1038,   1160, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank   254,    376,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,     44,    166,    288, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                282,    404,    526,    648,    660,    660,    660,    660,    719,    841, 
1 = Reset counter to 0 at Hblanks                               240,      2,    124,    246,    368,    490,    612,    734,    856,    978, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,     67,    189,    311, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,     97,    219,    341,    463,    585,    707,    829,    951,   1073, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 45,     64,     84,    103,    122,    142,    161,    180,    200,    219, 
1 = Reset counter to 0 at Hblanks                                38,     57,     76,     95,      4,     23,     42,     62,     81,    101, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,     15,     34,     53,     72,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 55,     79,    103,    127,    151,    175,    200,    224,    248,    272, 
1 = Reset counter to 0 at Hblanks                                47,     71,     95,    119,    143,      6,     30,     54,     78,    102, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,     17,     40,     64,     89,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 62,     89,    117,    145,    172,    200,    228,    255,    283,    310, 
1 = Reset counter to 0 at Hblanks                                57,     85,    113,    140,    168,    196,    223,    251,    278,    306, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank    36,     63,     91,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,     24,     51,     79, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 89,    128,    166,    205,    244,    282,    321,    333,    333,    333, 
1 = Reset counter to 0 at Hblanks                                75,    114,    152,    191,     37,     75,    114,    153,    191,    230, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,      7,     45,     84, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 81,     81,     81,     81,     94,    142,    190,    239,    287,    335, 
1 = Reset counter to 0 at Hblanks                                95,    143,    191,    240,    288,    336,      3,     51,     99,    148, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,     13,     61,    109, 
3 = Pause until Hblank occurs once, then switch to Free Run      48,     97,    145,    193,    242,    290,    338,    387,    435,    483, 

Testing Timer1 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs)
0 = Pause counter during Vblanks                                270,    392,    514,    636,    758,    880,   1002,   1124,   1246,   1368, 
1 = Reset counter to 0 at Vblanks                               240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Reset counter to 0 at Vblanks and pause outside of Vblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Vblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer1 sync modes (clock source = Hblank, 100 delay cycles, not resetted between runs)
0 = Pause counter during Vblanks                                  0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
1 = Reset counter to 0 at Vblanks                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
2 = Reset counter to 0 at Vblanks and pause outside of Vblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Vblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs)
0 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
1 = Free Run                                                    240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Free Run                                                    240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
3 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs)
0 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
1 = Free Run                                                    239,    361,    483,    605,    727,    849,    971,   1093,   1215,   1337, 
2 = Free Run                                                    239,    361,    483,    605,    727,    849,    971,   1093,   1215,   1337, 
3 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Check when Timer2 counter (System clock) is reset when reaching target (= 10).
counter ==  0,  1667 ticks  
counter ==  1,   833 ticks  
counter ==  2,   831 ticks  
counter ==  3,   837 ticks  
counter ==  4,   833 ticks  
counter ==  5,   831 ticks  
counter ==  6,   836 ticks  
counter ==  7,   832 ticks  
counter ==  8,   831 ticks  
counter ==  9,   836 ticks  
counter == 10,   833 ticks  <<<< This value should be non-zero
counter == 11,     0 ticks  
Reached target:                      1 (ok)
Reached 0xFFFF:                      0 (ok)
Counter reset AFTER reaching target: 1 (ok)
Target + 1 not reached:              1 (ok)


Check if write to mode register acknowledges the targetReached flag
Write 0x0000 to Timer0.mode, read 0x0400
Write 0xffff to Timer0.mode, read 0x07ff

Read mode after waiting for targetReached: 0x1c08
Read again: 0x0408

Write mode after waiting for targetReached and then read: 0x1c08
Read again: 0x0408


Done.
```

### 28 September 2026

[11TMR.txt](/tests/raw/20260928T0000Z-5501a-card-h/main/11TMR.txt)

```
===== 11 TMR TIMERS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
timers test
Detected NTSC system.

Forced NTSC system.
Timer0, clock:   System clock, 1000 cycles delay:   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011, 
Timer0, clock:   System clock, 5000 cycles delay:   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011, 
Timer0, clock:   System clock,       frame delay: 106416, 107338, 107338, 107375, 107330, 107336, 107338, 107349, 107364, 107330, 
Timer0, clock:      Dot clock, 1000 cycles delay:    200,    200,    200,    200,    199,    200,    200,    201,    200,    201, 
Timer0, clock:      Dot clock, 5000 cycles delay:    992,    992,    991,    991,    992,    992,    991,    992,    992,    991, 
Timer0, clock:      Dot clock,       frame delay: 111934, 112033, 112035, 112030, 112031, 112033, 112033, 112035, 112030, 112030, 
Timer1, clock:   System clock, 1000 cycles delay:   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011, 
Timer1, clock:   System clock, 5000 cycles delay:   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011, 
Timer1, clock:   System clock,       frame delay: 106828, 107364, 107330, 107336, 107348, 107344, 107358, 107331, 107336, 107348, 
Timer1, clock:         Hblank, 1000 cycles delay:      1,      0,      1,      0,      1,      0,      1,      0,      1,      0, 
Timer1, clock:         Hblank, 5000 cycles delay:      3,      2,      2,      3,      2,      2,      3,      2,      2,      3, 
Timer1, clock:         Hblank,       frame delay:    263,    263,    263,    263,    263,    263,    263,    263,    263,    263, 
Timer2, clock:   System clock, 1000 cycles delay:   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011,   1011, 
Timer2, clock:   System clock, 5000 cycles delay:   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011,   5011, 
Timer2, clock:   System clock,       frame delay: 106823, 107332, 107349, 107339, 107363, 107328, 107332, 107349, 107339, 107363, 
Timer2, clock: System clock/8, 1000 cycles delay:    126,    126,    127,    126,    127,    126,    126,    127,    126,    126, 
Timer2, clock: System clock/8, 5000 cycles delay:    626,    627,    626,    627,    626,    626,    627,    626,    626,    627, 
Timer2, clock: System clock/8,       frame delay:  70698,  70762,  70760,  70765,  70758,  70762,  70760,  70760,  70765,  70758, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                148,    270,    392,    514,    636,    758,    880,   1002,   1124,   1246, 
1 = Reset counter to 0 at Hblanks                               240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                275,    397,    519,    641,    763,    885,    984,    984,    984,    984, 
1 = Reset counter to 0 at Hblanks                               240,    362,    484,    606,      3,    125,    247,    369,    491,    613, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,     63,    185,    307,    429,    551,    673,    795,    917,   1039, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                270,    392,    505,    505,    505,    505,    544,    666,    788,    910, 
1 = Reset counter to 0 at Hblanks                                86,    208,    330,    452,    574,    696,    818,    940,   1062,   1184, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                282,    404,    526,    648,    656,    656,    656,    656,    719,    841, 
1 = Reset counter to 0 at Hblanks                               240,    362,    117,    239,    361,    483,    605,    727,    849,    971, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank   254,    376,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,    117,    239, 

Testing Timer0 sync modes (clock source = System clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                282,    404,    496,    496,    496,    496,    496,    597,    719,    841, 
1 = Reset counter to 0 at Hblanks                               240,    111,    233,    355,    477,    599,    721,    843,    965,   1087, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 256x240, dotclock @ 5.32224 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                  6,     25,     45,     64,     83,    103,    122,    141,    161,    180, 
1 = Reset counter to 0 at Hblanks                                40,     59,     79,     98,    117,    137,    156,    175,      4,     23, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,     19,     38,     57,     77, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 320x240, dotclock @ 6.65280 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 25,     49,     73,     97,    121,    145,    170,    194,    218,    242, 
1 = Reset counter to 0 at Hblanks                                48,     71,     95,    120,      5,     29,     53,     77,    101,    126, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     7,     31,     55,     79,    103,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 368x240, dotclock @ 7.60320 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 61,     89,    116,    144,    172,    199,    227,    255,    282,    310, 
1 = Reset counter to 0 at Hblanks                                57,     85,    112,    140,    168,    195,    223,    250,    278,    305, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank    54,     81,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      8,     35,     63,     90,    118,    146, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 512x240, dotclock @ 10.64448 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 89,    128,    166,    205,    244,    282,    321,    360,    399,    437, 
1 = Reset counter to 0 at Hblanks                                76,    115,    153,    192,    230,    269,    308,    346,     37,     76, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer0 sync modes (clock source = Dot clock, 100 delay cycles, resolution = 640x240, dotclock @ 13.30560 MHz, not resetted between runs)
0 = Pause counter during Hblanks                                 80,     80,     80,     80,     92,    140,    188,    237,    285,    333, 
1 = Reset counter to 0 at Hblanks                                95,    143,    192,    240,    288,    337,    385,     30,     79,    127, 
2 = Reset counter to 0 at Hblanks and pause outside of Hblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Hblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer1 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs)
0 = Pause counter during Vblanks                                270,    392,    514,    636,    758,    880,   1002,   1124,   1246,   1368, 
1 = Reset counter to 0 at Vblanks                               240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Reset counter to 0 at Vblanks and pause outside of Vblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Vblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer1 sync modes (clock source = Hblank, 100 delay cycles, not resetted between runs)
0 = Pause counter during Vblanks                                  0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
1 = Reset counter to 0 at Vblanks                                 0,      1,      1,      1,      1,      1,      1,      1,      1,      1, 
2 = Reset counter to 0 at Vblanks and pause outside of Vblank     0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
3 = Pause until Vblank occurs once, then switch to Free Run       0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs)
0 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
1 = Free Run                                                    240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
2 = Free Run                                                    240,    362,    484,    606,    728,    850,    972,   1094,   1216,   1338, 
3 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Testing Timer2 sync modes (clock source = System clock, 100 delay cycles, not resetted between runs)
0 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 
1 = Free Run                                                    239,    361,    483,    605,    727,    849,    971,   1093,   1215,   1337, 
2 = Free Run                                                    239,    361,    483,    605,    727,    849,    971,   1093,   1215,   1337, 
3 = Stop counter at current value                                 0,      0,      0,      0,      0,      0,      0,      0,      0,      0, 

Check when Timer2 counter (System clock) is reset when reaching target (= 10).
counter ==  0,  1665 ticks  
counter ==  1,   834 ticks  
counter ==  2,   831 ticks  
counter ==  3,   835 ticks  
counter ==  4,   834 ticks  
counter ==  5,   832 ticks  
counter ==  6,   834 ticks  
counter ==  7,   834 ticks  
counter ==  8,   832 ticks  
counter ==  9,   834 ticks  
counter == 10,   835 ticks  <<<< This value should be non-zero
counter == 11,     0 ticks  
Reached target:                      1 (ok)
Reached 0xFFFF:                      0 (ok)
Counter reset AFTER reaching target: 1 (ok)
Target + 1 not reached:              1 (ok)


Check if write to mode register acknowledges the targetReached flag
Write 0x0000 to Timer0.mode, read 0x0400
Write 0xffff to Timer0.mode, read 0x07ff

Read mode after waiting for targetReached: 0x1c08
Read again: 0x0408

Write mode after waiting for targetReached and then read: 0x1c08
Read again: 0x0408


Done.
```

## References

[^src]: ps1-tests, timers. https://github.com/JaCzekanski/ps1-tests.
[^run]: SCPH-5501 output: [main/11TMR.txt](/tests/raw/20260925T0000Z-5501a-card-main/main/11TMR.txt) and the files beside it, with the other runs listed under Runs.