Central Processing Unit (CPU)

32-bit RISC processor at the center of the PlayStation.

This is an old revision of this page, as edited by RemmyLee at 02:22, 23 October 2026. Edit this revision | Latest revision

Overview

The PlayStation uses a customized CPU based on the R3000A. The R3000A is a 32-bit RISC CPU.¹

The CPU contains an instruction cache (I-cache) and a scratchpad memory. Main memory and an interrupt controller surround the CPU at the base of the PlayStation.²

The GTE (Geometry Transformation Engine) is a coprocessor of the CPU.²

The CPU has the following specifications:

Memory

The PlayStation has 2 MB of main memory.¹

The R3000 TLB (the virtual memory management device) is not present. The relation between physical and logical addresses is therefore fixed.¹

The OS ROM is 512KB. It holds the OS kernel and the boot loader.¹

The memory map page lists the address ranges.

I-Cache

The I-cache holds 1K words (4K bytes) and is 1-way mapped. Logical space is divided into 4K-byte units that map onto the I-cache.³

The top 4 bits of a logical address decide whether the I-cache is used.⁴

The I-cache is used in segments A, B, P and Q. It is not used in segments C and R.⁴

The I-cache is divided into 256 lines of 16 bytes. One line holds 4 instructions.⁵

Each line has a tag. The tag records whether the line holds instructions and stores the upper 20 bits of their address.⁵

Bits 5 to 12 of the instruction address select the line. A hit takes 1 cycle.⁵

Scratchpad

The D-cache of the PlayStation is called the Scratch Pad. Its size is 1KB.¹

The D-cache is a high-speed memory inside the CPU.³

The scratchpad is mapped into memory as segment S. Data and programs can both be stored there.³

The scratchpad reads and writes once per cycle. It cannot be the target of a DMA transfer.⁶

Write and Read Buffers

The R-buffer is a single 4-byte register that buffers read data.⁵

A load from memory into the R-buffer takes 4 cycles. A read from the R-buffer to the CPU takes 1 cycle.⁵

The W-buffer is a FIFO of 4 registers of 4 bytes each. Each write takes one register. The length of the write does not matter.⁵

A write to the W-buffer takes 1 cycle. A write from the W-buffer to main memory takes 4 cycles.⁵

When the W-buffer is full, a write waits until a register is freed.⁵

A read from an address with a pending write waits for the write to complete. The read then gets the newest data.⁵

Neither buffer can be accessed by bytes or halfwords.⁵

The CPU manages the cache and the buffers. A program cannot control them.⁶

The exact cycle count of a code segment therefore cannot be predicted.⁶

Access Timing

The access timing from the CPU to main memory is as follows:

Address Alignment

The R3000 requires strict address alignment. Word data starts at a multiple of 4 and halfword data at a multiple of 2.³

A data load, data store or instruction fetch that breaks this rule causes an address error.³

Registers

The R3000 has 32 general-purpose registers of 32 bits. The compiler assigns each register a use.³

The macros in the table are defined in asm.h.³

The assembler uses AT as a work area. C code and assembler programmers may not use it.⁷

The R3000 has no subroutine call. A jump instruction holds the return address in a register. The compiler always uses RA for it.⁷

A C function receives its first 4 arguments in A0 to A3. Further arguments go on the stack.⁷

The stack is a pointer kept in SP by the compiler. FP holds the head address of the function frame.⁸

The compiler groups up to 64K bytes of variables in the bss section.⁸

GP holds the center address of the bss section. One instruction reaches any variable in it.⁸

Program Counter

The program counter cannot be accessed directly. It takes the following values:

Exceptions

An error such as a bus error or a reserved instruction raises an exception.⁸

On an exception the CPU jumps to 0x00000080. A device interrupt jumps to the same address.⁸

An exception cannot be masked.⁸

References