Interrupt Controller

Interrupt status and mask registers and the interrupt sources of the PlayStation.

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Summary

The interrupt controller collects the interrupt requests of the PlayStation devices in two registers. I_STAT holds the requests and I_MASK selects which of them reach the CPU. Both registers may be written with 16-bit stores.¹²

Table 1: Interrupt control registers
Address	Name	Content
1F801070h	I_STAT	Interrupt status register (read = status, write = acknowledge)
1F801074h	I_MASK	Interrupt mask register (R/W)

A bit of I_STAT reads 1 while its interrupt is requested. Writing 0 to the bit clears it and writing 1 leaves it unchanged, so a program acknowledges one interrupt without touching the others. A 1 in I_MASK enables the interrupt.¹

Interrupt Sources

I_STAT and I_MASK share the following bit layout:¹

Table 2: Interrupt bits
Bit	Name	Source
0	IRQ0 VBLANK	Vertical blank (PAL 50 Hz, NTSC 60 Hz)
1	IRQ1 GPU	GPU, requested with the GP0(1Fh) command (rarely used)
2	IRQ2 CDROM	CD-ROM controller
3	IRQ3 DMA	DMA controller
4	IRQ4 TMR0	Timer 0 (system clock or dot clock)
5	IRQ5 TMR1	Timer 1 (system clock or H-blank)
6	IRQ6 TMR2	Timer 2 (system clock or system clock / 8)
7	IRQ7	Controller and Memory Card byte received
8	IRQ8 SIO	Serial port
9	IRQ9 SPU	SPU
10	IRQ10	Controller lightpen, shared with PIO and DTL boards
11 to 15		Not used (always zero)
16 to 31		Garbage

The DTL-H2000 has a secondary controller for IRQ10 at 1F802030h.¹

Request and Execution

The bits of I_STAT are edge triggered, and a bit is set only when its source changes from false to true. While (I_STAT AND I_MASK) is nonzero the CPU sees bit 10 of the COP0 CAUSE register set. The interrupt is then taken if bit 10 and bit 0 of the COP0 SR register are also set.¹

COP0 has six hardware interrupt bits, but the PlayStation uses only CAUSE bit 10 and bits 11 to 15 always read zero. CAUSE bit 10 is not a latch. It clears itself when (I_STAT AND I_MASK) becomes zero, and COP0 therefore needs no acknowledge. CAUSE bits 8 and 9 are software interrupts that a program sets and clears by itself.³

The COP0 page describes the exception that follows.

Acknowledge

An interrupt is acknowledged by writing 0 to its bit in I_STAT. IRQ0, IRQ4, IRQ5 and IRQ6 need nothing more. Every other interrupt must also be acknowledged at the device that raised it (for example SIO0_CR bit 4).¹

The order matters because the bits are edge triggered. I_STAT must be acknowledged first and the device second. In the reverse order the device can raise a new request within one cycle, so I_STAT never sees a new edge and the bit is never set again.¹

Kernel Handling

When an interrupt or exception occurs, the kernel saves the registers in the execution TCB as the main flow context. Execution then begins at 0x00000080, which holds a jump to the kernel interrupt dispatcher. The dispatcher calls the routine for the interrupt, and when the routine completes the kernel restores the main flow context and resumes it.⁴

Event handlers and callbacks both run in this interrupt context. Event handlers use the 4K interrupt stack that the kernel keeps in its reserved memory, while callbacks use the callback stack declared in libetc.⁴⁵

Critical Sections

Any function that modifies data within the kernel must run with interrupts inhibited, and such a section of code is called a critical section. Interrupts are inhibited at the following times:⁴

Table 3: Times when interrupts are inhibited
Time	Re-enabled by
Immediately after system start	ResetCallbacks()
After EnterCriticalSection()	ExitCriticalSection()
At the start of an event handler	ReturnFromException() or ExitCriticalSection()

A root counter interrupt therefore cannot occur within a critical section.⁵

Cause Descriptors

The kernel names each interrupt source with a cause descriptor and an event type. A program passes both to OpenEvent() to install an event handler for the source. The kernel library defines the following descriptors, and the other libraries define further event types for HwCdRom.⁶

Table 4: Cause descriptors
Cause descriptor	Contents	Event type
RCntCNT0 to RCntCNT3	Root counter interrupt	EvSpINT
HwCdRom	CD-ROM decoder interrupt	EvSpUNKNOWN
HwSPU	SPU interrupt	EvSpTRAP
HwGPU	GPU interrupt	EvSpTRAP
HWPIO	Extension parallel port interrupt	EvSpTRAP
HwSIO	Extension serial port interrupt	EvSpTRAP
HwCPU	Exceptions	EvSpTRAP

Cautions in Interrupt Context

A routine in interrupt context should complete in the shortest possible time, because halting interrupts for a long time may adversely affect the PlayStation. ReturnFromException() in an event handler returns to the main flow but cuts off the interrupt dispatcher, which may make devices malfunction. Sony therefore limits it to error handling.⁴

The following are prohibited in interrupt context:⁷

Table 5: Prohibitions in interrupt context
Prohibited	Reason
Functions that use internal interrupts	The interrupt is never generated, so the function cannot complete
Non-re-entrant functions the main flow may call	Most library functions and kernel services are not re-entrant
ReturnFromException() in a callback	Prohibited

References

^ ^a ^b ^c ^d ^e ^f ^g psx-spx. Interrupts, 1F801070h I_STAT and 1F801074h I_MASK. https://psx-spx.consoledev.net/interrupts/
^ psx-spx. Unpredictable Things, I/O Write Datasize. https://psx-spx.consoledev.net/unpredictablethings/
^ psx-spx. Interrupts, PSX specific COP0 Notes. https://psx-spx.consoledev.net/interrupts/
^ ^a ^b ^c ^d Sony Computer Entertainment Inc. Run-Time Library Overview. January 1999. Page 2-6.
^ ^a ^b Sony Computer Entertainment Inc. Run-Time Library Overview. January 1999. Page 2-9.
^ Sony Computer Entertainment Inc. Run-Time Library Overview. January 1999. Page 2-10, Table 2-12.
^ Sony Computer Entertainment Inc. Run-Time Library Overview. January 1999. Page 2-7.

Categories: Hardware