Root Counters

Three 16-bit hardware timers and the vertical sync counter of the PlayStation.

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Summary

The root counters are timers that count automatically. Sony provides them for time limits and timing adjustments, which game programs need. A counter counts up from zero, and when it reaches its target value it generates an interrupt, clears to zero and starts again. Each interrupt can be masked.¹

Sony's libraries name four root counters. RCntCNT0 to RCntCNT2 are 16-bit hardware timers with registers at 1F801100h, 1F801110h and 1F801120h. The table below shows all four. RCntCNT3 counts vertical synchronization, and its target value is fixed at 1, so it generates an interrupt at each vertical blank.¹²

The Notes column is Sony's. psx-spx documents no timer registers for the vertical sync counter. The vertical blank reaches the CPU as IRQ0 in I_STAT, while the three hardware timers raise IRQ4, IRQ5 and IRQ6.¹³⁴

Registers

Each hardware timer has three registers at its base address. Official names for the registers and bits are in timerman.h of Sony's PlayStation 2 IOP SDK, which psx-spx follows. The PlayStation libraries call the third register TARGET.²

COUNT - Current Value

Bits 0 to 15 hold the current counter value and bits 16 to 31 are garbage. The counter increments by itself and may be written with any value. It is reset to 0000h on every write to MODE and when it reaches its reset condition, which is either FFFFh or the target value.⁵

A current value written above the target value does not match the target on the way up. The counter therefore runs to FFFFh, wraps to 0000h once and only then uses the target value.⁵

MODE - Counter Mode

MODE selects the synchronization, reset point, interrupt conditions and clock source of a counter:⁶

The meaning of GATM depends on the counter. Timer 0 synchronizes to H-blank and timer 1 to V-blank with the same four modes, while timer 2 has only two behaviors:⁶

In one-shot mode the interrupt is pulsed or toggled only once. The counter keeps counting, but further interrupts are suppressed until MODE is written again. If both CMP and OVFL are set, one-shot mode triggers only the condition that occurs first.⁶

Pulse mode is the normal setting. INTF then stays 1 except for a few clock cycles at each interrupt. In toggle mode INTF is set by the write to MODE and inverts at each interrupt, so in repeat mode IRQ4 to IRQ6 occur only on every second match, when INTF changes from 1 to 0.⁶

COMP - Target Value

Bits 0 to 15 hold the target value and bits 16 to 31 are garbage. With ZRET set the counter counts up to and including the target value and then restarts at 0000h.⁷

Reset and Wrap Timing

A counter reset by a write to MODE stays at 0000h for 2 clock cycles before it counts. A written current value likewise stays for 2 cycles before the counter counts or checks the target. A wrap at FFFFh holds 0000h for only 1 cycle, but a reset at the target value holds 0000h for 2 cycles.⁸

With a target of 0001h and ZRET set the counter therefore repeats the sequence 0000h 0000h 0001h.⁸

Clock Sources and Counter Timing

One system clock tick is about 0.03 microseconds. The display counters run at the timings below:⁹

The pixel display period depends on the display width through N:⁹

The GPU dot clock and H-blank are not synchronized with the CPU clock, so the counter may change during the CPU read cycle. A program should therefore read the counter repeatedly until two reads give the same value or the second is slightly larger.¹⁰

Library Modes

The kernel library sets the counters with mode macros combined by logical OR. RCntMdINTR permits the interrupt and RCntMdNOINTR prohibits it, which leaves polling as the only method.⁹

RCntMdFR, the default, counts normally. RCntMdGATE makes the counter count only while its gate condition holds:⁹¹¹

The counters count in hardware, so StopRCnt() does not stop a count. StopRCnt() only stops the counter from generating interrupts, and StartRCnt() only permits them.⁹

Use by the Kernel

All counters are stopped or free running immediately after the kernel starts, and a program must therefore initialize a counter before it uses one. The kernel itself uses root counter 3 (vertical blanking) to read the controller buttons. The button state cannot be read while root counter 3 is stopped or uninitialized.¹¹

The beginning of the vertical blanking period can be detected with root counter 3 and the event management service. The PS-X OS manual gives this sequence:¹²

EnterCriticalSection();
EV = OpenEvent(RCntCNT3, EvSpINT, EvMdNOINTR, NULL);
EnableEvent(EV);
SetRCnt(RCntCNT3, 1, RCntMdINTR);
StartRCnt(RCntCNT3);
while (1) {
    WaitEvent(EV);
}

References