CPU Pipeline Timing and Cache Isolation
Measures CPU store and load sequences, uncached instruction fetch, I/O register upper halves, an interrupt taken on a GTE command, and isolated cache reads.
| Machine | SCPH-5501 |
|---|---|
| Program | followup15, followup15g |
This is an old revision of this page, as edited by RemmyLee at 05:40, 23 October 2026. Edit this revision | Latest revision
Overview
Each timing row runs 100 turns of a short sequence built in RAM and run warm from the instruction cache, or from KSEG1 where the row says so. Root counter 2 counts system clock cycles for the whole call, the setup included, and no DMA runs. The other groups read register values: the upper half of RAM_SIZE and I_MASK after a store, two root counter 1 reads in a row, the exception PC when an interrupt lands on RTPS, and loads with the cache isolated.1
| Tag | Rows |
|---|---|
| SNL | A RAM store, n instructions, a RAM or scratchpad load |
| IOA | An I/O register load, n NOPs, a second load |
| LDL | A RAM load, p NOPs, one access on the cycle the data lands |
| BKB | Two RAM loads with a backward branch path between them |
| KLU | A load and a use of its value, run from KSEG1 |
| KSJ | Two stores, k NOPs and a jump or branch, run from KSEG1 |
| UFP | A store that zeroes root counter 2, n NOPs, a read of the counter |
| BBL | 2 to 6 loads back to back |
| MFL | The upper half of RAM_SIZE after an I_MASK store before a cache line fill |
| IMU | The upper half of I_MASK after a store and one other access |
| TIO | Two root counter 1 loads back to back |
| PLC | GP0 stores and polling loops |
| IGT | A root counter 2 interrupt at target n onto a cached RTPS |
| IS2 | Isolated loads after a routine has run from the cache |
| IS4 | An isolated load and store from cached code |
The second program, followup15g, repeats IGT with root counter 2 read before the RTPS and at the handler's entry, and then with a NOP in place of the RTPS.2
See also:
- Store and Load Sequences
- CPU Load and Store Timing
- Load Landing and Device Loads
- CPU Bus Gaps and Cache Isolation
- Write Queue and GTE Interrupts
- GTE Timing during CPU Stalls
Results
Stores and Loads
A RAM load placed 3 to 5 instructions after a RAM store took 1,475 to 1,480 cycles for 100 turns. From 6 instructions on, each further NOP added about 100 cycles, and SB, SH and SW gave the same times. A scratchpad load after the store took 955 cycles at n 3, and every NOP added 100. Through a taken backward BEQ path in place of the NOPs the rise came one instruction earlier: 1,478 to 1,480 cycles at n 4 and 1,562 at n 5.1
| n | RAM load | Scratchpad load |
|---|---|---|
| 3 | 1,475 | 955 |
| 5 | 1,478 | 1,155 |
| 6 | 1,567 | 1,259 |
| 7 | 1,665 | 1,355 |
| 9 | 1,875 | 1,555 |
A load of I_STAT, GPUSTAT, DPCR or root counter 2 followed at once by a second load of the same register took 1,155 or 1,156 cycles. With 1 to 3 NOPs between them the time rose to 1,355 cycles. With 4 NOPs it rose to 1,455 to 1,459. The same register made no difference.1
When the second load went to RAM or the scratchpad, the time rose in the same steps from a different start. With a RAM load as the second load the rows took 1,276 cycles with no NOP between the loads. They took 1,469 to 1,480 with 1 to 3 NOPs and 1,558 to 1,572 with 4. With a scratchpad load as the second load the rows took 955 cycles with no NOP and 1,155 to 1,160 with 1 to 3 NOPs. They took 1,255 with 4.1
In the LDL rows a RAM load is followed by p NOPs and one access. A store or a scratchpad load as that access took about 1,478 cycles at p 4 and 5, and about 100 more for each NOP after that. A second RAM load took 1,676 to 1,683 at p 4 and 5 and 1,957 at p 8, and an I_STAT load took 1,655 to 1,659 and 1,955.1
Two to six RAM loads back to back took about 1,480, 2,088, 2,698, 3,320 and 3,916 cycles. Each further load therefore added about 6 cycles to a turn. LW, LBU and LH gave the same times, whether the loads read one word, words 40h apart or a new word on every turn.1
Branches
A RAM load, 4 NOPs and a second RAM load took 1,681 cycles. With a taken backward BEQ path between the loads the row took 1,763, and 1 to 3 NOPs before the second load brought it to 1,765, 1,882 and 1,962. A BNE that is not taken in the same place gave 1,683. A two-turn inner loop of k instructions and a backward BNE took 1,555, 1,755 and 1,955 cycles for k 1 to 3.1
Uncached Code
Run from KSEG1, a load and an ADDU of its value with no NOP between them took 3,858 cycles for a RAM load, 3,535 for I_STAT and 3,252 for the scratchpad. For the scratchpad load each NOP added about 610 cycles, or 6 cycles a turn. For the RAM and I_STAT loads the second NOP added only 420 and 325 cycles. Two stores, k NOPs and a jump took 5,826 to 5,832 cycles at k 0 and about 8,250 at k 4. J, JR, JAL, a taken BEQ and a BEQ that is not taken all gave the same time within 20 cycles.1
The UFP rows store zero to the mode of root counter 2, which also zeroes its count, and read the count n NOPs later. From the cache the count read 0 at n 0 and n minus 1 from n 1 on. From KSEG1 the count read 4 plus 6 for each NOP: 4, 10, 16 and so on up to 52 at n 8. A few reads were 4 to 6 higher.1
| n | KSEG1 | Cache |
|---|---|---|
| 0 | 4 | 0 |
| 1 | 10 | 0 |
| 2 | 16 | 1 |
| 4 | 28 | 3 |
| 8 | 52 | 7 |
GP0 Stores and Polls
64 stores to GP0 back to back took 6,453 cycles for 50 turns, and the empty loop took 205. Each store therefore took about 1.95 cycles. 8, 16 and 32 stores each followed by a NOP took 1,955, 3,555 and 6,760 cycles for 100 turns, and the empty loop took 355. Each store and its NOP therefore took 2 cycles. A GPUSTAT poll turn took 1,357 cycles for 100 turns, and a root counter 2 poll turn 1,255.1
Register Upper Halves
RAM_SIZE (1F801060h) was read with LW after an I_MASK store. The store sits k words before line B, the cache line that holds the load, and at k 0 it is line B's first word. With no store the upper half read 3C00h cold, the upper half of line B's last word, and 8011h warm. At k 0, 1 and 2 it read 0000h cold, and warm it read the upper half of the stored value, AFA2h or ABCDh. At k 3 and 4 it read as with no store. All six runs of each row gave the same value.1
I_MASK was read after an SW of 12345678h and one other access. With the access to the BIOS, GPUSTAT, the scratchpad or I_STAT, the upper half read 0000h cold, and with 4 NOPs or a root counter 2 read it read 03E0h cold. Warm it read 6E6Eh or 7F7Fh when a RAM word of 6E6E1111h or 7F7F2222h was read before the store, and 3C03h otherwise. The value 1234h was never read. An LBU of the top byte read the high byte of the same halfword.1
Root counter 1 counted system clock cycles in the TIO rows. Two loads of it back to back read 4 apart warm wherever the first load sat in its cache line. Cold, they read 4 apart at words 0, 2 and 3 and 11 apart at word 1.1
Interrupt on RTPS
A root counter 2 interrupt at target n was taken by a handler that returns to EPC. For n 20 to 30 EPC pointed 11 to 1 words before the RTPS, and SXY2 in the handler held its old value. At n 31 EPC pointed at the RTPS itself, the word at EPC read 4A180001h, SXY2 in the handler already held the new value and the screen XY FIFO had shifted twice after the return. RTPS had therefore run once before the exception and again after the return. From n 32 on EPC pointed past the RTPS, SXY2 held the new value and the FIFO shifted once. FLAG read 80020000h in every row.1
With root counter 2 read before the RTPS, EPC pointed one word before the RTPS for targets 30 to 34 and at the RTPS at target 35. The FIFO again shifted twice at that target and once at every other. With a NOP in place of the RTPS the same targets gave the same EPC offsets, and the FIFO did not shift.2
Cache Isolation
After a routine of LUI $0 words ran from the cache, an isolated load of its word 0 and word 5 read the code words 3C00A000h and 3C00A005h. A word 30h on that never ran read 00000000h. An address 1000h on, in the same cache line with another tag, read 3C00A000h, while memory there held 00000000h. A data word read 00000000h isolated where memory held 11111111h. Both passes gave the same values.1
The program ran an isolated load, store and load from cached code, and the console did not hang. The cache word read 00000000h before, the isolated load read 7FEF0000h, and memory held 11111111h after.1
Runs
3 October 2026
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
15 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 00000480 BDAM 00000000
BPCM 00000000 SR 00000000 Cause 00000020 EPC 8002178C PRId 00000002
===== 01 SNL F15 STORE N LOAD | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
100 turns of a RAM store, n instructions, a load, nop (q14; cpu6 01SLS: sw, 5-8 NOPs,
lw 1484 1575 1667 1774). Path: beq over, n-4 NOPs, beq back to the lw (cpu4 03BRK).
sw, n NOPs, RAM lw (n 3-9): 1475 1479 1478 1567 1665 1764 1875
sh, n NOPs, RAM lw (n 3-9): 1475 1479 1480 1562 1665 1763 1872
sb, n NOPs, RAM lw (n 3-9): 1476 1478 1480 1571 1665 1763 1872
sw, path, RAM lw (n 4-9): 1478 1562 1662 1763 1873 1960
sh, path, RAM lw (n 4-9): 1479 1562 1666 1763 1877 1957
sb, path, RAM lw (n 4-9): 1480 1562 1666 1760 1875 1957
sw, n NOPs, scratchpad lw (n 3-9): 955 1055 1155 1259 1355 1455 1555
sh, n NOPs, scratchpad lw (n 3-9): 955 1055 1157 1255 1355 1455 1555
sb, n NOPs, scratchpad lw (n 3-9): 955 1055 1155 1259 1355 1455 1555
Done.
===== 02 IOA F15 AFTER IO LOAD | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
100 turns of an IO lw, n NOPs (0 to 4), a second lw, nop (q15; cpu4 01IOP: lw, 4 NOPs,
lw 1455 1450 1449 1449; cpu3 01LLP: I_STAT lw, lw 1055).
I_STAT lw, n NOPs, the same lw: 1155 1355 1355 1355 1455
I_STAT lw, n NOPs, RAM lw: 1276 1480 1478 1474 1572
I_STAT lw, n NOPs, scratchpad lw: 955 1155 1155 1155 1255
GPUSTAT lw, n NOPs, the same lw: 1156 1355 1355 1355 1459
GPUSTAT lw, n NOPs, RAM lw: 1276 1471 1479 1469 1558
GPUSTAT lw, n NOPs, scratchpad lw: 955 1155 1160 1155 1255
DPCR lw, n NOPs, the same lw: 1155 1355 1361 1355 1455
DPCR lw, n NOPs, RAM lw: 1276 1471 1479 1469 1558
DPCR lw, n NOPs, scratchpad lw: 955 1155 1155 1155 1255
timer 2 lw, n NOPs, the same lw: 1156 1355 1355 1355 1459
timer 2 lw, n NOPs, RAM lw: 1276 1471 1479 1469 1558
timer 2 lw, n NOPs, scratchpad lw: 955 1155 1160 1155 1255
Done.
===== 03 LDL F15 LOAD LANDS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
100 turns of a RAM lw, p NOPs (4 to 8), one access, 2 NOPs (q16; chain m LND p 6 sw
1567, p 6 and 7 lw 1762 1874).
RAM sw: 1478 1477 1562 1661 1759
RAM sh: 1471 1477 1562 1655 1761
RAM sb: 1478 1476 1558 1655 1761
scratchpad sw: 1479 1479 1559 1655 1760
RAM lw: 1683 1676 1767 1881 1957
scratchpad lw: 1479 1479 1562 1659 1757
I_STAT lw: 1655 1659 1758 1869 1955
Done.
===== 04 BKB F15 BACK BEQ | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
100 turns, RAM loads (q17; cpu4 03BRK: lw, 4 NOPs, lw, nop 1685; backward beq path 1783;
chain m BBR k 1-3 within 10 of the emulator).
lw, 4 NOPs, lw, nop: 1681
03BRK backward beq path, then 1, 2, 3 NOPs before the second lw: 1763 1765 1882 1962
lw, 2 NOPs, bne $0,$0 back (not taken), nop, lw, nop: 1683
chain m BBR (followup10.c:252-268) k 1, 2, 3: 1555 1755 1955
Done.
===== 05 KLU F15 KSEG1 USE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
100 turns from KSEG1 of a lw, n NOPs (0 to 3), addu of it (q18; chain m KST RAM lw, nop,
use 4453, I_STAT 4135).
RAM lw, n NOPs, addu: 3858 4465 4885 5490
I_STAT lw, n NOPs, addu: 3535 4135 4460 5068
scratchpad lw, n NOPs, addu: 3252 3853 4466 5078
Done.
===== 06 KSJ F15 KSEG1 JUMP | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
100 turns from KSEG1 of sw, sw, k NOPs (0 to 4), then a jump or branch over one word (q19;
chain m KST: sw, sw, 1 NOP, taken beq 6445); RAM lw, RAM sw, k NOPs (0 to 2).
sw, sw, k NOPs, j: 5826 6462 7035 7652 8246
sw, sw, k NOPs, jr: 5827 6459 7036 7656 8255
sw, sw, k NOPs, jal: 5827 6459 7040 7652 8254
sw, sw, k NOPs, taken beq: 5828 6471 7045 7655 8261
sw, sw, k NOPs, beq not taken: 5832 6463 7051 7658 8260
RAM lw, RAM sw, k NOPs: 4266 4885 5494
Done.
===== 07 UFP F15 FETCH PUSH | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
sh zero to timer 2's mode (it zeroes the count), n NOPs (0 to 8), lhu of the count: from
KSEG1, then from the cache (warm), 16 runs each (q20).
n 0 KSEG1: 4 4 4 4 4 8 4 4 4 4 4 4 4 4 4 4
n 0 cached: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n 1 KSEG1: 10 10 10 10 10 10 10 10 14 10 10 10 10 10 10 10
n 1 cached: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
n 2 KSEG1: 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
n 2 cached: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
n 3 KSEG1: 22 27 22 22 22 22 22 22 22 22 22 22 26 22 22 22
n 3 cached: 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
n 4 KSEG1: 28 28 28 28 28 28 28 28 28 32 28 28 28 28 28 28
n 4 cached: 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
n 5 KSEG1: 34 34 38 34 34 38 34 34 39 34 34 34 34 34 34 34
n 5 cached: 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
n 6 KSEG1: 40 40 40 45 40 40 45 40 40 45 40 40 45 40 40 45
n 6 cached: 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5
n 7 KSEG1: 46 46 46 50 46 46 50 46 46 46 46 51 46 46 50 46
n 7 cached: 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
n 8 KSEG1: 52 52 58 52 52 52 52 56 52 52 52 52 57 52 52 52
n 8 cached: 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
Done.
===== 08 BBL F15 BACK TO BACK | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
100 turns of k RAM loads back to back (k 2 to 6), then 1 NOP (q21; chain k LLN 3 and 4 lw
2068 and 2689). Walking: word i of the turn, the base 4k on each turn.
lw, one word: 1481 2086 2695 3323 3916
lw, words 40h apart: 1480 2088 2695 3320 3914
lw, walking words: 1473 2086 2699 3324 3916
lbu, one word: 1480 2086 2701 3320 3921
lbu, words 40h apart: 1478 2088 2699 3320 3918
lbu, walking words: 1481 2088 2704 3324 3923
lh, one word: 1480 2088 2697 3320 3914
lh, words 40h apart: 1472 2089 2701 3320 3922
lh, walking words: 1481 2088 2704 3318 3917
Done.
===== 09 MFL F15 MASK FILL | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
RAM_SIZE's upper half read after an I_MASK store k words before line B (k 0 to 4; cpu 07MIR:
0000 at 1 and 2, 3C00 at 3). Six runs cold (FlushCache) / warm; line B 8C82 2400 3400 3C00.
no store: cold 3C00 3C00 3C00 3C00 3C00 3C00 / warm 8011 8011 8011 8011 8011 8011
I_MASK AFA20009, k 0: cold 0000 0000 0000 0000 0000 0000 / warm AFA2 AFA2 AFA2 AFA2 AFA2 AFA2
I_MASK AFA20009, k 1: cold 0000 0000 0000 0000 0000 0000 / warm AFA2 AFA2 AFA2 AFA2 AFA2 AFA2
I_MASK AFA20009, k 2: cold 0000 0000 0000 0000 0000 0000 / warm AFA2 AFA2 AFA2 AFA2 AFA2 AFA2
I_MASK AFA20009, k 3: cold 3C00 3C00 3C00 3C00 3C00 3C00 / warm 8011 8011 8011 8011 8011 8011
I_MASK AFA20009, k 4: cold 3C00 3C00 3C00 3C00 3C00 3C00 / warm 8011 8011 8011 8011 8011 8011
I_MASK ABCD0009, k 0: cold 0000 0000 0000 0000 0000 0000 / warm ABCD ABCD ABCD ABCD ABCD ABCD
I_MASK ABCD0009, k 1: cold 0000 0000 0000 0000 0000 0000 / warm ABCD ABCD ABCD ABCD ABCD ABCD
I_MASK ABCD0009, k 2: cold 0000 0000 0000 0000 0000 0000 / warm ABCD ABCD ABCD ABCD ABCD ABCD
I_MASK ABCD0009, k 3: cold 3C00 3C00 3C00 3C00 3C00 3C00 / warm 8011 8011 8011 8011 8011 8011
I_MASK ABCD0009, k 4: cold 3C00 3C00 3C00 3C00 3C00 3C00 / warm 8011 8011 8011 8011 8011 8011
Done.
===== 10 IMU F15 IMASK UPPER | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
I_MASK after sw 12345678h, an access, the read: its upper half (lbu+3 its top byte), cold /
warm (02SIM warm read 27BD). v0 none, v1 RAM 6E6E1111h read first, v2 7F7F2222h, v3 27BD0000h.
f BIOS, lw: v0 0000/3C03 v1 0000/6E6E v2 0000/7F7F v3 0000/3C03
f BIOS, lhu+2: v0 0000/3C03 v1 0000/6E6E v2 0000/7F7F v3 0000/3C03
f BIOS, lbu+3: v0 0000/003C v1 0000/006E v2 0000/007F v3 0000/003C
g GPUSTAT, lw: v0 0000/3C03 v1 0000/6E6E v2 0000/7F7F v3 0000/3C03
g GPUSTAT, lhu+2: v0 0000/3C03 v1 0000/6E6E v2 0000/7F7F v3 0000/3C03
g GPUSTAT, lbu+3: v0 0000/003C v1 0000/006E v2 0000/007F v3 0000/003C
h scratchpad, lw: v0 0000/3C03 v1 0000/6E6E v2 0000/7F7F v3 0000/3C03
h scratchpad, lhu+2: v0 0000/3C03 v1 0000/6E6E v2 0000/7F7F v3 0000/3C03
h scratchpad, lbu+3: v0 0000/003C v1 0000/006E v2 0000/007F v3 0000/003C
i I_STAT, lw: v0 0000/3C03 v1 0000/6E6E v2 0000/7F7F v3 0000/3C03
i I_STAT, lhu+2: v0 0000/3C03 v1 0000/6E6E v2 0000/7F7F v3 0000/3C03
i I_STAT, lbu+3: v0 0000/003C v1 0000/006E v2 0000/007F v3 0000/003C
k 4 NOPs, lw: v0 03E0/3C03 v1 03E0/6E6E v2 03E0/7F7F v3 03E0/3C03
k 4 NOPs, lhu+2: v0 03E0/3C03 v1 03E0/6E6E v2 03E0/7F7F v3 03E0/3C03
k 4 NOPs, lbu+3: v0 0003/003C v1 0003/006E v2 0003/007F v3 0003/003C
l timer 2, lw: v0 03E0/3C03 v1 03E0/6E6E v2 03E0/7F7F v3 03E0/3C03
l timer 2, lhu+2: v0 03E0/3C03 v1 03E0/6E6E v2 03E0/7F7F v3 03E0/3C03
l timer 2, lbu+3: v0 0003/003C v1 0003/006E v2 0003/007F v3 0003/003C
Done.
===== 11 TIO F15 TWO IO LOADS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Two timer 1 lw back to back (timer 1 at the system clock), the first at word w of a cache
line: the two counts read, cold (FlushCache) / warm, three runs (q24; 07JBD 4/4/11/4).
word 0: cold 16290 16294 58648 58652 35471 35475 / warm 43518 43522 47754 47758 52007 52011
word 1: cold 7586 7597 49499 49510 26328 26339 / warm 34385 34389 38620 38624 42864 42868
word 2: cold 63998 64002 40828 40832 17662 17666 / warm 25715 25719 29960 29964 34208 34212
word 3: cold 55344 55348 32169 32173 9010 9014 / warm 16603 16607 20852 20856 25110 25114
Done.
===== 12 PLC F15 POLL COSTS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
GP0(00h) stores (a NOP, gpu/i-o-ports-dma-channels-commands-vram.txt:33) and poll turns
(q25; console 12.4 a GP0 store, poll 108, timer poll turn 112).
50 turns: nothing 205; 64 GP0 sw back to back 6453
100 turns: nothing 355; 8 GP0 sw, a NOP after each 1955; 16 GP0 sw, a NOP after each 3555; 32 GP0 sw, a NOP after each 6760
100 turns: GPUSTAT lw, nop, and bit 28, beq not taken, nop, nop 1357
100 turns: timer 2 lhu, nop, bne taken over one, nop 1255
Done.
===== 13 IGT F15 IRQ ON GTE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Timer 2 IRQ at target n (mode 0010h: IRQ at target, one-shot, pulse, timers.txt:26-30) onto
a cached RTPS 40 NOPs after the mode write, taken by our handler, which returns to EPC.
Kernel's 80000080h: 3C1A0000 275A0C80 03400008 00000000
n: EPC from RTPS in words / word at EPC / SXY2 and FLAG in the handler / timer 2 there /
fifo shifts after the return (0, 1, 2; 9 other). SXY2 old 00030003, new about 00CC0199.
no IRQ: SXY 00020002 00030003 006300C7 FLAG 80020000
20: -11 00000000 00030003 80020000 199 1
21: -10 00000000 00030003 80020000 195 1
22: -9 00000000 00030003 80020000 191 1
23: -8 00000000 00030003 80020000 196 1
24: -7 00000000 00030003 80020000 193 1
25: -6 00000000 00030003 80020000 198 1
26: -5 00000000 00030003 80020000 195 1
27: -4 00000000 00030003 80020000 202 1
28: -3 00000000 00030003 80020000 197 1
29: -2 00000000 00030003 80020000 203 1
30: -1 00000000 00030003 80020000 199 1
31: 0 4A180001 006300C7 80020000 205 2
32: 1 00000000 006300C7 80020000 207 1
33: 2 00000000 006300C7 80020000 206 1
34: 3 00000000 006300C7 80020000 203 1
35: 4 00000000 006300C7 80020000 204 1
36: 5 00000000 006300C7 80020000 205 1
37: 6 00000000 006300C7 80020000 206 1
38: 7 00000000 006300C7 80020000 212 1
39: 8 00000000 006300C7 80020000 213 1
40: 9 00000000 006300C7 80020000 214 1
41: 10 00000000 006300C7 80020000 216 1
42: 11 00000000 006300C7 80020000 211 1
43: 12 00000000 006300C7 80020000 212 1
44: 13 00000000 006300C7 80020000 213 1
45: 14 00000000 006300C7 80020000 214 1
46: 15 00000000 006300C7 80020000 215 1
47: 16 00000000 006300C7 80020000 216 1
48: 17 00000000 006300C7 80020000 217 1
49: 18 00000000 006300C7 80020000 218 1
50: 19 00000000 006300C7 80020000 219 1
51: 20 00000000 006300C7 80020000 220 1
52: 21 00000000 006300C7 80020000 221 1
53: 22 00000000 006300C7 80020000 222 1
54: 23 00000000 006300C7 80020000 223 1
55: 24 00000000 006300C7 80020000 224 1
56: 25 00000000 006300C7 80020000 225 1
57: 26 00000000 006300C7 80020000 226 1
58: 27 00000000 006300C7 80020000 227 1
59: 28 00000000 006300C7 80020000 228 1
Kernel's vector back: 3C1A0000
Done.
===== 14 IS2 F15 ISOLATE STEP 2 | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Cache isolation step 2: FlushCache, a routine run from the cache, then an isolated lw from
uncached code (cpu_core.c iso_load) at five addresses (q26; chain h read 8FA40254).
routine word 0 80113AA0: isolated 3C00A000, memory 3C00A000
routine word 5 80113AB4: isolated 3C00A005, memory 3C00A005
routine +30h, never run 80113AD0: isolated 00000000, memory 00000000
routine +1000h, same line, other tag 80114AA0: isolated 3C00A000, memory 00000000
a data word 8010FCE4: isolated 00000000, memory 11111111
routine word 0 80113AA0: isolated 3C00A000, memory 3C00A000
routine word 5 80113AB4: isolated 3C00A005, memory 3C00A005
routine +30h, never run 80113AD0: isolated 00000000, memory 00000000
routine +1000h, same line, other tag 80114AA0: isolated 3C00A000, memory 00000000
a data word 8010FCE4: isolated 00000000, memory 11111111
Done.
===== 15 IS4 F15 ISOLATE STEP 4 | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Cache isolation step 4: step 3 (isolated lw, sw 22222222, lw, sw back) from cached code.
It hung the 5501 on 2026-09-26 with nothing after its label (14ISO.txt:8).
4 the same from cached code: cache word before 00000000, read 7FEF0000, memory after 11111111
Done.
5 October 2026
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR 801090B4 DCIC 00000000 BadVaddr 00000480 BDAM 00000000
BPCM 00000000 SR 40000000 Cause 00000020 EPC 80109C20 PRId 00000002
===== 01 IG2 F15 IRQ ON GTE TIMED | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
IGT again (row 58): timer 2 read before the RTPS and first in the handler; then a NOP in
the RTPS's place. n: EPC from the RTPS in words / timer 2 before it / at the handler's
entry / at IGT's place in it / fifo shifts.
RTPS:
20: -11 80 60 224 1
21: -10 160 61 225 1
22: -9 160 66 225 1
23: -8 160 63 226 1
24: -7 160 64 229 1
25: -6 160 69 228 1
26: -5 160 66 229 1
27: -4 160 67 231 1
28: -3 160 68 227 1
29: -2 160 69 233 1
30: -1 37 78 237 1
31: -1 37 74 237 1
32: -1 37 80 239 1
33: -1 37 74 238 1
34: -1 37 74 237 1
35: 0 160 75 239 2
36: 1 160 76 240 1
37: 2 160 77 236 1
38: 3 160 78 242 1
39: 4 160 79 244 1
40: 5 160 80 243 1
41: 6 160 81 240 1
42: 7 160 82 245 1
43: 8 160 83 247 1
44: 9 160 84 248 1
45: 10 160 85 244 1
46: 11 160 86 249 1
47: 12 160 87 250 1
48: 13 160 91 250 1
49: 14 160 89 252 1
50: 15 160 90 249 1
51: 16 160 91 254 1
52: 17 160 92 257 1
53: 18 160 93 252 1
54: 19 160 94 258 1
55: 20 160 95 260 1
56: 21 160 96 255 1
57: 22 160 97 260 1
58: 23 160 98 262 1
59: 24 160 99 258 1
NOP in its place:
20: -11 84 60 223 0
21: -10 160 61 224 0
22: -9 160 66 225 0
23: -8 160 63 222 0
24: -7 160 64 228 0
25: -6 160 65 227 0
26: -5 160 66 230 0
27: -4 160 71 230 0
28: -3 160 68 227 0
29: -2 160 69 232 0
30: -1 37 74 238 0
31: -1 37 80 239 0
32: -1 37 74 233 0
33: -1 37 74 236 0
34: -1 37 74 237 0
35: 0 160 75 234 0
36: 1 160 76 240 0
37: 2 160 77 236 0
38: 3 160 78 242 0
39: 4 160 79 242 0
40: 5 160 86 245 0
41: 6 160 81 245 0
42: 7 160 82 241 0
43: 8 160 83 246 0
44: 9 160 84 248 0
45: 10 160 89 248 0
46: 11 160 86 251 0
47: 12 160 87 250 0
48: 13 160 88 251 0
49: 14 160 89 252 0
50: 15 160 90 249 0
51: 16 160 91 254 0
52: 17 160 92 251 0
53: 18 160 93 258 0
54: 19 160 94 253 0
55: 20 160 95 258 0
56: 21 160 96 255 0
57: 22 160 97 260 0
58: 23 160 98 257 0
59: 24 160 99 263 0
Kernel's vector back: 3C1A0000
Done.