DMA Channel 6 Ordering Table Clear
Checks how DMA channel 6 clears an ordering table and which of its control bits are fixed.
| Machine | SCPH-5501 |
|---|---|
| Program | dma/otc-test (ps1-tests) |
This is an old revision of this page, as edited by RemmyLee at 05:11, 23 October 2026. Edit this revision | Latest revision
Overview
Channel 6 of the DMA controller writes an ordering table into RAM: each entry points to the entry before it, and the last entry holds the end marker. The program starts it with CHCR 11000002h, the value libgpu's ClearOTagR uses, and changes one field per check: the sync mode, the start bit, the direction and the step. It also writes test patterns to CHCR to find the fixed bits, reads CHCR after a transfer with and without chopping, and runs a transfer with the master enable clear.1
Results
The SCPH-5501 passed all 15 checks in every run.2
Channel 6 wrote the same table whatever the direction, step and sync mode fields said. With CHCR 11000002h and four entries, each entry held the address of the one before it and the first entry held FFFFFFh. The table came out the same with the direction bit set (from RAM), with the step bit clear (forward) and in sync modes 1, 2 and 3. A block count of 0 cleared 65,536 entries.2
The channel did not start without bit 28 or without bit 24, and it did not start with its enable bit in DPCR clear. In those three cases the memory kept its old contents.2
Only bits 30, 28 and 1 of CHCR kept the value written. A write of 70770703h read 50000002h, a write of 0 read 00000002h, and a write of 8E88F8FCh read 00000002h. Bit 1 therefore reads one at all times.2
CHCR read 00000002h straight after the start of a 32,768-entry clear. It read the same with chopping set (00110100h added), and the table was complete at that read.2
Runs
25 September 2026
===== 06 OTC DMA OTC | BIOS 19951204 System ROM Version 3.0 11/18/96 A
dma/otc-test (DMA Channel 6)
pass - testOtcStandard
pass - testOtcBigTransfer
pass - testOtcWontStartOnAutomaticMode
pass - testOtcWontStartWithoutStartFlag
pass - testOtcForward
pass - testOtcFromRam
pass - testOtcSyncModeBlocks
pass - testOtcSyncModeLinkedList
pass - testOtcSyncModeReserved
pass - testOtcWhichBitsAreHardwiredToZero
pass - testOtcWhichBitsAreHardwiredToOne
pass - testOtcUnusedControlBitsAreAlwaysZero
pass - testOtcControlBitsAfterTransfer
pass - testOtcControlBitsAfterTransferWithChopping
pass - testOtcStandardWithMasterDisabled
Done.
27 September 2026
===== 06 OTC DMA OTC | BIOS 19951204 System ROM Version 3.0 11/18/96 A
dma/otc-test (DMA Channel 6)
pass - testOtcStandard
pass - testOtcBigTransfer
pass - testOtcWontStartOnAutomaticMode
pass - testOtcWontStartWithoutStartFlag
pass - testOtcForward
pass - testOtcFromRam
pass - testOtcSyncModeBlocks
pass - testOtcSyncModeLinkedList
pass - testOtcSyncModeReserved
pass - testOtcWhichBitsAreHardwiredToZero
pass - testOtcWhichBitsAreHardwiredToOne
pass - testOtcUnusedControlBitsAreAlwaysZero
pass - testOtcControlBitsAfterTransfer
pass - testOtcControlBitsAfterTransferWithChopping
pass - testOtcStandardWithMasterDisabled
Done.
27 September 2026 run 2
===== 06 OTC DMA OTC | BIOS 19951204 System ROM Version 3.0 11/18/96 A
dma/otc-test (DMA Channel 6)
pass - testOtcStandard
pass - testOtcBigTransfer
pass - testOtcWontStartOnAutomaticMode
pass - testOtcWontStartWithoutStartFlag
pass - testOtcForward
pass - testOtcFromRam
pass - testOtcSyncModeBlocks
pass - testOtcSyncModeLinkedList
pass - testOtcSyncModeReserved
pass - testOtcWhichBitsAreHardwiredToZero
pass - testOtcWhichBitsAreHardwiredToOne
pass - testOtcUnusedControlBitsAreAlwaysZero
pass - testOtcControlBitsAfterTransfer
pass - testOtcControlBitsAfterTransferWithChopping
pass - testOtcStandardWithMasterDisabled
Done.
27 September 2026 run 3
===== 06 OTC DMA OTC | BIOS 19951204 System ROM Version 3.0 11/18/96 A
dma/otc-test (DMA Channel 6)
pass - testOtcStandard
pass - testOtcBigTransfer
pass - testOtcWontStartOnAutomaticMode
pass - testOtcWontStartWithoutStartFlag
pass - testOtcForward
pass - testOtcFromRam
pass - testOtcSyncModeBlocks
pass - testOtcSyncModeLinkedList
pass - testOtcSyncModeReserved
pass - testOtcWhichBitsAreHardwiredToZero
pass - testOtcWhichBitsAreHardwiredToOne
pass - testOtcUnusedControlBitsAreAlwaysZero
pass - testOtcControlBitsAfterTransfer
pass - testOtcControlBitsAfterTransferWithChopping
pass - testOtcStandardWithMasterDisabled
Done.
27 September 2026 run 4
===== 06 OTC DMA OTC | BIOS 19951204 System ROM Version 3.0 11/18/96 A
dma/otc-test (DMA Channel 6)
pass - testOtcStandard
pass - testOtcBigTransfer
pass - testOtcWontStartOnAutomaticMode
pass - testOtcWontStartWithoutStartFlag
pass - testOtcForward
pass - testOtcFromRam
pass - testOtcSyncModeBlocks
pass - testOtcSyncModeLinkedList
pass - testOtcSyncModeReserved
pass - testOtcWhichBitsAreHardwiredToZero
pass - testOtcWhichBitsAreHardwiredToOne
pass - testOtcUnusedControlBitsAreAlwaysZero
pass - testOtcControlBitsAfterTransfer
pass - testOtcControlBitsAfterTransferWithChopping
pass - testOtcStandardWithMasterDisabled
Done.
28 September 2026
===== 06 OTC DMA OTC | BIOS 19951204 System ROM Version 3.0 11/18/96 A
dma/otc-test (DMA Channel 6)
pass - testOtcStandard
pass - testOtcBigTransfer
pass - testOtcWontStartOnAutomaticMode
pass - testOtcWontStartWithoutStartFlag
pass - testOtcForward
pass - testOtcFromRam
pass - testOtcSyncModeBlocks
pass - testOtcSyncModeLinkedList
pass - testOtcSyncModeReserved
pass - testOtcWhichBitsAreHardwiredToZero
pass - testOtcWhichBitsAreHardwiredToOne
pass - testOtcUnusedControlBitsAreAlwaysZero
pass - testOtcControlBitsAfterTransfer
pass - testOtcControlBitsAfterTransferWithChopping
pass - testOtcStandardWithMasterDisabled
Done.
References
-
^ ps1-tests, dma/otc-test. https://github.com/JaCzekanski/ps1-tests.
-
^ a b c d e SCPH-5501 output: main/06OTC.txt and the files beside it, with the other runs listed under Runs.