CPU Speed During a DMA2 List
Measures CPU loops during a DMA2 list, the BIOS shell loops that race the list at the logo, and the end of the MDEC busy bit after a table.
| Machine | SCPH-5501 |
|---|---|
| Program | followup5 |
This is an old revision of this page, as edited by RemmyLee at 05:41, 23 October 2026. Edit this revision | Latest revision
Overview
While the BIOS logo shows, the shell's code builds a primitive in RAM while DMA2 still walks the ordering table that holds it, and the display is right only if DMA2 passes that primitive first. The program times the code that runs in that window during a DMA2 list of 1024 empty nodes.1
Every time here is root counter 2 on the 33.8688 MHz clock, and the program reads it with loads only. A timer write is not used to start the stopwatch, because the Instruction Fetch During DMA2 test found such a write held behind a running list. Each row runs alone after one warm call, and during a list that starts just before the timed call.1
| Tag | Group |
|---|---|
| TBF | MDEC status read 0 to 20 NOPs after a table's last word |
| PLS | A CHCR2 poll loop of 200 turns in four shapes |
| SHL | The BIOS shell's own loops, from the instruction words in ROM |
| HCR | A timer write followed by 0 to 8 cached NOPs and then KSEG1 code |
| RCE | The logo race end to end |
See also:
Results
MDEC Busy After a Table
Read 0 to 3 NOPs after a quantization table's last word, at 13 to 20 cycles, the status was A004FFFFh. From 4 NOPs on, at 20 cycles and later, it was 8004FFFFh. Bit 29 therefore clears about 20 cycles after the last word.1
Poll Loops
A poll loop of 200 turns took 2,670 cycles alone and about 4,105 during a list. Using the loaded value 3 or 4 instructions after the load made the loop 2,870 cycles alone and left the time during the list unchanged.1
BIOS Shell Loops
The shell's loop L1 ran 35 turns in about 1,920 cycles alone and about 2,755 during a list. L2 ran 24 turns in 683 cycles alone and about 1,055 during a list. The byte copy of 58h bytes took about 1,395 cycles alone and about 2,400 during a list. All three in a row took about 3,865 cycles alone and about 5,865 during a list.1
Held Timer Write
A timer 2 mode write followed by 256 NOPs from KSEG1 counted about 1,575 cycles alone. During a list it counted 8 or 9 for every count of 0 to 8 cached NOPs before the KSEG1 code. The cached NOPs did not release the held write.1
Logo Race
The CPU ran L1 n times, L2 24 times and then the byte copy over the primitive's header. DMA2 read the primitive after the copy for every n up to the row whose copy ended at 12,097 cycles after the list started. From the row whose copy ended at 12,399 cycles on, DMA2 had read the primitive before the copy. The list ended at 12,529 and 12,553 cycles in those two rows.1
Runs
30 September 2026
===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
5 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 00000480 BDAM 00000000
BPCM 00000000 SR 00000000 Cause 00000020 EPC 80016C84 PRId 00000002
===== 01 TBF F5 MDEC TABLE BUSY | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
Quant, luminance (40000000h and 16 words): timer 2 zeroed just before the last word,
k NOPs, then MDEC1 and timer 2. status@timer for each k.
k0 A004FFFF@13 k1 A004FFFF@13 k2 A004FFFF@13 k3 A004FFFF@20 k4 8004FFFF@20 k5 8004FFFF@24 k6 8004FFFF@24 k7 8004FFFF@28 k8 8004FFFF@29 k9 8004FFFF@29 k10 8004FFFF@35 k11 8004FFFF@37 k12 8004FFFF@38 k13 8004FFFF@38 k14 8004FFFF@38 k15 8004FFFF@50 k16 8004FFFF@51 k17 8004FFFF@51 k18 8004FFFF@51 k19 8004FFFF@55 k20 8004FFFF@56
k0 A004FFFF@13 k1 A004FFFF@13 k2 A004FFFF@13 k3 A004FFFF@20 k4 8004FFFF@20 k5 8004FFFF@20 k6 8004FFFF@20 k7 8004FFFF@28 k8 8004FFFF@29 k9 8004FFFF@29 k10 8004FFFF@33 k11 8004FFFF@37 k12 8004FFFF@38 k13 8004FFFF@38 k14 8004FFFF@38 k15 8004FFFF@50 k16 8004FFFF@51 k17 8004FFFF@51 k18 8004FFFF@51 k19 8004FFFF@55 k20 8004FFFF@56
Done.
===== 02 PLS F5 POLL SHAPES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
200 turns of a CHCR2 poll loop, cycles by timer 2, alone and straight after a DMA2 list
of 1024 empty nodes starts (CHCR 01000401, GP1(04h)=2); list done counted from the start.
run_timed's loop, value used 2 on (lw, nop, and): alone 2670, during 4105, list done at 10587; alone 2670, during 4109, list done at 10560;
value used 3 on: alone 2870, during 4112, list done at 10583; alone 2870, during 4092, list done at 10563;
value used 4 on: alone 2876, during 4103, list done at 10574; alone 2870, during 4111, list done at 10562;
value never used: alone 2670, during 4115, list done at 10586; alone 2679, during 4104, list done at 10571;
Done.
===== 03 SHL F5 SHELL LOOPS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
The BIOS shell's own loop words from ROM, as each ran in the logo race window; cycles by
timer 2 alone and straight after a DMA2 list of 1024 empty nodes starts.
L1 (800524DCh) 35 turns: alone 1923, during 2762, list done at 10981; alone 1915, during 2750, list done at 10967;
L2 (800531ACh) 24 turns: alone 683, during 1055, list done at 10759; alone 683, during 1056, list done at 10722;
byte copy (800308D0h) 58h bytes: alone 1398, during 2400, list done at 11035; alone 1391, during 2396, list done at 11008;
L1 35, L2 24, copy 58h in a row: alone 3851, during 5854, list done at 11605; alone 3881, during 5878, list done at 11580;
Done.
===== 04 HCR F5 HELD WRITE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
A timer 2 mode write (which zeroes it), k NOPs from the cache, 256 NOPs from KSEG1, then
the count: alone, and straight after a DMA2 list of 1024 empty nodes starts.
k 0: alone 1574, during 8; alone 1574, during 8;
k 1: alone 1574, during 8; alone 1574, during 8;
k 2: alone 1576, during 8; alone 1575, during 8;
k 3: alone 1582, during 8; alone 1578, during 8;
k 4: alone 1577, during 8; alone 1581, during 9;
k 5: alone 1579, during 8; alone 1578, during 8;
k 6: alone 1579, during 8; alone 1580, during 8;
k 7: alone 1580, during 8; alone 1580, during 8;
k 8: alone 1583, during 8; alone 1581, during 8;
Done.
===== 05 RCE F5 LOGO RACE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000480
OT of 1024 (ClearOTagR order, DMA2 from entry 1023 down), a 6 word prim linked from entry
2. The CPU runs L1 n times, L2 24, then copies 58h bytes over the prim's header, which
then links a node setting the texture page: 1 = DMA2 read the prim after the copy, 0 =
before. @ the copy's end and / the list's end, timer 2 from the list's start.
n from 0 by 4: 1@3251/11186 1@3468/11209 1@3758/11258 1@4039/11303 1@4332/11342 1@4608/11396 1@4916/11435 1@5198/11475 1@5478/11518 1@5774/11562 1@6046/11616 1@6309/11653 1@6641/11700 1@6918/11737 1@7201/11792 1@7504/11824 1@7793/11878 1@8079/11915 1@8367/11964 1@8646/12002 1@8945/12056 1@9231/12083 1@9510/12134 1@9796/12181 1@10093/12217 1@10358/12264 1@10636/12305 1@10941/12344 1@11244/12386 1@11515/12424 1@11823/12479 1@12097/12529 0@12399/12553 0@12604/12650 0@12774/12818 0@12939/12983 0@13089/13133 0@13264/13308 0@13427/13475 0@13583/13627 0@13746/13790 0@13946/13990 0@14147/14191 0@14383/14427 0@14558/14606 0@14799/14843 0@14999/15043 0@15202/15246 0@15421/15469 0@15632/15678 0@15842/15886 0@16050/16094 0@16281/16325 0@16475/16519 0@16695/16739 0@16894/16938 0@17092/17138 0@17319/17363 0@17508/17552 0@17736/17781 0@17950/17994
n from 0 by 4: 1@3253/11187 1@3461/11212 1@3749/11255 1@4048/11302 1@4339/11347 1@4634/11405 1@4907/11436 1@5188/11489 1@5493/11518 1@5774/11562 1@6046/11616 1@6309/11653 1@6641/11700 1@6918/11737 1@7201/11792 1@7504/11824 1@7793/11878 1@8079/11915 1@8367/11964 1@8646/12002 1@8945/12056 1@9231/12083 1@9510/12134 1@9796/12181 1@10093/12217 1@10358/12264 1@10636/12305 1@10941/12344 1@11244/12386 1@11515/12424 1@11823/12479 1@12097/12529 0@12399/12553 0@12604/12650 0@12774/12818 0@12939/12983 0@13089/13133 0@13264/13308 0@13427/13475 0@13583/13627 0@13746/13790 0@13946/13990 0@14147/14191 0@14383/14427 0@14558/14606 0@14799/14843 0@14999/15043 0@15202/15246 0@15421/15469 0@15632/15678 0@15842/15886 0@16050/16094 0@16281/16325 0@16475/16519 0@16695/16739 0@16894/16938 0@17092/17138 0@17319/17363 0@17508/17552 0@17736/17781 0@17950/17994
Done.